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Two-dimensional transient simulations of drain lag and current collapse in GaN-based high-electron-mobility transistors W. D. Hu, X. S. Chen, F. Yin, J. B. Zhang, and W. Lu Citation: J. Appl. Phys. 105, 084502 (2009); doi: 10.1063/1.3106603 View online: http://dx.doi.org/10.1063/1.3106603 View Table of Contents: http://jap.aip.org/resource/1/JAPIAU/v105/i8 Published by the AIP Publishing LLC.

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JOURNAL OF APPLIED PHYSICS 105, 084502 共2009兲

Two-dimensional transient simulations of drain lag and current collapse in GaN-based high-electron-mobility transistors W. D. Hu,a兲 X. S. Chen,b兲 F. Yin, J. B. Zhang, and W. Luc兲 National Laboratory for Infrared Physics, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China

共Received 16 November 2008; accepted 23 February 2009; published online 17 April 2009兲 The intrinsic mechanisms of drain lag and current collapse in GaN-based high-electron-mobility transistors are studied by using two-dimensional numerical simulations. Simulated drain lag characteristics are in good agreement with reported experimental data. The dynamic pictures of trapping of hot electrons under drain-pulse voltages are discussed in detail. Hot-electron buffer-trapping effect plays an instrumental role in the current collapse mechanism. Polarization-induced interface charges have significant effect on the hot-electron buffer trapping and the current collapse can be weakened by increasing the interface charges. The trapped charges can accumulate at the drain-side gate edge, where the electric field significantly changes and gate-to-drain-voltage-dependent strain is induced, causing a notable current collapse. The simulation results show that the drain voltage range, beyond 5 V, is already in the field of the well-developed hot electron regime. The hot electrons can occupy a great number of traps at the drain-side gate edge leading to the current collapse at high drain bias 共around 10 V兲, where the hot-electron trapping effect dominates. By considering quantum-well high-electron-mobility transistors, we find that better electron localization can reduce the current collapse. © 2009 American Institute of Physics. 关DOI: 10.1063/1.3106603兴 I. INTRODUCTION

GaN-based high-electron-mobility transistors 共HEMTs兲 are attracting considerable attention as high-power and highfrequency devices for radar, avionics, and wireless basestation transmitters, thanks to the unique material properties of III-N material. However, radio frequency 共rf兲 draincurrent 共Ids兲 collapse is the major factor limiting the outputpower density at microwave frequencies in GaN-based HEMTs.1–4 Its detrimental consequences on device performance have been shown by using different experimental techniques, including measurements of pulsed Ids versus drain-source voltage 共Vds兲 characteristics, gate- and drain-lag transients, and rf response.4–8 There are two widely accepted possible explanations for current collapse or current dispersion: the virtual gate surface trapping model5,9,10 and buffer trapping of hot electrons model11,12 in GaN-based HEMTs. The buffer-trapping model has been confirmed by gated transmission line measurement on GaN-based transistors.9,13,14 In this case, bulk traps alter the distributions of the two-dimensional electron gas 共2DEG兲 in the active region and limit switching characteristics of the devices. In the virtual gate model, the virtual gate depletes the 2DEG and increases the parasitic source and/or drain resistance of the devices. The virtual gate model is a good explanation for unpassivated devices 共or not well passivated devices兲 where surface states are induced by processing damage.15,16 The current collapse and gate lag can be reduced, but cannot be eliminated completely by the surface passivation or gate a兲

Electronic mail: [email protected]. Electronic mail: [email protected]. c兲 Electronic mail: [email protected]. b兲

0021-8979/2009/105共8兲/084502/7/$25.00

insulator.17,18 This indicates that the buffer-trapping effect is a common phenomenon for GaN-based transistors, where the virtual gate effect can be ignored under some conditions. These current collapse or dispersion problems are being addressed by experimental studies that can produce epitaxyand processing-related improvements and simulations that can optimize device design. Numerical simulations, which can contain structural details such as layer thicknesses, doping profiles, and trap concentrations, provide key insights into device operations and the degradation mechanisms of the reliability. A detailed assessment of the effect and characterization of the relevant trap states is crucial for the optimization of nitride transistor performance. In previous theoretical works,15,19–21 effects of a donortype surface state and bulk traps on gate lag were studied on GaN-based HEMTs. Self-heating related thermal effects have also been theoretically studied by Turin and Balandin.22,23 However, the effects of hot electrons on drain lag have been ignored in the simulations and few numerical works24,25 have been reported on the drain lag simulation taking buffer trapping into consideration for GaN-based MESFET. Motivated by experimental results and previously proposed qualitative models, we present the results of numerical simulations that clearly show that buffer trapping could explain the observed feature of drain-current collapse and drain lag with a twodimensional device simulator.26 The pulse-on and pulsedown modes for drain lag simulations are presented and compared with the experimental observations respectively. In addition, it is shown that the quantum-well 共QW兲 HEMT structure is effective for suppressing the current collapse and drain lag.

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TABLE I. Calculated polarization-induced interface charges at the AlxGa共1−x兲N / GaN heterointerface with the three models for the devices A共x = 0.35兲 and B共x = 0.3兲. The spontaneous polarizations of GaN and AlN for the calculations are ⫺0.090 and −0.034 C / m2, respectively, from Ref. 32. The unit is cm−2. Models Vegard’s law Miller et al. model Bernardini and Fiorentini’s model Experimental report

Device A 13

1.977⫻ 10 1.818⫻ 1013 1.223⫻ 1013 ⬃1.2⫻ 1013 a

Device B 1.679⫻ 1013 1.527⫻ 1013 1.049⫻ 1013 ⬃1 ⫻ 1013 b

a

Reference 21. Reference 18.

b

FIG. 1. 共a兲 Cross-sectional structure of simulated GaN-based HEMT. The structure parameters of devices A and B are from Refs. 21 and 18, respectively. 共b兲 Bias circuit used in simulations with a transient source-drain voltage to obtain the drain current response vs time. 共c兲 Drain turn-on pulsing mode for device A. A fixed voltage is applied to the gate and the drain is pulsed from 0.1 V to Vdd. 共d兲 Drain turn-off pulsing mode for device B. A fixed voltage is applied to the gate. The drain is pulsed from 0.1 V to Vdd and changed back to 0.1 V. Then the drain voltage is left at 0.1 V for the rest of the simulation.

II. DEVICE DESCRIPTION AND SIMULATION MODEL

Figure 1共a兲 is the schematic of the simulated structure. Two kinds of device parameters from Ref. 21 共device A兲 and Ref. 18 共device B兲 are employed in the simulations for the purpose of comparison with experimental results. For device A, the undoped GaN and Al0.35Ga0.65N layer thicknesses are 1.5 ␮m and 29 nm, respectively. The gate length is 0.7 ␮m, whereas the gate-drain and gate-source spacings are 2 and 0.7 ␮m, respectively. For device B, the undoped GaN and Al0.3Ga0.7N layer thicknesses are 2 ␮m and 25 nm, respectively. The gate length is 1.0 ␮m, whereas the gate-drain and gate-source spacings are 2.4 and 1.5 ␮m, respectively. Two-dimensional simulations are performed using Sentaurus device 共previous ISE-DESSIS兲 module bundled in the Sentaurus TCAD software, which calculates the terminal characteristics and charge distribution in the devices using a density-gradient 共DG兲 solving algorithm. Since the DG model is robust, fast, and can be applied to highly nonequilibrium situations, the quantized electron gas has been accounted for by the DG transport model.27 The DG approach is a self-consistent way to account for the quantum effects via the quantum potential correction to the continuity equation.28 The parameters adopted in the DG approach are calibrated by self-consistent Poisson–Schrödinger solving algorithm. As we know, self-heating effects can significantly influence the current-voltage characteristics at the higher source drain biases by usually more than 20 V.23 Although the Sentaurus device is capable of handling nonisothermal simulations, we assumed a fixed temperature of T = 300 K in all simulations since the range of the considered source drain biases is around 10 V for our simulation and self-heating effects go beyond the scope of this work. Detailed discussions on self-heating effects for GaN-based FETs can be found in Refs. 22 and 23. Since hot electrons play an important role in the vertical real space charge transfer and subsequent capture in bulk and surface traps, carrier temperature is calculated by the hydrodynamic transport equations.29 The

Schottky barrier tunneling is considered for the gate leakage current calculation. The strain-induced and spontaneous polarizations cause interface charges at nitride heterointerfaces. We take into account these charges by specifying the interface charges at the heterointerfaces. The theoretical computations of the interface charges for GaN-based HEMTs are given as follows.30 The strain-induced piezoelectric polarization of AlxGa共1−x兲N can be expressed by Ppz_AlGaN共x兲 = 2␧xx共e31 − c13/c33e33兲,

共1兲

where ␧xx is the strain of the x-y plane, c13 and c33 are the elastic constants, and e33 and e31 are the piezoelectric constants. The spontaneous polarization of Al共1−x兲GaxN can be expressed by Psp_AlGaN共x兲 = xPsp_AlN + 共1 − x兲Psp_GaN .

共2兲

The charge due to the piezopolarization at AlGaN/GaN is given by DPpz = 0 − Ppz_AlGaN共x兲. The charge due to the spontaneous polarization at AlGaN/GaN is given by DPsp = Psp_GaN − Psp_AlGaN共x兲. Since the polarization charge calculated by a linear interpolation 共Vegard’s law兲 between the total polarization charges of GaN and AlN may cause significant discrepancy compared with the experimental results, the model of Miller et al.31 and Bernardini and Fiorentini32 are used for comparisons. The calculated interface charges at the AlGaN/GaN heterointerface are listed in Table I. Obviously, Vegard’s law overestimates the polarization-induced interface charges at the AlGaN/GaN interface, especially at the larger Al molar fraction, compared with the model of Miller et al. and Bernardini and Fiorentini. The overestimation causes a significant discrepancy on predicting the sheet carrier concentrations of the 2DEG in the channel. For the drain lag simulations, it is found that the discrepancy of the interface charge does significantly influence the drain current collapse, as shown in Fig. 3. Given the possible discrepancy of the interface charges on the passivation/AlGaN and GaN/ substrate interfaces 共the model of Miller et al. only gives the polarization-induced interface charge in the AlGaN/GaN channel兲, Bernardini and Fiorentini’s model is used for predicting the interface charges. The inner mechanisms of the discrepancy of the simulated drain lag for the three models are discussed in Sec. III.


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TABLE II. Summary of parameter values at 300 K adopted in all simulations. Material property Electron mobility Bandgap Shockley–Read–Hall lifetime 共␶max兲 Energy relaxation time Relative permittivity Electron affinity Electron saturation velocity Effective conduction band density of states

FIG. 2. 共a兲 Scheme of space charge components in the GaN-based HEMT device, where −␴POL1 dipole charge is due to the polarization-induced charges at passivation/AlGaN, ␴POL2 dipole charge is due to the polarization-induced charges at AlGaN/GaN, −␴POL3 dipole charge is due to the polarization-induced charges at GaN/AlN-buffer, ␴POL4 dipole charge is due to the polarization-induced charges at AlN-buffer/substrate, ␴2DEG is the 2DEG, ␴AH is the hole accumulation next to the AlGaN surface, and ␴IDT is the ionized donor traps. 共b兲 Scheme of the net polarization-induced charge at each interface. 共c兲 Scheme of the piezoelectric and spontaneous polarizations at each interface.

Finally, the interface charge induced by the polarizations at AlGaN/GaN is included in our simulation as DPsp + DPpz. The interface charge is Psp_AlGaN共x兲 + Ppz_AlGaN共x兲 for AlGaN/ passivation and Psp_AlN − Psp_GaN for GaN/buffer. All parameters in Eqs. 共1兲 and 共2兲 can be found in Ref. 30. Figure 2 shows the detailed scheme of interface charge components in the simulated GaN-based HEMT device. Photoionization measurements in GaN-based HEMTs have been carried out by Klein et al.,9 which indicated that two trap levels, located approximately 1.8 and 2.85 eV below the conduction band, respectively, in the high resistivity MOVCD GaN buffer layer, produced the current collapse in GaN-based HEMTs.33 These trap levels are included in the GaN layer in our simulations. The trap density is NGaN = 2.5⫻ 1016 cm−3 with a capture cross section of ␴GaN = 1.0 ⫻ 10−15 cm−2 A. A significant amount of structural defects, such as threading or misfit dislocations, and processing damage, such as plasma damage or thermal damage, exist in the AlGaN barrier due to the immaturity of AlGaN/GaN technology, which is translated into bulk traps.15,34,35 Since most of the trap parameters are still unknown, we assume only one single acceptor type electron bulk trap level and fit the values from the experimental data in the AlGaN barrier. The trap density is NAlGaN = 5.0⫻ 1016 cm−3 with a capture cross section of ␴AlGaN = 1.0⫻ 10−15 cm−2. We positioned the trap level 2.2 eV below the conduction band. Linear interpolations are adopted to compute the parameter values as a function of mole fraction in AlGaN. Table II summarizes the important parameter values19,20,34–36 used in the simulations. The simulations are carried out using all of the theoretical and experimental values and the structural design as described above. First, a device structure is created in the Sentaurus device editor module to model the device geometry and create a mesh of nodes where the solutions to the basic

Units

GaN

AlN

cm2 / V s eV ns ps ¯ eV cm/s

1200 3.47 1 0.1 9.5 3.4 1.2⫻ 107

300 6.2 1 0.1 8.5 1.9 1.5⫻ 107

cm−3

2.65⫻ 1018

4.1⫻ 1018

equations would be computed. Second, the material parameters from Table II are entered into a file that the simulation loads at startup. Lastly, the electrode and physics are entered in a third file that the Sentaurus device module loads. The calculations made from instructions in this file take into account Poisson’s equation coupled to the density gradient model 共calibrated by Schrödinger’s equation兲, continuity equation, Shockley–Read–Hall recombination mechanism, Boltzmann statistics, and electron high-field saturation model. III. RESULTS AND DISCUSSIONS

Figure 3共a兲 shows the simulated and experimental Ids共t兲 transients in response to Vds turn-on pulse at Vgs = 0 V for device A. It is found that the simulation results with Bernadini’s model are in better agreement with the reported experiment data,21 while the simulated turn-on drain lag with Vegard’s law or the model of Miller et al. is smaller than that with Bernadini and Fiorentini’s. The reason is that the two models 共especially Vegard’s law兲, which overestimate the polarization-induced interface charges at the AlGaN/GaN heterointerface, have much higher density of the 2DEG in the conductive channel. Under the same bias condition, the 2DEG with low density can obtain much more energy and be accelerated to a much higher temperature than that of high

FIG. 3. 共Color online兲 Simulated 共Vegard’s Law with dot line, model of Miller et al. with dash line, Bernardini and Fiorentini’s model with solid line兲 and experimental 共circles兲 Ids共t兲 transients in response to 共a兲 Vds turn-on pulse at Vgs = 0 V and Vdd = 6 V; the experimental results are from Ref. 21 for device A. 共b兲 Vds turn-down pulse at Vgs = 0 V and Vdd = 20 V, the experimental results are from Ref. 18 for device B. For comparison, the drain currents have been normalized.


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FIG. 4. 共Color online兲 Simulated average electron temperature using Vegard’s Law 共dot line兲, the Miller et al. model 共dash line兲, and Bernardini and Fiorentini’s model 共solid line兲 in response to Vds turn-on pulse at Vgs = 0 V and Vdd = 6 V.

density as shown in Fig. 4, causing a more pronounced hotelectrons effect. Those heated hot electrons subsequently are trapped by the buffer traps inducing the notable turn-on current collapse. A similar phenomenon can be found in the turn-down drain lag simulation. The drain-lag simulated results show that polarization-induced interface charges have significant effect on the hot-electron buffer trapping. Here, it should be mentioned that the current collapse can be weakened by increasing interface-fixed charges, but the threshold voltage shifts toward negative bias because of the higher current density via the buffer layer. Therefore, there may be a trade-off relationship between reducing the current collapse and obtaining sharp current cutoff. As shown in Fig. 3共a兲, there is a quick fall in Ids during the initial 0.05 s, where Ids decreases exponentially 关Ids共t兲 ⬃ exp共−t / ␶兲兴 with the characteristic time ␶ = 0.03 s. Then Ids decreases gradually and reaches the steady-state value with a collapse of about 8%. The simulated characteristic time is comparable to that of the reported.21 In order to analyze the dynamic pictures of the hot electrons accounting for the current collapse and drain lag, the simulated trapped charge at the drain-side gate edge is calculated. Figure 5共a兲 shows the spatial distributions of trapped charge density under the pulse-on drain bias measured at

FIG. 5. 共a兲 Trapped charge density as a function of Y direction 共cut at the drain-side gate edge, x = 0.4 ␮m. The origin of the X axis is at the middle of the gate and the origin of the Y axis is at the AlGaN/GaN interface.兲 under pulse drain bias measured at time t = 0.1, 0.2, and 0.6 s 关as shown in Fig. 3共a兲兴 for device A. 共b兲 Trapped charge density as a function of y direction 共cut at the drain-side gate edge, x = 0.2 ␮m兲 under pulse drain bias measured at time t = 47, 52, 53, 54, 55, and 80 s 关as shown in Fig. 3共b兲兴 for device B.

J. Appl. Phys. 105, 084502 共2009兲

time t = 0.1, 0.2, and 0.6 s for device A. It is well known that acceptor-type traps can be either negative or neutral like the acceptor. Acceptor traps are neutral when empty and negatively charged 共ionized兲 when filled with electrons. Filled acceptor traps can emit electrons or capture holes called detrapping. Empty acceptor traps can capture electrons or emit holes called trapping. There is a dynamic equilibrium between trapping and detrapping at different time stages in the active region. At t = 0.1 s, Vds = 0.1 V, and Vgs = 0 V, the system is at the steady state. The deep traps in the buffer are under the dynamic equilibrium trapping and detrapping. When Vds is positively biased from t = 0.2 to 0.6 s, the equilibrium conditions determine the detrapping process. The excess channel electrons can spill over in all directions while the drain bias is ramped up and acquire enough energy at the gate edges to reach far deep into the buffer where a number of traps are initially unoccupied. The deep traps in the buffer need some time to capture the electrons. Finally, Ids decreases gradually to the steady state at another equilibrium. Figure 3共b兲 shows the simulated and experimental Ids共t兲 transients in response to Vds turn-off pulse at Vgs = 0 V for device B. It is found that the simulation results with Bernadini’s model are in good agreement with the reported experiment data.18 In order to analyze the dynamic pictures of hot electrons during the pulse-off mode, the simulated trapped charge density at the drain-side gate edge is calculated. Figure 5共b兲 shows the spatial distributions of trapped charge density under the pulse-off drain bias measured at t = 47, 52, 53, 54, 55, and 80 s for device B. Similar to the former discussions, there is a dynamic equilibrium between trapping and detrapping at the different time stages in the active region. When Vds is ramped up to 20 V from 0.1 V while keeping Vgs = 0, the equilibrium conditions determine the detrapping process. A number of traps are occupied by hot electrons and the trapped charge density is maximal at t = 47 s as shown in Fig. 5共b兲. When the gate voltage is switched to the initial level, the trapped charges remain nearly the same as that of Vds = 20 V. At the same time, the system of the trapped electrons finds itself far from equilibrium—detrapping and trapping. With the trap filling mechanism being interrupted, the detrapping process alone dominates the dynamics of the trap population until the equilibrium is reached. Finally, Ids recovers to the steady state value at the equilibrium. Figure 6共a兲 shows the transverse and lateral electric fields versus the X direction at y = 0.003 ␮m for device A. The electric field significantly changes in both transverse and longitudinal directions at the drain-side gate edge. The gateto-drain-voltage-dependent strain2,11,36 is induced by the transition from the metal covered part of the channel to the gate/drain extension region. In the simulation, the electrons are trapped at the gate edge due to the strain and are called trapped charges. Therefore, the 2DEG significantly decreases at the drain-side gate edge. The depletion of the 2DEG induces the fluctuation of the electric fields at the drain-side gate edge. According to the HD model, the electrons in the channel are significantly heated and can exit the AlGaN barrier and spread toward the GaN bulk layer, as shown in Figs. 6共b兲 and 6共c兲, thus the electrons occupy more traps at the


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FIG. 6. 共a兲 Transverse and lateral electric fields vs X direction cut at y = 0.003 ␮m 共The origin of the X axis is at the middle of the gate, while the origin of the Y axis is at the AlGaN/GaN interface.兲共b兲 Electron temperature contour map around the gate to channel region and 共c兲 distribution of trapped electrons around the gate to channel region at Vgs = 0 V and t = 0.203 s for device A. Dimensions are in ␮m.

drain-side gate edge at the high drain biases. This increases the energy of the conduction band under the gate edge located toward the drain and creates a potential barrier to electron flow leading to the current collapse. Figure 7 shows the simulated Ids共t兲 transients in response to Vds turn-down pulse at Vdd = 1, 2.5, 5, and 10 V. For Vdd ⱕ 2.5 V, the electrons in the channel cannot be significantly heated and spread vertically, thus hot electrons trapping effect can be neglected. It shows that the drain voltage range 共Vdd ⱖ 5 V兲 is already in the field of well-developed hot electron regime. When the drain voltage is increased to around 10 V, hot electrons can occupy many traps at the drain-side gate edge leading to the current collapse at the high drain biases where the hot electrons trapping effect dominates. Figure 8 shows the simulated Ids共t兲 transients in response to Vds turn-down pulse at Vdd = 10 V with and without hot electron effects. Notice that while a collapse of about 15% at the initial time stage is observed with hot electrons trapping effect 共solid line兲 virtually a negligible collapse is observed without hot electrons trapping effect 共dashed line兲. Although the applied drain voltage is not very high, the drain pulse provides enough energy to heat up electrons during the transient and the hot electrons may play an important role in the current collapse. The simulation results carried out with the simple drift-diffusion 共namely, without the hot electrons

FIG. 7. 共Color online兲 Simulated Ids共t兲 transients in response to Vds turndown pulse at Vdd = 1, 2.5, 5, and 10 V. For comparison, the drain currents have been normalized.

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FIG. 8. 共Color online兲 Simulated Ids共t兲 transients in response to Vds turndown pulse at Vdd = 10 V with hot electron effect 共solid square line兲 and without hot electron effect 共dashed triangle line兲. For comparison, the drain currents have been normalized.

trapping effect兲 transport equations reveal the negligible collapse, emphasizing the instrumental role of the hot electrons in the collapse mechanism. Although the growth at low pressure by introducing more defects or antidoping by carbon may be used to increase the resistivity of GaN, the dopants also increase the defects density in the GaN bulk, which has been shown to further enhance the current collapse effect.35 To minimize the drain current collapse and parasitic conduction, QW HEMT structures are proposed and demonstrated on the basis of the simulations. Since AlN 共or SiC兲 with a band gap of 6.1 eV 共7 eV兲 is highly resistive and high-quality AlN epilayers can be grown and bulk AlN substrates are also available, we substitute the GaN bulk layer with highly resistive AlN bulk layer37–39 to build the AlGaN/GaN/AlN 共AlGaN/GaN/SiC兲 QW HEMTs. The GaN channel layer with a thickness of 50 nm, which is much larger than the critical thickness of GaN/AlN heterostructure, is treated as fully relaxed,40,41 and only spontaneous polarization charges appear at the GaN/AlN interface.37 The channel of the narrower band gap GaN between the buffer layer of the wider band gap AlN and the AlGaN barrier layer increases the quantum confinement of 2DEG and forms a double-heterostructure band structure. However, the large net polarization charges, inducing the two-dimensional hole gas 共2DHG兲 at the GaN/AlN interface, could possibly deplete the 2DEG. A backside-doping scheme is adopted to overcome depletion for device B. Figure 9 shows the simulated electron density as a function of the distance from AlGaN/GaN with and without backside doping 共BD兲 for the proposed QW-HEMT. The simulations indicate that the electron density without backside doping is about 80% lower, which is obviously not acceptable. The simulations demonstrate that a 5 ⫻ 1018 cm−3 BD in the QW-HEMT has the similar sheet electron density as the conventional structure. An excess BD causes an undesired backside electron density in the GaN channel as shown in the inset of Fig. 9. This backside electron density can significantly increase the parasitic conduction in GaN. Considering the parasitic conduction in the bulk and the electron density in the channel, we demonstrate that the doping value around 4 ⫻ 1018 cm−3 is much better than others at this nar-


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FIG. 9. Simulated electron density as a function of distance from AlGaN/ GaN 共cut at x = 0 ␮m兲 with different backside doping densities for the proposed QW-HEMT. Solid triangle line shows the electron density for the conventional HEMT under the same condition. Inset shows the whole electron density throughout the device. The origin of the Y axis is at the AlGaN/ GaN interface.

row range. So, in a wide range of doping density, the device has the good performance and the best doping density may be around 4 ⫻ 1018 cm−3. Generally, a QW HEMT on an AlN substrate forms a double heterostructure with a narrow band gap GaN channel between a wide-band gap AlN buffer layer and an AlGaN barrier layer. Our simulation of the QW-HEMT coherently grown on an AlN buffer layer, similar to that reported in Ref. 38, shows that in addition to the 2DEG formed at the AlGaN/ GaN interface, a 2DHG 共as shown in Fig. 10兲 is induced at the negatively charged GaN/AlN interface, as discussed in Refs. 38 and 39. If the GaN layer is thick enough, the 2DHG avoids the shunting of the 2DEG by background electrons in the structure bulk. In this case, a reduction in the channel thickness can improve the electron confinement and prevent the electron spillover toward the bulk. However, the coexistence of the 2DEG and 2DHG in a thin GaN channel may cause the negative effect on device performance. Indeed, the Ohmic source and drain contact regions formed by annealing may overlap both the 2DEG and 2DHG channels. This is expected to result in shunting of electron conductivity by the parasitic holes. In addition, the electrons heated in the elec-

FIG. 11. 共a兲 Simulated Ids共t兲 transients in response to Vds turn-on pulse at Vgs = 0 V and Vdd = 6 V for conventional HEMT 共circles兲 and QW HEMT 共triangles兲. 共b兲 Simulated Ids共t兲 transients in response to Vds turn-off pulse at Vgs = 0 V and Vdd = 10 V for conventional HEMT 共circles兲 and QW HEMT 共triangles兲. For comparison, the drain currents have been normalized.

tric field induced by the drain-source voltage are capable of penetrating into the 2DHG region, leading to carrier losses through electron-hole recombination. Therefore, the existence of the 2DHG at the GaN/AlN interface makes the application of backside-doping concept necessary. Figure 10 shows that a BD of 4 ⫻ 1018 cm−3 can significantly screen the depletion effect of the 2DHG and increase the concentrations of the 2DEG. To verify the advantage of the proposed QW HEMT, we performed transient simulations for the current collapse effect. The drain pulse as transient signal is such that the minimum drain voltage is 0.1 V and the maximum is 10 V. Compared to the conventional HEMT, the proposed QW HEMT shows a decreased current collapse as shown in Fig. 11. As the AlGaN/GaN/AlN QW structure provides the larger band edge discontinuity and effective confinement than the simple AlGaN/GaN heterostructure, the quantum confinement limits the electrons spillover into the GaN bulk when the 2DEG becomes the hot electrons under the drain bias, decreasing the bulk trapped charges. In Fig. 11共a兲, the hot electrons need to acquire more enough energy at the gate edges to reach far deep into the GaN layer for QW HEMT, therefore, the excess channel electrons for QW HEMT spill over less than that of the conventional-structure HEMT while the drain bias is ramped up, thus causing the reduction in the current collapse. Similarly, under the turn-down drain pulse as shown in Fig. 11共b兲, the amount of the trapped charges for QW HEMT is less than that of the conventional-structure HEMT. When the gate voltage is switched to the initial level, the detrapping process needs the shorter time and is easy to return to the steady state. Our simulation results predict that a reduction in the drain current collapse of 5%–10% for 10 V maximum drain pulse can be achieved. IV. CONCLUSION

FIG. 10. 共Color online兲 Simulated band diagram as a function of distance cut at the middle of the gate with backside doping 共solid lines兲 and without backside doping 共dashed lines兲 for the proposed AlGaN/GaN/AlN QW-HEMT.

In summary, we demonstrated the buffer-trapping effect and explained the observed feature of drain lag and current collapse using two-dimensional transient simulations. The simulation results from Bernardini and Fiorentini’s model are in good agreement with the reported experiment data, indicating that polarization-induced interface charges have


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significant effects on hot-electron buffer trapping. The trapped charge may accumulate at the drain-side gate edge, where the electric field significantly changes and gate-todrain-voltage dependent strain is induced. 2DEG can significantly be heated and spread toward the GaN bulk. Those “hot electrons” are transferred in the vertical real space and subsequently captured by the bulk traps at the drain-side gate edge causing the notable current collapse. Trapping and detrapping processes determine the collapse and recovery of drain current under drain pulse. QW HEMT structures have been proposed and demonstrated to optimize device performance. The simulation results also correlate the current collapse with the double-heterostructure effect of the AlGaN/ GaN/AlN structure. An effective quantum confinement can reduce the current collapse. A possible approach for removing the current collapse that follows from our simulations is field-plate over the drain-side gate electrode, which can lessen the electric field changes at the drain-side gate edge. This work was supported in part by grants from the State Key Program for Basic Research of China 共Grant Nos. 2006CB921507 and 2007CB613206兲, National Natural Science Foundation of China 共Grant Nos. 60576068, 60706012, 10734090, and 10747162兲, Knowledge Innovation Program of the Chinese Academy of Sciences 共Grant No. C2-26兲, and Applied Materials Shanghai Research and Development Fund 共Grant No. 08520740600兲. The authors appreciate Dr. Ying Hou for critical reading of the manuscript. 1

J. Appl. Phys. 105, 084502 共2009兲

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