Two-Stage Isolated Switch-Mode Power Supply With ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 11, NOVEMBER 2010

Two-Stage Isolated Switch-Mode Power Supply With High Efficiency and High Input Power Factor Carlos Alberto Gallo, Fernando Lessa Tofoli, and João Antonio Corrêa Pinto

Abstract—This paper presents the conception and analysis of a switch-mode power supply (SMPS) with desirable characteristics of high-frequency isolation, high input power factor, low harmonic distortion, and high efficiency. Nearly unity input power factor can be obtained by using an interleaved boost converter associated with a nondissipative snubber, as high efficiency of the ac–dc front-end stage results. Additionally, a soft-switching full-bridge topology performs the dc–dc conversion, providing isolation to the SMPS by using a high-frequency transformer. By cascading both stages, the aforementioned characteristics are achieved. Theoretical background on each one of the converters is presented, and experimental results obtained from a laboratory prototype are presented and discussed in order to validate the proposal. In addition, the evaluation tests demonstrate the operation with nearly unity power factor, high efficiency, and good dynamic response over a wide load range. Index Terms—Harmonics, power factor correction (PFC), soft switching, switch-mode power supply (SMPS).

I. I NTRODUCTION

T

HE evolution of electronic equipment has demanded the reduction of size, weight, and volume of switch-mode power supplies (SMPSs). Desirable features are multipleregulated output voltages, isolation, high efficiency, and highfrequency operation [1]. Generally, they employ ac voltages as primary power source, which must be converted to dc voltages [2]. However, the input stages of SMPSs are well known to be harmonic sources. To minimize harmonic distortion levels and achieve unity input power factor, the boost power factor correction (PFC) circuit operating in continuous-conduction mode is by far the popular choice for medium- and highpower (400 W to a few kilowatts) applications. This is because the continuous nature of the boost converter’s input current results in low electromagnetic interference (EMI) compared to other active PFC topologies such as buck–boost and buck converters [3]. Numerous boost-type topologies have been proposed in the last few years with the aim of improving the characteristics of

Manuscript received March 17, 2009; revised June 15, 2009; accepted December 21, 2009. Date of publication February 8, 2010; date of current version October 13, 2010. This work was supported in part by CAPES, by CNPq, and by FAPEMIG (research agencies in Brazil) under Proc. Nb. 574001/2008-5-(INCT-EIE). C. A. Gallo is with the Department of Mechanical Engineering, Federal University of Uberlândia, 38400-902 Uberlândia-MG, Brazil (e-mail: [email protected]). F. L. Tofoli is with the Department of Electrical Engineering, Federal University of São João del-Rei, 36307-352 São João del-Rei-MG, Brazil (e-mail: [email protected]). J. A. Corrêa Pinto is with the Department of Electrical Engineering, Federal Institute of Education, Science and Technology of Pará, 66240-260 Belém-PA, Brazil (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2010.2041735

Fig. 1.

Proposed SMPS.

the traditional converter, such as the reverse-recovery problem of the boost diode [4], [5] and increase of the output voltage [6]. However, as the power rating increases, it is often required to associate converters in series or in parallel. Interleaving techniques consist in the interconnection of multiple switching cells for which the operating frequency is the same, but the internal switching instants are sequentially phased over fractions of the switching period [7]. The converter described in [8] employs this strategy with a popular PFC integrated circuit (IC), as the switching frequency is 100 kHz. An interleaved boost converter can be employed as a preregulator stage, where two switching cells operate at 100 kHz each. Filter inductors and filter capacitors are then supposed to be designed for a switching frequency that is equal to 200 kHz, implying the substantial reduction of the filter elements if compared with the topology proposed in [8]. In addition, interleaving partially cancels the input and output ripples, as the size of the energy-storage inductors and differential-mode EMI filter in interleaved implementations can be reduced [9], [10]. SMPSs are employed in dc voltage step-up or step-down, as several dc–dc converters can be used for this purpose. The phase-shift full-bridge (PSFB) topology is one of the most popular choices when dealing with isolated dc–dc conversion, mainly due to its high efficiency and low EMI [11]. However, the circulating loss in primary is high for a conventional PSFB converter, particularly in high-input-current application. Soft-switching techniques have been proposed for pulse-widthmodulated (PWM) full-bridge converters and can be classified into two types: One is zero-voltage switching (ZVS) [12], and the other is ZV and zero-current switching (ZVZCS) [13]. In ZVZCS PWM full-bridge converters, one leg achieves ZVS, and the other leg achieves ZCS [14]. If the desired characteristics of an SMPS are reduced switching losses, high-frequency isolation, and high efficiency, a dc–dc full-bridge converter using the nondissipative snubber presented in [15] has proven to be adequate. This topology also develops some prominent advantages, since soft switching is achieved for a wide load range and conduction losses are almost the same as those in the hard-switched converter. This paper proposes a high-power-factor SMPS by the association of an ac–dc interleaved boost converter and a dc–dc

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GALLO et al.: TWO-STAGE ISOLATED SMPS WITH HIGH EFFICIENCY AND HIGH INPUT POWER FACTOR

Fig. 2.

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Interleaved boost converter operating with average-current-mode control.

full-bridge topology. Additionally, high efficiency, regulated output voltage, and soft switching of the controlled semiconductors are direct advantages. Initially, the converters are analyzed separately and then associated in a prototype to be evaluated experimentally. The SMPS can be represented by the block diagram shown in Fig. 1. II. AC–DC I NTERLEAVED B OOST C ONVERTER The ac–dc interleaved boost converter is shown in Fig. 2. It operates with the average-current-mode control, which can be implemented with a PFC dedicated IC [16]. An optimum alternative that leads to high power levels at high switching frequencies lies in the nondissipative snubber represented in the dotted line for a single boost converter. The components of the snubber circuit are two diodes Dr11 and Dr12 , one resonant capacitor Cr1 , and one resonant inductor Lr1 . At this point, it is worth to mention that the placement of Cr1 and Lr1 obeys the criteria stated in [17] for the conception of passive lossless snubbers applied to boosttype topologies. An auxiliary power supply can be easily implemented from the converter circuit by coupling boost inductor Lb1 and inductor Lfb1 and also adding one diode Dfb1 , one auxiliary capacitor Caux , and one auxiliary inductor Laux . It must be mentioned that the absence of inductor Laux would lead to the necessity of an external voltage source for the correct operation of the proposed snubber. The derived circuit is responsible for providing energy to the resonance, with the consequent achievement of soft switching for the main switches during both turning on and turning off. Moreover, the aforementioned power supply can also be employed to supply the control circuitry without the need of additional auxiliary voltages. By interleaving the converters, the

converter is always supposed to provide energy to the auxiliary power supply, even when duty cycle is low. Although the number of components seems rather large implying increased cost and volume, complexity is reduced if compared with the solution proposed in [18], where two auxiliary active switches are used, but the number of components is reduced. Other interleaved boost-type converters that employ active switches are presented in [19]–[21]. Even though conduction losses tend to increase if compared with the traditional hard topology, the current flows through at most three semiconductor elements simultaneously (disregarding the diodes of the rectifier bridge) in any of the operating stages. As it will be seen, the application of the snubber cell is justified by the appreciable increase in the efficiency of the converter operating at high frequency. A. Operating Principle In order to study the proposed topology, the following conditions are assumed. 1) All switches and diodes are ideal. 2) Input voltage Vi is constant, and output voltage Vo is rippleless over one switching period. 3) Inductors and capacitors are lossless, and the output current is continuous during the operation. By definition, the following expressions are valid: 1 ωo1 = √ Cr1 Laux

(1)

1 ωo2 = √ Cr1 Lr1

(2)

ωo3 =

1 Cr1 (Lr1 + Laux )

(3)

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Fig. 3. Operating stages. (a) First stage (t0 , t1 ). (b) Second stage (t1 , t2 ). (c) Third stage (t2 , t3 ). (d) Fourth stage (t3 , t4 ). (e) Fifth stage (t4 , t5 ). (f) Sixth stage (t5 , t6 ).

Io α= Vaux

where ωo1

ωo2

Laux Cr1

(4)

ωo3

resonance frequency between capacitor Cr1 , inductor Lr1 , and inductor Laux in the fifth stage (in radians per second); normalized load current (in amperes); output current (in amperes); voltage across auxiliary capacitor Caux (in volts); initial and final values of the voltage across capacitor Cr1 in the fifth stage (see Fig. 4), respectively (in volts).

K=

Vo Vaux

(5)

K1 =

Vdc1 Vaux

(6)

K2 =

1−K 1 + K1

(7)

K3 =

Vdc2 Vaux

(8)

Lr1 =

Laux 2

(9)

The operation of the converter shown in Fig. 2 is divided into the following six stages, according to Fig. 3. A single cell is considered in the analysis due to the inherent analogy between the converter legs. The main waveforms are shown in Fig. 4.

resonance frequency between capacitor Cr1 and inductor Laux in the first stage (in radians per second); resonance frequency between capacitor Cr1 and inductor Lr1 in the fourth stage (in radians per second);

1) First Stage (t0 , t1 ): This stage begins when switch S1 is turned on under null-current condition, because inductor Lr1 is linearly discharged through the loop involving Co /Ro , Db1 , and S1 . The auxiliary power supply maintains the resonance between Laux and Cr1 . This stage finishes when the voltage across capacitor Cr1 equals output voltage Vo , causing diode Dr12 to be forward biased.

α Io Vaux Vdc1 , Vdc2


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Fig. 5. Duty cycle versus normalized load current.

4) Fourth Stage t3 , t4 : There is resonance between inductor Lr1 and capacitor Cr1 , as the current through Lr1 equals load current Io . Capacitor Cr1 is negatively charged, while inductor Lr1 is fully discharged. The time interval that defines this stage is Δt4 = t4 − t3 = Fig. 4.

Main theoretical waveforms.

It can be demonstrated that the current through inductor Laux is given by Cr1 (Vaux + Vdc1 ) sin ω01 t. (10) iLaux (t) = Laux The time interval that defines this stage is Δt1 = t1 − t0 =

arccos K2 . ω01

(11)

Cr1 Vo . Io

5) Fifth Stage t4 , t5 : Resonance between capacitor Cr1 and inductors Laux and Lr1 occurs through the loop formed by Db1 , Co /Ro , Dr11 , and the auxiliary power supply until the current through Lr1 equals load current Io . The current through inductor Laux is iLaux (t) = Cr1 ω03 [(Vaux − V0 ) − Vdc2 ] sin ω03 t.

(16)

vCr1 (t) = − [(Vaux − Vo ) − Vdc2 ] cos ω03 t. The time interval that defines this stage is π Δt5 = t5 − t4 = . ω03

(17)

(18)

6) Sixth Stage t5 , t6 : The voltage across resonant capacitor Cr1 is clamped to the voltage assumed at the end of the previous resonant stage until a new switching cycle begins. Boost inductor Lb1 provides energy to the load. The time interval that defines this stage is Δt6 = Ts − (Δt1 + Δt2 + Δt3 + Δt4 + Δt5 )

(19)

where Ts is the switching period. (13)

3) Third Stage t2 , t3 : This stage begins when switch S1 is turned off with null voltage due to resonant capacitor Cr1 , which is linearly discharged through the loop formed by Lb1 , Co /Ro , and Dr12 . The time interval that corresponds to this stage is Δt3 = t3 − t2 =

(15)

The voltage across capacitor Cr1 is

2) Second Stage (t1 , t2 ): The voltage across capacitor Cr1 is clamped to Vo . Resonant inductor Laux is linearly discharged through the loop formed by Dr11 , Dr12 , Co /Ro , and the auxiliary power supply. This stage is responsible for the PWM characteristics of the converter, and it finishes when switch S1 is turned off. The current through inductor Laux is Cr1 (Vo − Vaux ) · t+ (Vdc1 +Vaux ) 1 − K22 . iLaux (t) = − Laux Laux (12) The time interval that defines this stage is 1 + K1 1 Δt2 = t2 − t1 = 1 − K22 . ω01 K − 1

3π . 2ω02

(14)

B. Static Characteristic of the AC–DC Converter By definition, the static gain of the converter is G=

Vo . Vi

(20)

The gain can be obtained from the voltage across inductor Lb1 , which is equal to the difference between input voltage Vi and output voltage V0 when there is no resonance and/or capacitor Cr1 is discharged.

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Fig. 6. Full-bridge converter.

When switch S1 is tuned on, the following expression is valid: vLb1 (t) = Lb1

diLb1 (t) . dt

(21)

Since inductor Lb1 is charged linearly, it gives vLb1 (t) = Vi

(22)

ΔiLb1 = Io

(23)

Δt = Δt2 = (t2 − t1 ) = DTs

(24)

where Δt is the interval that corresponds to the second stage and D is the duty cycle. Substituting (22)–(24) into (21) gives Vi Io = . Lb1 DTs

(25)

When switch S1 is tuned off, inductor Lb1 is discharged. The interval during which the voltage across Lb1 is V0 − Vi is defined as Δt Δt = (1 − D)Ts − [Δt3 + Δt4 + Δt5 ].

(26)

The voltage across Lb1 during Δt is (Vo − Vi ) = Lb1

Io . Δt

(28)

Substituting (28) into (27) gives DTs Vi . Δt

(29)

Dividing both sides of (29) by Vi and rearranging it in terms of (20), one can obtain the static gain as G=1+

expressed as G=1+

(1 − D) −

fs ω01

D K α

+π

3 √

2 2

+

(31)

3 2

where fs is the switching frequency. From (31), one can show the curves in Fig. 5, where the dutycycle behavior is a function of the normalized current, for several values of the static gain. If α < 1, the output characteristic of the converter is similar to that of a quasi-resonant converter [22]. Otherwise, if α ≥ 1, the output characteristic is the same as that of a PWM boost topology. III. DC–DC F ULL -B RIDGE C ONVERTER

Vi DTs = . I0

(V0 − Vi ) =

Gating signals applied to the full-bridge converter.

(27)

From (25), one can obtain Lb1

Fig. 7.

DTs . Δt

(30)

Substituting (14), (15), and (18) into (26), and the resulting expression for Δt into (30), the static gain can be finally

Fig. 6 shows the full-bridge converter associated with a nondissipative snubber, representing the dc–dc stage of the SMPS. It operates using phase-shift control, as gating signals are generated using a dedicated PWM IC, according to the schematic shown in Fig. 7. This topology employs a coupled output inductor to minimize the currents through the primary winding and the main switches, resulting in reduced conduction losses and high switching frequency [22]. The snubber cell introduced here is an adaptation of the structure presented in [15]. A. Operating Principle In order to study the proposed topology, the operation of the converter shown in Fig. 6 is divided into eight stages, according


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Fig. 8. Operating stages. (a) First stage (t0 , t1 ). (b) Second stage (t1 , t2 ). (c) Third stage (t2 , t3 ). (d) Fourth stage (t3 , t4 ). (e) Fifth stage (t4 , t5 ). (f) Sixth stage (t5 , t6 ). (g) Seventh stage (t6 , t7 ). (h) Eighth stage (t7 , t8 ).

to Fig. 8. A single part is considered in the analysis due to the inherent symmetry of the circuit. The main waveforms are shown in Fig. 9. The analysis is based on the following assumptions. 1) All switches and diodes are ideal. 2) Input voltage Vi is equal to the output voltage of the interleaved boost converter, represented by Vo . 3) The voltage across capacitor Cb is considered constant and ripple free. 4) Input current Ii is constant and flows through capacitor Cb . By definition, the following expressions result: Cr =

Cr2 Cr1 + C Cr1 r2

(32)

X =

Cr1 Cr2

(33)

Fig. 9. Main theoretical waveforms.

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Cr1 = Cr (X + 1)

Cr (X

+ 1) X 1 ω0 = Lr Cr

Cr2 =

= ω0p

1 Lp Cr4

1 Lr Cr1 Lr Io α = Vi Cr

ω01 =

n1 = n2 = n

Vi

(38)

(39) (40)

(42) (43)

K2 = K1

Lr (X + 1) Lp X

(44)

K3 =

Imag Ii

(45)

KLf =

Lf 1 Lf 2

(46)

1 Ts

(47)

fs = Kf

f = s fo

2) Second Stage t1 , t2 : This stage begins when switch S4 is is charged to the input voltage turned off. Capacitor Cr4 is reverse biased. until diode Dr2 The voltage across inductor Lf 1 is

1 Ii sin ωop t + Vi cos ωop t − Vo . vLf1 (t) = − n Cr4 ωop (52) The time interval that corresponds to this stage is Lp X + 1 K2 1 −1 Δt2 = t2 − t1 = tan . (53) ωo Lr X α 3) Third Stage t2 , t3 : The current is freewheeling through the primary winding, as switch S2 can be turned on in zero-voltage condition, since the current flows through D2 . The voltage across coupled inductor Lf 2 causes the current through the primary winding to decrease quickly until it becomes null, as the current through Lf 2 becomes maximum. This stage is responsible for phase-shift con is turned on in zerotrol, and it finishes when Saux1 current condition due to inductor Lr . The voltages across and Cr2 are equal to null and Vi , respectively. Cr1 The voltages across inductors Lf 1 and Lf 2 are = VLf1

Lf 1 V Lf 2 − Lf 1 o

(54)

= VLf2

Lf 2 V . Lf 1 − Lf 2 o

(55)

(48)

resonance frequencies (in radians per second); normalized load current (in amperes); primary inductance (in henries); switching frequency (in hertz); input voltage (in volts); input current (in amperes); switching period (in seconds); magnetizing current (in amperes); turns ratio.

1) First Stage t0 , t1 : Switches S1 and S4 are turned on at the beginning of the stage. The voltage across the primary ). There winding is equal to that across capacitor Cb (VCb is power transfer from the primary to the secondary side. The stage finishes when switch S4 is turned off. The voltage across inductor Lf 1 is (t) = vLf1

Vi − Vo . n

(50)

The time interval that corresponds to this stage is nL α Cr f 1 . (51) Δt1 = t1 − t0 = Lr 1 − n Vo

(37)

Cr2 = Cr4

vs1 (t) = vs2 (t) = vLf1 (t) + Vo .

(36)

(41)

Io Ii

Consequently, the voltages across the secondary windings of the transformer can be obtained as

(35)

Cr1 = Cr3

K1 =

where ωo , ωo1 , ωop α Lp fs Vi Ii Ts Imag n = n1 = n2

(34)

(49)

The time interval that corresponds to this stage is Δt3 =

Ts − (Δt1 + Δt2 + Δt4 + Δt5 + Δt6 + Δt7 + Δt8 ) . 2 (56)

are turned in 4) Fourth Stage t3 , t4 : Switches S2 and Saux1 zero-current condition. The current through Lr increases linearly until it reaches Ii . This stage finishes when switch S1 is turned off in zero-voltage condition. The current through resonant inductor Lr is

iLr (t) =

Vi t. Lr

(57)

The time interval that corresponds to this stage is Δt4 = t4 − t3 =

α . K1 ωo

(58)


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5) Fifth Stage t4 , t5 : This stage begins when switch S1 is turned off in zero-voltage condition because the current through Lr equals Ii . At the same time, there is resonance between Lr , Cr1 , and Cr2 . The voltages across capacitors Cr1 and Cr2 are −VCr1 and null, respectively. Switch S3 is then turned on in zero-voltage condition. and Cr2 are The voltages across resonant capacitors Cr1 Lr I vCr1 (t) = − o [1 − cos (ωo t)] (59) α (X + 1) Cr Lr Io X [1 − cos (ωo t)] + Vi . (60) vCr2 (t) = α (X + 1) Cr The time interval that corresponds to this stage is 2X + 1 1 Δt5 = t5 − t4 = cos−1 . (61) ωo X remains discharged. 6) Sixth Stage t5 , t6 : Capacitor Cr2 . Then, auxiliary There is a resonance between Lr and Cr1 switch Saux1 can be turned off in zero-current condition. The stage finishes when the current through Lr becomes null. The current through resonant inductor Lr is Vi Cr (X + 1) sin (ωo1 t) . (62) iLr (t) = Ii − X Lr is The voltage across resonant capacitor Cr1 (t) = − vCr1

Vi cos (ωo1 t) . X

(63)

The time interval that corresponds to this stage is √ α X X + 1 −1 √ Δt6 = t6 − t5 = . (64) sin ωo K1 X + 1 7) Seventh Stage t6 , t7 : The current through Lr becomes is fully discharged linearly. null. Capacitor Cr1 is The voltage across resonant capacitor Cr1 V I t − i . (t) = i vCr1 Cr (X + 1) X

(65)

The time interval that corresponds to this stage is Δt7 = t7 − t6 =

K1 (X + 1) . α ωo X

(66)

8) Eight Stage t7 , t8 : The voltage across Cr1 becomes null, as switches S1 and S3 are turned on and off simultaneously, respectively, and a new switching cycle begins. During this stage, there is power transfer to the load. The time interval that corresponds to this stage is

Δt8 = t8 − t7 = D Ts √ α X X +1 K1 (X + 1) −1 √ + − sin ωo α X ωo K1 X + 1 where D is the duty cycle of switch S1 .

Fig. 10. Static gain curves of the full-bridge converter varying Kf .

B. Static Characteristic of the DC–DC Converter Expression (68) represents the static gain of the full-bridge converter, which can be shown as that in Fig. 10. Considering n = 1, D = 0.42, and X = 2, one can obtain the curves that show the static gain as a function of the normalized load current α for several values of Kf , which corresponds to the ratio between the switching and resonance frequencies G =

− 1) Vo 2 (KLf = Vi n (KLf − 2D ) 1 α K1 (X + 1) + Kf . × D − 2π K1 2α X 2

(68)

One can see that the static gain assumes the characteristic of a conventional full-bridge converter when α > 1. It means that, for a given value of Kf , energy transfer is decreased when parameter α increases, because the gain is reduced as well. When α > 1, the characteristic of a quasi-resonant converter is observed. Fig. 11 shows the static-gain curves as a function of the normalized load current α for several values of duty cycle D , considering Kf = 0.083. For a given duty-cycle curve, one can see that the static gain decreases when parameter α increases, i.e., energy transfer is reduced when the load increases. It is also possible to notice that the static gain increases proportionally to the duty cycle for a given value of α . IV. D ESIGN P ROCEDURE

(67)

A. AC–DC Interleaved Boost Converter This section presents a design procedure for the interleaved boost converter, whose specifications are given in Table I.

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TABLE II F ULL -B RIDGE C ONVERTER S PECIFICATIONS

Analogously, (4) can be rearranged as Laux = Cr1

αVaux Io

2 .

(73)

Auxiliary voltage Vaux and output current Io can be obtained from the following, respectively: √ √ Vaux = 2Vi D = 2 · 220 · 0.65 = 202.15 V Io =

Po 2000 = 5 A. = Vo 400

(74) (75)

Solving the equation system represented by (71) and (73) gives Laux and Cr1 as Laux = 5.14 μH

Fig. 11. Static-gain curves of the full-bridge converter varying D .

Cr1 = Cr2 = 3.14 nF ∼ = 3.3 nF.

TABLE I I NTERLEAVED B OOST C ONVERTER S PECIFICATIONS

(76)

It must also be mentioned that inductor Lr1 can be determined from (9) Lr1 = Lr2 =

5.6 · 10−6 = 2.8 μH. 2

(77)

B. DC–DC Full-Bridge Converter The choice of parameter α in (73) must observe the PWM characteristics of the converter and also the reduction of the peak current through the main switches. From Fig. 5, if α = 1 and G = 4.0 are chosen, the duty cycle can be determined as D = 0.65. The effective pulse frequency of the input inductor current is twice the switching frequency. Therefore, the inductance value can be obtained as Lb1 = Lb2 =

Vi (2D) 220 · 2 · 0.65 ∼ = = 1 mH. fs 2ΔiL 100 · 103 · 2 · 1.5

(69)

Resonance frequency fo must be greater than switching frequency fs f0 =

100 · 103 fs = = 1.25 MHz. 0.08 0.08

(70)

The design of the resonant elements is related to (70). Then, (1) can be written as 1 ωo1 = √ = 2πfo . Cr1 Laux

(71)

Substituting (70) into (71) gives Cr1 Laux = 1.62 · 10−14 .

(72)

This section presents a design procedure for the full-bridge converter, whose specifications are given in Table II. Analogously to the interleaved boost converter, the choice of parameter α must observe the PWM characteristics of the converter. From Fig. 11, if the duty cycle is D = 0.42, one can choose α = 3.5 and G = 0.7. Resonance frequency fo must be greater than switching frequency fs f0 =

100 · 103 fs = = 1.2 MHz. 0.083 0.083

(78)

The design of the resonant elements is related to (78). Then, (36) can be written as ω0 =

1 = 2πfo . Lr Cr

(79)

Substituting (78) into (79) gives Lr Cr = 1.76 · 10−14 . Analogously, (39) can be rearranged as 2 α Vi Lr = . Cr Io

(80)

(81)


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TABLE III PARAMETER S ET U SED IN THE E XPERIMENTAL T ESTS

Output current Io can be obtained from Io =

Po 1500 = 25 A. = Vo 60

(82)

Substituting (82) and the previous specifications into (81) gives Lr = 3136. Cr

(83)

Solving the equation system represented by (80) and (81) gives Lr and Cr as Lr = 7.43 μH Cr = 2.37 nF. Cr

(84)

Cr2

= 2.37 nF and = 7.5 nF are substituted into (32), If = 3.44 nF, although Cr1 = 3.3 nF can one can determine Cr1 be chosen. V. E XPERIMENTAL R ESULTS An experimental prototype of the SMPS was implemented using the parameter set shown in Table III. Results for the SMPS operating at 1.5 kW are discussed as follows. The PFC for light- and rated-load conditions is shown in Fig. 12(a) and (b), respectively. It also demonstrates that the use of average-current-mode control is efficient, causing the minimization of the total harmonic distortion of the input current. Fig. 13 shows the soft commutation of switch S1 , which is turned on and off under zero-current and zero-voltage conditions, respectively, in both light- and rated-load conditions. Additionally, there are not high current and voltage peaks when the switch is turned on or off, respectively.

Fig. 12. Input voltage and current. (a) Light load (450 W). Scales: Vi = 100 V/div., Ii = 3 A/div., time = −5 ms/div., power factor = 0.983, T HDV = 3.55%, and T HDI = 6.89%. (b) Rated load (1.5 kW). Scales: Vi = 100 V/div., Ii = 5 A/div., time = − 5 ms/div., power factor = 0.9985, T HDV = 3.12%, and T HDI = 5.23.

Fig. 14 shows the soft commutation of switch S1 , which is turned on and off with reduced voltage and current, respec is turned tively. Additionally, Fig. 15 shows that switch Saux1 on under zero-current condition due to inductor Lr , and one can see in Fig. 16 that switch S3 is turned on and off under zero-voltage condition. Fig. 17 shows the waveforms regarding the primary winding. Both voltage and current decrease quickly until they become null due to phase-shift control, causing the conduction losses to be reduced as well. Fig. 18 shows some results on the dynamic response of the proposed SMPS when a positive load step from 50% to 100% of the rated load is applied. It can be seen that satisfactory outputvoltage regulation results, with sinusoidal input current. Fig. 19 shows the input power factor as a function of the output power of the SMPS. The curve shows that a high power factor is obtained along the entire load range. One can see that the power factor is 0.998 at rated load, which is in accordance with the waveforms shown in Fig. 12.

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Fig. 15. Drain-to-source voltage and current waveforms of switch Saux1 . Scales: VSaux1 = 100 V/div., ISaux1 = 4 A/div., and time = 2 μs/div.

Fig. 13. Drain-to-source voltage and current waveforms of switch S1 using the proposed snubber. (a) Light load (450 W). Scales: VS1 = 200 V/div., IS1 = 2 A/div., and time = 1 μs/div. (b) Rated load (1.5 kW). Scales: VS1 = 200 V/div., IS1 = 4 A/div., and time = 1 μs/div.

Fig. 14. Drain-to-source voltage and current waveforms of switch S1 . Scales: = 100 V/div., I = 4 A/div., and time = 2 μs/div. VS1 S1

Fig. 20 shows the efficiency curves of both stages of the proposed SMPS. The efficiency of the front-end ac–dc converter is significantly increased by the snubber for almost the entire load range, which is higher than 98% at rated load. It must also be

Fig. 16. Drain-to-source voltage and current waveforms of switch S3 . Scales: = 50 V/div., I = 4 A/div., and time = 2 μs/div. VS3 S3

mentioned that such a characteristic can be further improved if MOSFETs with reduced on-resistance are employed. Furthermore, the soft-switching dc–dc converter rated at 1.5 kW, operating at 100 kHz, presents high efficiency as well, which is over 95% at rated load. Fig. 21 shows the efficiency curve of the two-stage SMPS. It can be seen that the efficiency is significantly high for a wide load range and is above 90% at rated load. Although poor performance is typically expected when dealing with multiplestage SMPSs [23], the use of soft-switching techniques allows high-frequency operation with minimized switching losses and the consequent reduction of size, weight, and volume of magnetics, preserving the useful life of the controlled switches as well. Therefore, high efficiency in both stages is obtained at the cost of increased number of elements and complexity. Even though the proposed arrangement seems rather complex, it must be mentioned that several direct advantages are obtained, which are high power factor, reduced harmonic content of the input current, regulated output voltage, reduction of size of magnetic elements, and also high efficiency. For instance, although most of such characteristics have been achieved with the approaches presented in [24] and [25], the obtained efficiency along the entire load range is not so high.


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Fig. 19. Power factor versus output power.

Fig. 20. SMPS.

Efficiency versus output power for each of the power stages of the

Fig. 17. Voltage and current waveforms of the primary winding. (a) Voltage. (b) Current. Scales: Vp = 100 V/div., Ip = 3 A/div., and time = 2 μs/div.

Fig. 21. Efficiency versus output power of the proposed SMPS.

Fig. 18. Dynamic behavior of the SMPS for a positive load step. Scales: Vo = 25 V/div., Ii = 20 A/div., and time = 5 ms/div.

Therefore, tradeoffs must be made when the aforementioned characteristics become mandatory issues. VI. C ONCLUSION This paper has reported the analytical development of a twostage SMPS. Characteristics such as high-frequency isolation,

high input power factor, low harmonic distortion, and high efficiency have been achieved. The interleaved boost converter is quite efficient as a preregulator stage. Direct advantages are the reduction of size and volume of magnetics and also the absence of auxiliary power supplies. Furthermore, the passive nondissipative snubber lacks auxiliary switches, reducing the complexity of the control circuit and also minimizing switching losses. Although the introduction of the active snubber is supposed to increase the complexity of the control circuit in the fullbridge converter, conduction losses are almost the same due to the phase-shift operation. On the other hand, all the main and auxiliary switches commutate softly, implying increased efficiency. Therefore, optimum performance at high switching frequencies can be obtained.

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R EFERENCES [1] M. Mankikar, “Analysis of various power supply business models,” in Proc. Appl. Power Electron. Conf. Expo., 2001, pp. 54–57. [2] D. Staffiere and M. Mankikar, “Power technology roadmap,” in Proc. Appl. Power Electron. Conf. Expo., 2001, pp. 49–53. [3] R. M. F. Neto, F. L. Tofoli, and L. C. de Freitas, “A high-power-factor half-bridge doubler boost converter without commutation losses,” IEEE Trans. Ind. Electron., vol. 52, no. 5, pp. 1278–1285, Oct. 2005. [4] W. Y. Choi, J. Kwon, E. H. Kim, J. J. Lee, and B. H. Kwon, “Bridgeless boost rectifier with low conduction losses and reduced diode reverserecovery problems,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 769– 780, Apr. 2007. [5] J. M. Kwon, W. Y. Choi, and B. H. Kwon, “Cost-effective boost converter with reverse-recovery reduction and power factor correction,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 471–473, Jan. 2008. [6] I. Barbi and C. M. T. Cruz, “Unit power factor active clamping single phase three level rectifier,” in Proc. Appl. Power Electron. Conf. Expo., 2001, pp. 331–336. [7] Y. Jang and M. M. Jovanovic, “Interleaved boost converter with intrinsic voltage-doubler characteristic for universal-line PFC front end,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1394–1401, Jul. 2007. [8] F. L. Tofoli, E. A. A. Coelho, L. C. de Freitas, V. J. Farias, and J. B. Vieira, Jr., “Proposal of a soft-switching single-phase three-level rectifier,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 107–113, Jan. 2008. [9] P. W. Lee, Y. S. Lee, D. K. W. Cheng, and X. C. Liu, “Steady-state analysis of an interleaved boost converter with coupled inductors,” IEEE Trans. Ind. Electron., vol. 47, no. 4, pp. 787–795, Aug. 2000. [10] W. Li and X. He, “An interleaved winding-coupled boost converter with passive lossless clamp circuits,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1499–1507, Jul. 2007. [11] A. J. Mason, D. J. Tschirhart, and P. K. Jain, “New ZVS phase shift modulated full-bridge converter topologies with adaptive energy storage for SOFC application,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 332–342, Jan. 2008. [12] W. Chen, X. Ruan, and R. Zhang, “A novel zero-voltage-switching PWM full bridge converter,” IEEE Trans. Power Electron., vol. 27, no. 2, pp. 793–801, Mar. 2008. [13] X. Ruan and B. Li, “Zero-voltage and zero-current-switching PWM hybrid full-bridge three-level converter,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 213–220, Feb. 2005. [14] X. Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian, “Soft switched full bridge dc–dc converter with reduced circulating loss and filter requirement,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1949–1955, Sep. 2007. [15] L. H. S. C. Barreto, A. A. Pereira, V. J. Farias, L. C. de Freitas, and J. B. Vieira, Jr., “A non-dissipative snubber applied to the FORWARDPWM-ZVS-SR,” in Proc. Int. Power Electron. Congr., 2000, vol. 1, pp. 237–241. [16] P. C. Todd, “UC3854 controlled power factor correction circuit design,” UNITRODE Application Note U-134. [17] K. M. Smith, Jr. and K. M. Smedley, “Properties and synthesis of lossless, passive soft switching converters,” in Proc. 1st Int. Congr. Israel Energy Power Motion Control, 1997, pp. 112–119. [18] L. R. Barbosa, B. A. Angélico, and C. H. G. Treviso, “A new interleaved boost PWM soft switched converter,” in Proc. IEEE Int. Conf. Ind. Appl., 2000, pp. 108–113. [19] A. T. Cezar, A. A. Pereira, and L. R. Barbosa, “An interleaved boost PWM soft switched converter without stresses,” in Proc. IEEE Int. Conf. Ind. Appl., 2004, pp. 250–255. [20] Y. Jang and M. M. Jovanovic, “Soft switching circuit for interleaved boost converters,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 80–86, Jan. 2007.

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Carlos Alberto Gallo was born in São José do Rio Preto, Brazil, on June 18, 1974. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Federal University of Uberlândia, Uberlândia, Brazil, in 2000, 2002, and 2005, respectively. He is currently a Professor with the Federal University of Uberlândia. His research interests include high-frequency power conversion, microprocessor-based control of power converters, power-factor-correction topologies, and uninterruptible-power-supply systems.

Fernando Lessa Tofoli was born in São Paulo, Brazil, on March 11, 1976. He received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Federal University of Uberlândia, Uberlândia, Brazil, in 1999, 2002, and 2005, respectively. He is currently a Professor with the Federal University of São João del-Rei, São João del-Rei, Brazil. His research interests include power-qualityrelated issues, high-power-factor rectifiers, and soft-switching techniques applied to static power converters.

João Antonio Corrêa Pinto was born in Belém, Brazil, on July 29, 1955. He received both B.Sc. degrees in physics and electrical engineering from the Federal University of Pará, Belém, Brazil, in 1982 and 1992, respectively, and the M.Sc. and Ph.D. degrees in electrical engineering from the Federal University of Uberlândia, Uberlândia, Brazil, in 1997 and 2002, respectively. He is currently a Professor with the Federal Institute of Education, Science and Technology of Pará, Pará, Brazil. His research interests include highfrequency power conversion, modeling and control of converters, power-factorcorrection circuits, uninterruptible-power-supply systems, and new converter topologies.