CDNLive 2014. Tel Aviv. Israel. Talk Outline. ⢠Technion â Fraunhofer IAF Collaboration. ⢠Technology (brief). ⢠High frequency MMIC design challenges.
A Millimeter Wave Broadband, Low Noise and High Gain Integrated Receiver Front-end Based on GaAs Metamorphic HEMTs A step-by-Step high frequency design flow with ADS and Cadence
Aleksey Dyskin
Tel Aviv, 3 November, 2014
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Talk Outline • • • • • • •
Technion – Fraunhofer IAF Collaboration Technology (brief) High frequency MMIC design challenges Front End building blocks ADS/Cadence flow Some measured results Conclusions.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Technion – Fraunhofer IAF collaboration Started in 2009 between Prof. D. Ritter and Prof. I. Kallfass groups.
The first 100nm mHEMT technology (and meanwhile the last) project was started.
First works in InP technology were carried out.(Dr. Kraus PhD thesis on Sigma-Delta)
Technion-2013.
The project was finished with 2 tape-outs and 4 published papers.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Technology|GaAs metamorphic HEMT 100 nm by Fraunhofer IAF
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Technology – metamorphic HEMT Material
Doping
In0.53Ga0.47As
Si
In0.52Al0.48As
n.i.d. Si
Al0.48In0.52As
a = 5.87 (InP)
Al0.48Ga0.52As
a = 5.65 (GaAs)
Remarks cap Schottky barrier -doping
In0.52Al0.48As
n.i.d.
spacer
InxGa1-xAs
n.i.d.
channel
In0.52Al0.48As
n.i.d.
buffer
In0.52Al0.48As Ga0.52Al0.48As
n.i.d. metamorphic buffer
4“ si GaAs substrate
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Technology – 100 nm mHEMT fT / fmax 220 / 300 GHz MMICs up to 200 GHz typical LNA yield > 80% 3 Mask sets per year
SiN GATE
MET1
MESA
250 nm SiN passivation
Technion-2013.
OHM
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Technology - Passives METG GATE SiN MET1
MESA
OHM
MET1
SiN NiCr
SUBSTRATE
Au
• two metalization levels
• 250 nm CVD SiN passivation
• 2.7 µm Au air bridge technology
• full-wafer backside process
• 225 pF/mm2 MIM capacitors
• microstrip technology
• 50 /sq NiCr resistors
• grounded coplanar technology Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
High Frequency MMIC Challenges
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Electromagnetic Simulations Important and indispensable tool for passives/high frequency interconnects
ADS has a Momentum EM simulator, Cadence still does not.
High frequency design should be assisted with accurate EM analysis Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Proper DRC and LVS Each high frequency IC has plenty of passive/active cells to verify both for design rules and schematic matching
No applicable DRC/LVS in ADS. Usually LVS is being performed only visually.
Even one small LVS or DRC mistake can ruin entire tape out. Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
SoC capabilities The aim of each semiconductor company is to put all the blocks into one chip (SoC)
Cadence gives a proper environment for integrating the high frequency IC into one chip.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Front End Building Blocks
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Why do we need wide bandwidth? • • • •
Backhaul communications (70-84 GHz) High resolution radiometry applications Multifunctional communication standards (60, E Bands) Instrumentation needs
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Low Noise Amplifier • • • • •
50-90 GHz bandwidth High gain and low noise figure Broadband I/O matching Linear Compact
Low Noise Amplifier
A.Dyskin, D Ritter, I. Kallfass, “Ultra Wideband Cascaded Low Noise Amplifier Implemented in 100 nm GaAs mHEMT Technology”, Technion-2013. pp.1-4,IEEE International Symposium on Signals,Systems and Electronics, October 2012, , Potsdam, Germany.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Low Noise Amplifier • • •
•
Ls inductive degeneration. L1 resonates out input capacitance. L2 and C1 and Cin keep constant Q matching thus ensuring broader performance for single stage. 4-order matching network, also utilized for biasing, eliminating the need of additional biasing elements.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Asymmetric Passive Switch • • • • •
50-90 GHz bandwidth Low insertion loss Broadband I/O matching One operating voltage Compact
Asymmetric Switch A.Dyskin, N. Peleg, S. Wagner, D Ritter, I. Kallfass, “An asymmetrical 60-90 GHz single-pole double throw switch MMIC”, pp 145-148, European Microwave Integrated Circuits Conference,Technion-2013. October 2013, Nuremberg, Germany.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Asymmetric Passive Switch • • • • •
L4 and L5 match Port3. λ/4 translates open to short and vice versa. L2 and L3 match Port1. L1 matches Port2. LDC produces capacitive loading on M1 gate at high frequencies, providing DC feed on low frequencies. Port1 L3 λ/4
L2 LDC Vctrl
Port3 L5
Vctrl
M2
L4 RG MIM
M1
MIM L1 Port2
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Symmetric Active Switch • • • • •
50-90 GHz bandwidth High gain and low noise figure Broadband I/O matching Linear Compact
Symmetric Active Switch
A.Dyskin, S. Wagner, D Ritter, I. Kallfass, “An active 60-90 GHz single-pole double throw switch MMIC”, Journal of Infrared, Millimeter and Terahertz Waves, Vol.35, IssueTechnion-2013. 4, pp. 412-417, April 2014.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Symmetric Active Switch
• • • •
The branch amplifier was matched stand alone, based on the LNA The input stage was matched to the minimum noise The output stage was matched to the maximum power. In order to compensate the capacitance of the inactive stage, the capacitance compensation network was introduced.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
ADS/Cadence Flow
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Schematic Design Schematic design made in ADS:
Momentum simulations of the EM parts (stubs and vias) Short DC and S-params optimizations Large signal Harmonic Balance
Schematic design is verified in Cadence with SpectreRF:
The whole design is converted to Cadence (EM parts are converted as s-params files) Brief verification of DC and S-params results. Freeze
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout Design Layout Design is made in Virtuoso Layout XL
Each coplanar line/stub should be connected properly. Back - metallization vias should be connected properly. Proper RF and DC ports definitions for future DRC/LVS If there are layout constraints, should be re-simulated in Momentum, simulated as a whole circuit.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout design – what is EM simulated? Port1 L3 λ/4
L2 LDC Vctrl
Port3 L5
Vctrl
M2
L4 RG
M1
MIM
MIM L1 Port2
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
DRC/LVS iteration verifications DRC and LVS should be run on the Layout with Assura
DRC is being run continuously on the layout from the early steps to avoid future complicated fixes. If there are any DRC issues, Momentum should be re-run to verify the performance of the fixed circuit, if needed. LVS black boxes should be well defined (s-param elements)
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
The entire flow Schematic with ADS Momentum on interconnects Momentum on passives
Schematic with SpectreRF Design verification Freeze
Layout with Layout XL DRC at early stages Layout constraints?
Layout check with Assura DRC Problems? LVS check
Tape out Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout Design – Virtuoso Examples
Low Noise Amplifier
Active Switch Asymmetric Switch
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout Design – Virtuoso Examples
Front End
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Some Measured Results| LNA
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout
3.5 X 1 mm2 Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
S-params
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Noise figure
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Some Measured Results| Asymmetric Switch
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout
1.1 X 0.9 mm2
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Insertion Loss
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Ports Matching
•Good matching between measurements and simulations •Good power matching at all the ports of the switch.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Linearity Simulation
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Some Measured Results| Active Switch
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout
2.6 X 1.5 mm2
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
S-Params
Was fixed in second tape-out
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Layout
These back side vias were added to avoid parasitic resonances with ground planes. Could be avoided with careful EM simulations (takes a lot of time for such high frequencies and bandwidth).
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Noise simulation
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Conclusions
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Conclusions and achievements High frequency design still involves 2 simulators for successful design
The first ever reported active switch topology with state-of-theart performance
The proposed flow indeed works
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Acknowledgments • Prof. Ritter research group at the Technion. • Prof. Ingmar Kallfass research group at Fraunhofer IAF, Freiburg, Germany. • Measurements and modeling team at Fraunhofer IAF, Freiburg, Germany.
Technion-2013.
A.Dyskin. CDNLive 2014. Tel Aviv. Israel
Thank you for your time.
Technion-2013.