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Ultrawide-Band Tunable True-Time Delay Lines Using Ferroelectric Varactors Dan Kuylenstierna, Student Member, IEEE, Andrei Vorobiev, Peter Linnér, Senior Member, IEEE, and Spartak Gevorgian, Senior Member, IEEE
Abstract—This paper reports on compact tunable true-time delay lines based on ferroelectric (Ba0 25 Sr0 75 TiO3 ) varactors integrated on high-resistivity silicon. The delay lines are based on lumped elements, physically implemented as synthetic coplanar-strip lines. An approximate analytical design procedure, exactly valid for 0, is proposed. The physical size of the 0.33 mm2 , including bias pads. fabricated delay lines is 2.0 Measurements are performed from room temperature (RT) down to 80 K. The measurements reveal ultrawide-band characteristics for both group delay and insertion loss. At RT, the absolute group delay is (RT 0 V) 70 ps with tunability of 20% under 20-V dc bias, the insertion less than 3.5 dB, and the reflection loss better than 12 dB below 20 GHz. At 145 K, the absolute group 100 ps with a tunability delay is increased to (145 K 0 V) of 50% under 20-V applied bias. At 7 GHz, the insertion loss is 3 dB, resulting in figures-of-merit of 0.03 dB/ps and 50 ps/mm. The leakage current at RT is less than 0.1 A. Index Terms—Delay line, ferroelectric, group delay, tunable, ultrawide-band.
I. INTRODUCTION
ferroelectric varactors offers superior performance in terms factor, negligible leakage current, etc. [11] at of higher frequencies above 10–20 GHz. Ferroelectric varactors can also be integrated with semiconductor (silicon) substrates [11], [12]. Compact true-time tunable delay lines using parallel-plate Ba Sr TiO (BST) varactors as tuning elements was reported in [13]. This paper reports on an improved design demonstrating better figures-of-merit in terms of decibels/picosecond, picoseconds/millimeter, and larger tunability. At room temperature (RT), both group delay and insertion loss are nearly constant over an ultrawide frequency band, extending from 1 to 25 GHz. Low-temperature measurements demonstrate further improved performance. The design is implemented as a synthetic coplanar-strip (CPS) line, integrated on an Si substrate. An approximate analytical design procedure, exactly , is proposed. valid for This paper is organized as follows. Section II presents the approximate design procedure. Section III presents the design and fabrication. Section IV covers measured results and analysis.
D
ELAY LINES are widely used in delay-locked loops (DLLs) [1], voltage-controlled oscillators (VCOs) [2], feed-forward amplifiers [3], and phased-array antennas and radars [4], [5]. For wide-band operation, it is advantageous to use true-time delay steering techniques. The simplest possible true-time delay line is a low-loss transmission line. A tunable delay line may be designed as a slow-wave structure, using tunable elements periodically loading a transmission line. Different physical phenomena in dielectrics (ferroelectrics, liquid crystals), ferromagnetic materials, ferrites, and semiconductors are utilized to accomplish the tunability. Only some of these technologies allow high-density integration and, more specifically, integration with standard semiconductor circuits. The overall performance of tunable monolithic-microwave integrated-circuit (MMIC) delay lines [5], [6] are limited by semiconductor varactors. Recently, ferroelectric varactors have been considered for applications in phase shifters [7]–[9] and delay lines [10]. Compared to semiconductor varactors, Manuscript received October 1, 2004; revised December 16, 2004. This work was supported by the Swedish Agency for Innovation Systems VINNOVA and by the Swedish Foundation for Strategic Research SSF. D. Kuylenstierna, A. Vorobiev, and P. Linnér are with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, 412 96 Göteborg, Sweden (e-mail:
[email protected]). S. Gevorgian is with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, 412 96 Göteborg, Sweden and also with the Microwave and High-Speed Electronics Research Center, Ericsson Microwave Systems AB, 431 84 Mölndal, Sweden. Digital Object Identifier 10.1109/TMTT.2005.848805
II. THEORY The simplest possible true-time delay line is a dispersion-free transmission line with a group delay (1) where is the physical length of the line and velocity defined as
is the group
(2) where is the propagation constant. Considering the dispersion-free region, may be approximated with the phase ve. Equation (1) may then be written locity (3) For reasonable delay times, has to be very large, which makes distributed delay lines inconvenient for on-chip integration. A. Synthetic Delay Lines More compact true-time delay lines may be accomplished as synthetic transmission lines. Fig. 1 shows a T unit cell of
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the characteristic impedance of the biased and unbiased states are related as (11) is the maximum bias voltage. Using (9), the charwhere acteristic impedance of the unbiased state may be expressed in terms of the system impedance as
Fig. 1. Low-pass T unit cell of synthetic transmission line.
a synthetic transmission line. Its component values may be derived from cascade analysis [14] resulting in
(12)
(4)
Inserting (12) into (4) and (5), the component values for a tunable delay line may be written
(5) where is the characteristic impedance, is the center frequency, and is the electric length at . At low frequencies, synthetic transmission lines are nearly dispersion free and the propagation constant may be written (6) where and are inductance and capacitance, respectively, per unit cell and is the physical length of the unit cell. Combining (3) and (6), the delay time per unit cell in a synthetic transmission line may be written (7)
(13) and (14) Inserting (10), (13), and (14) into (7) and (8), respectively, the bias-dependent delay time and characteristic impedance in the may be written low-frequency limit
(15) and
Similarly, the characteristic impedance is written (16) (8) For the dispersion-free approximation to be valid, the electric length of a unit cell must not be larger than a critical value at the maximum frequency of operation . Knowing and , which are determined by the application, and may be calculated from (4) and (5), respectively. B. Tunable Delay Lines Tunable delay lines are normally realized by the use of varactors. A problem is that tuning only the capacitance affects not only the group delay according to (7), but also the characteristic impedance according to (8). To maintain the matching under both bias states, it is necessary to also tune the inductance. However, for reasonable tuning ranges, acceptable matching may be obtained if the characteristic impedance of the line is chosen so that the geometric mean of the characteristic impedance in the two bias states equals the system impedance (9) and are the characteristic impedance with where and without bias, respectively. Defining the tunability of the varactor as (10)
Fig. 2 shows the performance of a 16-unit-cell-long theoretical delay line composed of ideal components. The line is designed using (13) and (14) with (which means that occurs at half the Bragg frequency), rad/s, and a varactor tunability of . It is seen that the group delay is nearly constant up to 30 GHz. The , respectively, is estimated group delay under bias 0 V and to be ps and ps using (15). This is in Fig. 2(c). In the Smith exactly what is obtained for chart, it is seen how the characteristic impedance for the two bias states is symmetrically shifted around the 50- point. III. DESIGN AND FABRICATION A. Layout The ideal lossless delay line, with performance as shown in Fig. 2, is physically implemented as a synthetic CPS line [see Fig. 3(a)]. The symmetric coplanar CPS topology may include inductors in both strips. This results in an effectively doubled inductance per unit length compared, for instance, to a coplanarwaveguide (CPW) line or microstrip (MS) line. Fig. 3(b) shows the substrate in cross section. U-form inducand , effectively capactors are patterned in metal layers itively connected through the BST film. The width and gap of m, chosen for tradeoff the U-form inductors are
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Fig. 2. Theoretical performance of a synthetic transmission line. (a) S (0) [—], S (V [—], (V ) [- - -]. (d) Smith chart S (0) [—], S (V ) [- - -].
between large inductance and low metal losses. The height of m. Varactor loads are formed at overthe unit cell is laps between and [see Fig. 3(c) and (b)]. The physical size of the load varactors is 3 3 m. A small window in and enables overlap of and at the same time as the signal strips 1 and 2 are rather wide. This arrangement results in a tradeoff between losses and process tolerance against misalignment. In [13], two alternate designs were published, one that was superior with regard to losses, and one that was superior with regard to stability against misalignment. Fig. 3(b) shows the equivalent circuit of the unit cell of the synthetic CPS line. The voltage-dependent capacitance of the varactor is given by the formula for a parallel-plate capacitor (17) where is the area of the varactor, is the permittivity of is the thickness of the BST film. The the BST film, and varactor conductance may be written as
) [- - -]. (b) S
(0) [—], S
(V
) [- - -]. (c) Delay time (0)
inductance is affected by mutual coupling between adjacent strips; however, it is basically independent of voltage, temperature, and frequency. In the model, it is assumed to be constant (19) The metal resistance may be approximated as a combination of dc and RF resistance (20) is the thickness where is the conductivity of the metal, is the skin depth. of the metal, and is temperature dependent due to the temperature-dependent conductivity. Microwave conductance of the varactor (18) and metal losses (20) are the two main loss mechanisms in the tunable delay lines. For optimization of the design, it is important to determine which of the two is dominating. B. Process Technology
(18) is the loss tangent of the BST film. The last step where [15]. The unit cell uses the approximation that
The processing starts with commercially available oxidized k cm Si covered by TiO n-type high-resistive (15 nm) and Pt (100 nm). The TiO is used as an adhesion layer. For reduction of metal losses in the bottom electrode, a
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Fig. 3. Fabricated delay line. (a) Entire line including 16-unit cells. (b) Substrate cross section. (c) Magnification around one of the load varactors. (d) Equivalent circuit of the unit cell.
0.5- m-thick Au film is deposited on top of the thin Pt film. On top of Au, 50-nm Pt is required for lattice matched heteroepitaxial growth of the Ba Sr TiO film. Au and Pt are deposited in situ by electron-beam evaporation at RT. Before deposition of the ferroelectric film, is prepatterned by ion etching to form required shapes in the bottom electrode. After prepatterning of the bottom electrode, the ferroelectric film is grown over the wafers entire surface with laser ablation using a KrF excimer laser operating at 10 Hz and 1.5 J/cm . During the film deposition, the substrate temperature is maintained at 650 C and oxygen pressure at 0.4 mbar. After deposition, the samples are cooled down to RT and the pressure is increased to 950 mbar. When the film deposition is finished, , consisting of 50 nm Pt and 0.5 m Au, is deposited by e-beam evaporation at RT. Finally, is patterned by a liftoff process, using AZ1514E photoresist, in order to form the top electrode. IV. RESULTS AND ANALYSIS The delay lines have been measured using an HP-8510 vector network analyzer (VNA). Low-temperature measurements have been performed on an in-house built cryogenic microwave probe station based on a CTI 350 CP cryo cooler. Figs. 4–6 shows measured and modeled -parameters and group delay for RT, 250 K, and 145 K, respectively. Measurements were also performed at 85 K, and these results are similar to those obtained at 145 K. At RT, the measured group delay without bias is rather constant 0V 70 ps up to 25 GHz. At 250 K, 250 K 0 V ps up to 20 GHz. At 145 K, 145 K 0 V 100 ps up to 12 GHz. Under applied bias, 20 V 55 ps, which is almost independent of temperature. At RT and 250 K, the insertion loss is less than 3.5 dB
until 20 GHz. At 145 K, the insertion loss increases fast after 10 GHz. The measured leakage current at RT is 0.1 A. The measured results were matched to the equivalent-circuit model in Fig. 3(d) by circuit optimization in ADS. The results of this optimization are shown in Table I. The group delay is estimated to an accuracy of 5% up to 20 GHz. The insertion loss is estimated to an accuracy of 1 dB at RT and 250 K (the average match is better, but the ripple is not aligned), at 145 K, the error is slightly larger. The model also gives a qualitative estimation of the reflection loss, even though the exact ripple that is sensitive to the impedance level and pad capacitance is not predicted. It should be mentioned that the measured data is not deembedded. For frequencies above 20 GHz, the measured group delay increases, which indicates that the Bragg frequency is approaching. However, the increase is faster than what is predicted by the model. Also, the measured insertion loss, especially at 145 K, increases faster than predicted. A possible explanation is the effect of mutual coupling between adjacent unit cells, which is not covered by the model. Overall, the match between the model and measured data is rather good up to 25 GHz, but the model is not useful above this frequency. In the model parameters (see Table I), some clear temperature-dependent trends are seen. As expected, due to the temperature-dependent permittivity and loss tangent of the BST film [16], the capacitance and loss constant increase with decreased temperature. Contrary, the dc resistance is reduced with decreased temperature due to increased conductivity of the metal. This means that the two dominant loss mechanisms, i.e., resistive losses and varactor losses, go in different directions with reduced temperature. The fact that the insertion loss at RT increases as , as is predicted from (20), indicates that metal losses dominates and the performance may be further improved
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Fig. 4. Measured (0 V [], 20 V [
]
) and modeled (0 V [-], 20 V [- - -]) results at RT. (a) Transmission. (b) Reflection. (c) Group delay.
Fig. 5. Measured (0 V [], 20 V [
]
) and modeled (0 V [-], 20 V [- - -]) results at 250 K. (a) Transmission. (b) Reflection. (c) Group delay.
Fig. 6. Measured (0 V [], 20 V [
]
) and modeled (0 V [-], 20 V [- - -]) results at 145 K. (a) Transmission. (b) Reflection. (c) Group delay.
TABLE I MODEL PARAMETERS FOR DELAY LINES
TABLE II FIGURES-OF-MERIT FOR DELAY LINES
if the metal thickness is increased. The total thickness of and , together forming the U-shape inductors, is only 1 m, which is comparable to at 10 GHz. Using the equivalent circuit in Fig. 3(d), together with the extracted model parameters in Table I, it is easy to estimate the loss reduction that may be achieved with thicker metal. For instance, if the metal thickness
is increased to 3 m, the insertion loss at 20 GHz would be reduced with 1.5 dB.
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Fig. 7. Reflection coefficient in Smith chart. (a) RT and (b) 145 K. S (0 V) [-] and S (20 V) [- - -].
Table II summarizes figures-of-merit at the three different temperatures, as well as a comparison to previously published true-time delay lines. In terms of decibels/picoseconds and picoseconds/millimeter, the delay lines published here are superior to the delay lines in [5] and [13]. On the other hand, it is fair to mention that the distributed phase shifters, implemented as periodically loaded CPWs, in [6] and [9] have high figures-ofmerit in terms of phase shift per decibels; however, information about group delay is lacking in these papers. The main advantage of the delay lines reported in this paper is the compact size. These delay lines are significantly smaller than the distributed phase shifters in [6] and [9]. It should also be mentioned that the delay lines in this paper were designed for operation at RT. For this reason, the reflection loss at lower temperature is not optimized according to (12), which is easily seen from the Smith chart (see Fig. 7). At RT [see Fig. 7(a)], the characteristic impedances of the two bias states are positioned nearly symmetric around the 50- point, as shown in Fig. 2(d). At 145 K [see Fig. 7(b)], the characteristic impedance of the unbiased state is increased due to the higher permittivity of the BST film. Better low-temperature performance of delay lines may be obtained by optimization for low-temperature operation. V. CONCLUSIONS True-time tunable delay lines have been implemented as synthetic CPS lines using ferroelectric varactors as a tunable element. It has been demonstrated that the design results in approximately constant group delay and insertion loss from 1 up to 20 GHz depending on temperature and bias voltage. At RT, metal losses are dominant both with and without applied bias. This means that the performance may be improved with thicker metal. At 145 K, metal losses dominates under applied bias, but without bias, losses in the ferroelectric varactors are larger. An equivalent-circuit model has been proposed and may be used for further optimization of the devices.
ACKNOWLEDGMENT The authors would like to thank H. Jacobsson, Ericsson Microwave Systems AB, Mölndal, Sweden, for useful discussions. The authors also thank the reviewers for their fruitful remarks, which improved the quality of this paper. This study was carried out within the Competence Center Chalmers Center for High-Speed Technology (CHACH), the High-Speed Electronics Program (HSEP), and the project Pacific Boat. REFERENCES [1] Y. J. Jung, S. W. Lee, D. Shim, W. Kim, C. Kim, and S. I. Cho, “A dual loop delay locked loop using multiple voltage controlled delay lines,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 784–791, May 2001. [2] J. E. Rogers and J. R. Long, “A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18 m CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1781–1789, Dec. 2002. [3] D. Wills, “A control system for a feedforward amplifiers,” Microwave J., vol. 41, no. 4, pp. 22–34, Apr. 1998. [4] P. Teo, K. Jose, Y. Gan, and V. Varadan, “Beam scanning of array using ferroelectric phase shifters,” Electron. Lett., vol. 36, no. 19, pp. 1624–1626, Sep. 2000. [5] C. C. Chang, C. Liang, R. Hsia, C. W. Domier, and N. C. Luhmann, “True time phased array system based on nonlinear delay line technology,” in Proc. Asia–Pacific Microwave Conf., Taipei, Taiwan, R.O.C., Nov. 2001, pp. 795–799. [6] A. Nagra and R. York, “Distributed analog phase shifters with low insertion loss,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 9, pp. 1705–1711, Sep. 1999. [7] V. K. Varadan, K. Jose, V. V. Varadan, R. Hughes, and J. F. Kelly, “Novel microwave planar phase shifter,” Microwave J., vol. 38, no. 4, pp. 244–254, Apr. 1995. [8] Y. Liu, A. Nagra, E. Erker, P. Periaswamy, T. Taylor, J. Speck, and R. York, “BaSrTiO interdigitated capacitors for distributed phase shifter applications,” IEEE Microw. Guided Wave Lett., vol. 10, no. 11, pp. 448–450, Nov. 2000. [9] B. Acikel, T. R. Taylor, P. J. Hansen, J. S. Speck, and R. A. York, “A new high performance phase shifter using Ba Sr TiO thin films,” IEEE Microw. Wireless Comp. Lett., vol. 12, no. 7, pp. 237–239, Jul. 2002. [10] A. Kozyrev, V. Osadchy, A. Pavlov, D. Kosmin, L. Sengupta, X. Zhang, and L. Chiu, “S -band microwave phase shifters based on ferroelectric varactors,” in 15th Int. Integrated Ferroelectrics Symp., vol. 55, Mar. 9–12, 2003, pp. 839–846.
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[11] A. Vorobiev, P. Rundqvist, K. Khamchane, and S. Gevorgian, “Silicon substrate integrated high -factor parallel-plate ferroelectric varactors for microwave/millimeterwave applications,” Appl. Phys. Lett., vol. 83, no. 15, pp. 3144–3146, Oct. 2003. [12] D. Kuylenstierna, A. Vorobiev, and G. Subramanyam, “Tunable electromagnetic bandgap structures based on Ba Sr TiO ,” in Proc. 33rd Eur. Microwave Conf., Munich, Germany, Oct. 2003, pp. 1111–1114. [13] D. Kuylenstierna, A. Vorobiev, P. Linnér, and S. Gevorgian, “Ferroelectrically tunable delay lines,” in Proc. 34th Eur. Microwave Conf., Amsterdam, Netherlands, Oct. 11–15, 2004, pp. 157–160. [14] S. J. Parisi, “180 lumped element hybrid,” in IEEE MTT-S Int. Microwave Symp. Dig., Long Beach, CA, Jun. 1989, pp. 1243–1246. [15] A. Vorobiev, P. Rundqvist, K. Khamchane, and S. Gevorgian, “Microwave loss mechanism in Ba Sr TiO thin film varactors,” J. Appl. Phys., vol. 96, no. 8, pp. 4642–4649, Oct. 2004. [16] O. G. Vendik, S. P. Zubko, and M. A. Nikol’ski, “Microwave loss-factor of Ba Sr TiO as a function of temperature, biasing field, barium concentration, and frequency,” J. Appl. Phys., vol. 92, no. 12, pp. 7448–7452, Dec. 2002.
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Dan Kuylenstierna (S’04) was born in Göteborg, Sweden, in 1976. He received the M.Sc. degree in physics and nanoscale science from the Chalmers University of Technology, Göteborg, Sweden, in 2001, and is currently working toward the Ph.D. degree in microwave electronics at the Chalmers University of Technology. His main scientific interests are periodic structures, lumped elements, metamaterials, and use of these to shrink the size of passive MMICs. Mr. Kuylenstierna was the recipient of the Second Prize in the Student Paper Award Competition presented at the 2004 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS), Fort Worth, TX.
Andrei Vorobiev was born in Gorky, Russia, on 1963. He received the M.Sc. degree in physics of semiconductors and dielectrics from Gorky State University, Gorky, Russia, in 1986, and the Ph.D. degree in physics and mathematics from the Institute for Physics of Microstructures of Russian Academy of Sciences (IPM RAS), Nizhny Novgorod, Russia, in 2000. Since 1986, he has been an Engineer and then the Head of the Laboratory of Microelectronics, Design Office of Measuring Instruments, Gorky, Russia, where his research interests were in the area of development of technology of hybrid film microwave integrated circuits. In 1991, he joined the Technology Division, IPM RAS, initially as a Leading Engineer and then as a Senior Research Associate, where his research interests were in the area of preparation and investigation of high-temperature superconductor films and multilayer structures. Since 2001, he has been with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden, initially as a Post-Doctoral Fellow and then as a Guest Researcher. His current interest is in the area of development of fabrication of ferroelectrically tunable devices for microwave applications.
Peter Linnér (S’69–M’74–SM’87) became a Teaching Assistant of mathematics and telecommunications with the Chalmers University of Technology, Göteborg, Sweden, in 1969. In 1973, he joined the research and teaching staff of the Division of Network Theory, Chalmers University of Technology, with research interests in the areas of network theory, microwave engineering, and computer-aided-design methods. In 1974, he joined the Military and Industrial (MI) Division, Ericsson Telephone Company, Mölndal, Sweden, where he was a Systems Engineer and Project Leader involved with several military radar projects. He returned to the Chalmers University of Technology, as a Researcher in the areas of microwave array antenna systems, and since 1981, he has been a Associate Professor of telecommunications. For a portion of 1992, he was a Guest Researcher with the University of Bochum, Bochum, Germany. His current interest is the application of computer-aided network methods and microwave circuit technology with emphasis on filters, matching, modeling, and lumped-element methods.
Spartak Gevorgian (M’96–SM’97) received the M.S. degree in radioelectronics from Yerevan Polytechnic, Yerevan, Armenia, in 1972, and the Ph.D. and Dr. Sci. degrees from the Electrotechnical University, St. Petersburg, Russia, in 1977 and 1991, respectively. From 1972 to 1993, he held different research and teaching positions with the Polytechnic Institute and Electrotechnical University. From 1993 to 1998, he had research positions with the Chalmers University of Technology, Göteborg, Sweden. Since 1998, he has been a Professor with the Chalmers University of Technology. Since 1996, he has also worked part time with Ericsson Microwave Systems AB, Mölndal, Sweden. He has authored or coauthored over 220 papers and conference presentations. He holds over 30 patents/patent applications. He has been or is currently engaged in research projects supported by different national (Russia, Armenia, Sweden) and European Union (EU) projects. His research interests are in physics, design, and experimental investigation of microwave devices and components including tunable filters, delay lines, phase shifters, etc. based on bulk and thin-film ferroelectrics integrated with silicon substrate, silicon RF integrated circuits (RFICs) and MMICs, optimization of passive components in foundry-based MMICs (voltage-controlled oscillators (VCOs), amplifiers, etc.), microwave photonic devices (optically controlled components based on silicon, photonic generation of microwaves), and modeling of passive coplanar and CPS components based on conformal mapping. Dr. Gevorgian was the recipient of scholarships from University College London (1981–1982) and the Electrotechnical University (1988–1991).
