Universal NBTI Compact Model for Circuit Aging ... - IEEE Xplore

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 14, NO. 3, SEPTEMBER 2014

Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions Chenyue Ma, Hans Jürgen Mattausch, Senior Member, IEEE, Kazuya Matsuzawa, Seiichiro Yamaguchi, Teruhiko Hoshida, Masahiro Imade, Risho Koh, Member, IEEE, Takahiko Arakawa, and Mitiko Miura-Mattausch, Fellow, IEEE

Abstract—In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (Vth ) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (Eox ). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted. Index Terms—Negative bias temperature instability (NBTI), modeling, interface-state, hole-trapping, universality.

I. I NTRODUCTION

T

HE negative bias temperature instability (NBTI) effect of p-MOSFETs has been considered as one of the major limitations of the circuit lifetime due to its serious impact on threshold voltage (Vth ), transconductance (gm ), drain current (Ids ) and subthreshold swing (SS) [1]–[8]. Recently, the interfacestate generation and the hole-trapping within the gate oxide are considered as original mechanisms for the NBTI degradation [9], [10]. A two-stage trapping model was proposed by describing these two mechanisms as strongly coupled mechanisms [10], [11]. In such a two-stage model, holes are first captured by neutral oxygen vacancy precursors to form trap-centers. Then hydrogen atoms located at the Si/oxide interface are likely to move to the trap-center and thereby create interfacestates [10]. On the other hand, the interface-state creation and the hole-trapping/detrapping are demonstrated as independent mechanisms by observing their different characteristics during the stress/recovery processes [9], [11]. The Vth degradation (ΔVth ), induced by the hole-trapping mechanism, increases and saturates very fast during the stress process, and recovers fast during recovery process. Meanwhile, ΔVth induced by the

Manuscript received May 1, 2014; accepted May 6, 2014. Date of publication May 18, 2014; date of current version September 2, 2014. C. Ma, H. J. Mattausch, and M. Miura-Mattausch are with the Graduate School of Advanced Sciences of Matter, Hiroshima University, Hiroshima 739-8530, Japan (e-mail: [email protected]; [email protected]; [email protected]). K. Matsuzawa, S. Yamaguchi, T. Hoshida, M. Imade, R. Koh, and T. Arakawa are with Semiconductor Technology Academic Research Center, Yokohama 222-0033, Japan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2014.2322673

interface-state generation features continuous increase and slow recovery characteristics during stress and recovery processes. The NBTI model describing the interface-state generation and the hole-trapping mechanisms in planar MOSFET is developed in our previous works [12], [13]. Although the developed NBTI model is able to reproduce the specific measured data from different publications, the universality is needed to be proofed for different dielectric materials and processes. Therefore, the main purpose of this work is to investigate the detailed model-parameter properties for better understanding of the model physics. Besides of obtaining similar or even better accuracy compared to the publications [5], [14]–[16], the proposed universal NBTI model enables circuit aging simulation because it can be implemented into the compact device model HiSIM. The dynamic NBTI characteristics and the circuit-performance degradation are reproduced under different frequency and duty cycle conditions. The contributions of interface-state generation and hole-trapping mechanisms to the circuit delay time degradation are investigated separately, for understanding the failure mechanism during real circuit operation. As confirmed in this work, the model parameters show universal properties with the gate oxide electrical field (Eox ), in spite of different dielectric materials and fabrication processes. Paper organization is as follows: In Section II, the universality of the model parameters is verified with static NBTI measurement results published by different authors. In Section III, the universal NBTI model is further verified with dynamic NBTI measurement results for various bias and frequency conditions. Additionally, the degradation of circuit performances is simulated by implementing the universal NBTI model into the compact model HiSIM [17]. Finally, the conclusions are given in Section IV. II. U NIVERSAL P ROPERTIES OF M ODEL PARAMETERS The hole-trapping and the interface-state generation are widely accepted as the two major mechanisms responsible for the NBTI degradation [9]. Holes tunneling into the gate oxide are possibly to be captured by the pre-existing traps located at the Si/oxide interface as well as in the gate oxide [6]. Under high gate bias condition, holes with high energy may generate interface-states by breaking chemical bonds [2], [11]. Positive charged interface states cause a shift of the flat-band voltage. The NBTI model has been developed by investigating the mechanisms of the hole-trapping and the interface-state generation [12], [13]. Only important points are summarized in the following for completeness.

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MA et al.: UNIVERSAL NBTI COMPACT MODEL FOR CIRCUIT AGING SIMULATION

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The hole-trapping in the preexisting interface traps is described with the dynamic balance equation [14] as dnT_trap (t) = k [Ntrap0 − nT_trap (t)] dt

(1)

where Ntrap0 is the density of trap sites existing at the interface. nT_trap is the density of trapped holes and k is the hole-trapping rate. By solving (1), the hole-trapping density is derived as t nT_trap (t) = Ntrap0 1 − exp − . (2) τc Here τc = 1/k is defined as the hole-capture time. At the same time, holes tunneling into the gate oxide may be captured by the oxide traps. The density is described as powerlaw function of stress time with time exponent of n = 0.14, as being demonstrated by measurements and theories [4], [5] nT_ox = N0 tn

(3)

where N0 is the oxide trap density close to the Si/SiO2 interface. The hole trapping induced threshold voltage shift S (ΔVth _HT ) is described by combining (2) and (3) q S ΔVth _HT = C (nT_trap + nT_ox ) ox = ΔVth_trap + ΔVth_ox q t = Ntrap0 1 − exp − + N0 tn . (4) Cox τc Here ΔVth_trap and ΔVth_ox are the threshold voltage shift (ΔVth ) induced by the hole trapping in the preexisting interface traps and oxide traps, respectively. Cox is the capacitance of the gate oxide and q is the electron charge. After the stress is removed, ΔVth recovers following an inverse process of the hole-trapping R max ΔVth _HT = ΔVth_trap exp(−t/τe ).

(5)

max Here ΔVth _trap is the maximum ΔVth_trap at the end of the stress process. Under high negative stress, holes with high energy have possibility to create interface-states by breaking chemical bonds [2]. Measurement results have demonstrated that the interfacestate generation rate can be written as an exponential function of the gate oxide electric field (Eox ) [1]

dnS_int = A exp(BEox ). dt

(6)

Here nS_int is the density of generated interface-states. A and B are fitting parameters determined by applied materials and fabrication processes. If the degradation of the flat-band voltage (ΔVfb ) due to the interface-state generation is considered, the gate oxide electric field (Eox ) is calculated as Eox =

Vg − (Vfb0 + ΔVfb ) − φs qnS_int = Eox0 − . Tox Cox Tox

(7)

Fig. 1. Comparison of published NBTI models with measured data [15] with stress bias of Vg_str = −2.3 V and −1.2 V. In references [14], [19] and [5], the time dependences of ΔVth are reported as ΔVth ∼ exp(t), ΔVth ∼ log(t), and ΔVth ∼ tn .

Here Vg is the applied gate bias, φs is the surface potential, Vfb0 is the flat-band voltage, Eox0 is the gate oxide field without degradation, and Tox is the thickness of the gate oxide. Substituting (7) into (6), the density of the generated interfacestates is calculated as t . (8) nS _int (t) = Rstr log 1 + τS Here Rstr is the interface state generation rate coefficient. The ΔVth caused by the interface-state generation during the stress S process (ΔVth _int ) is thus written as qnS _int q t S = · Rstr · log 1 + ΔVth_int (t) = . (9) Cox Cox τS R After the stress is removed, the ΔVth recovery (ΔVth _int ) is modeled as an inverse process of stress t R max max (t) = ΔV − ΔV · R log 1 + . ΔVth rec _int th_int th_int τrec (10) max Here ΔVth _int is the maximum ΔVth at the end of the stress, and Rrec is defined as recovery rate coefficient of the generated interface states. The NBTI compact model is finally written by combining both mechanisms of the hole-trapping and interfacestate generation

ΔVth_NBTI = ΔVth_HT + ΔVth_int .

(11)

Different published NBTI models [5], [14], [19] are compared with the measurement results [15] as shown in Fig. 1(a) and (b). Although the model parameters are carefully modified to meet the best fitting results, evident deviations are inevitable for these previous models. The NBTI model proposed in this work shows a good agreement over a wide range of stress durations with various stress biases. The accuracy of the developed NBTI model has been validated with measured data shown in Fig. 2 [20] and Table II [4], [20], [21]. The maximum fitting error is demonstrated to be less than 6% (not shown here). Although the model parameters are extracted by fitting measured data with different dielectric materials and processes, all of them are found to exhibit universal properties as a function of Eox . As shown in Fig. 3, N0 (hole density injected into the gate oxide) is determined by the gate injection current

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TABLE I M ODEL PARAMETERS OF THE C OMPACT NBTI M ODEL

Fig. 2. Accuracy of model evaluation validated by comparing with measured data [20] under (a) stress and (b) recovery conditions.

Fig. 3. Universality of N0 (hole density injected into gate oxide) as a function of the electrical field (Eox ).

(Ig ), which is a function of Eox (Eq. T7 in Table I). The Eox dependences of Ntrap0 (existing interface trap density), Rstr (interface-state reaction rate) and τc (hole capture time constant) are plotted in Fig. 4, verifying again universal properties. Correspondingly formulated functions with their coefficients are listed from Eq. T8 to Eq. T10 in Table I. The increased Ntrap0 and the decreased τc indicate that higher Vg_str increases the hole-trapping probability at the deep trap levels [20], [22]. Increase of Rstr with Eox denotes that the reaction of silicon bonds at the Si/SiO2 interface occurs more easily under high stress bias. During the recovery process, as shown in Fig. 5, Rrec (interface state recovery rate) decreases as a power-law function of stress duration, indicating that more deep level traps with larger hole-emission time constant are generated during long term stress [22]. On the other hand, when the universalized NBTI model is used for reproducing the specific samples manufactured with different materials and processes, modification of related parameters by a small amount is necessary. Details are described in the following: 1) ΔVth_trap_speci in Eq. T8: ΔVth_trap_speci indicates the difference of preexisting-trap density between the universal value and each specific case. The initial value of ΔVth_trap_speci is 0. For specific cases, ΔVth_trap_speci


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TABLE II P ROCESS AND T EMPERATURE C ONDITIONS OF S AMPLES

Fig. 6. (a) Comparison of the universal NBTI model with measurement results and previous published model [19] for duty cycles of 50% with stress bias Vg_str = 0 V ∼ −1.8 V. (b) ΔVth of the 1st, 10th, and 100th stress/recovery (S/R) cycle.

3) GL1 and GL2 in Eq. T7: N0 (density of holes injected into oxide) is described using the gate current Ig (Eq. T7), which is determined by two model parameters, GL1 and GL2 , according to the HiSIM model [17], [21]. For specific cases, GL1 and GL2 should be modified, thus MN0 and NN0 change correspondingly. Fig. 4. Universality of Ntrap0 (existing interface trap density), τc (hole capture time constant) and Rstr (interface-state reaction rate) as functions of Eox .

Fig. 5. Universality of Rrec (interface-state recovery rate) as a function of the previous stress duration.

should be modified to suit for various preexisting trap densities originating from different materials and processes. 2) Mtc and MRstr in Eqs. T9 and T10: τc and Rstr (Eqs. T9 and T10) can be modified by changing the intercepts (Mtc and MRstr ) in semi-log scale plot (log(ΔVth ) ∼ Eox ) for different temperatures, materials and processes, but the slopes (Ntc and NRstr ) remain constant, which is similar to the experimental and theoretical results in Refs. [2], [20].

III. AC A NALYSIS AND C IRCUIT S IMULATION Fig. 6(a) shows comparisons between the universal NBTI model, published model [19] and measured results with duty cycles of 50% [19]. Besides obtaining similar accuracy as the previous model, the universal model also shows its capabilities in realizing circuit aging simulation in a consistent way when implemented into the compact HiSIM model, which will be discussed in detail later. ΔVth of the 1st, 10th, and 100th stress/recovery (S/R) cycle is depicted in the same max graph (Fig. 6(b)). This comparison shows that both ΔVth min (maximum ΔVth at the end of stress period) and ΔVth (minimum ΔVth at the end of recovery period) increases with increased cycle number, and the Vth degradation cannot be totally recovered. The long term cycle-to-cycle NBTI degradation with cycle time length of TCLK = 1000 s (500 s stress and 500 s recovery) is shown in Fig. 7. Both maximum and minimum edges of ΔVth during numerous S/R switches are simulated with the developed universal NBTI model. The modeling result matches max min and ΔVth extracted well with the measured data of ΔVth from measured data with 65 nm technology [19]. The dynamic NBTI degradation is further investigated. Fig. 8(a) is the simulation result for various frequencies. The max min and ΔVth decreases with inamplitude between ΔVth creased frequency. Fig. 8(b) shows that the frequency depenmax min and ΔVth extracted from measurement [23] dence of ΔVth

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Fig. 7. Comparison of the max and min ΔVth during long term dynamic NBTI degradation with cycle time of TCLK = 1000 s (data is from [19]).

Fig. 10. Flow chart of the NBTI model implementation into the compact model HiSIM. With the degraded Vfb , the degradation of the device characteristics and circuit performance are automatically calculated using HiSIM.

Fig. 8. (a) Simulation result of AC NBTI degradation with various frequenmax and ΔV min for p-MOSFET cies. (b) Frequency dependence of ΔVth th samples with DPN SiON of 1.3 nm EOT at stress bias Vg_str = −2.4 V [23].

Fig. 11. (a) Illustration of resistive-load inverter. (b) Frequency dependence of Δtdelay_Vout after different durations of the total operation time.

Fig. 9. Verification that the developed model can quantitatively reproduce the typical “S-shape” duty cycle dependence (data is from [19]).

can be accurately described using the developed universal NBTI model. The duty cycle dependence of ΔVth is simulated in Fig. 9. The model result with S/R cycle time TCLK = 1000 s is compared with the measured data and shows a good agreement. The cases of TCLK = 500 s is TCLK = 100 s are simulated and observed as standard “S-shape” property. The developed universal NBTI model is implemented into the compact model HiSIM [17] for investigating the dynamic degradation in devices and circuits. The flow chart of the inclusion algorithm is shown in Fig. 10. The threshold voltage degradation at the ith time step (ΔVth,i ) is included in the flatband voltage at the (i + 1)th time step (Vfb,i+1 ) as Vfb,i+1 = Vfb,i + ΔVth,i . At each time step ti , the HiSIM model is utilized for estimation of Vfb,i and electrical field defined as Eox,i = (Vg − Vfb,i − φs,i )/Tox , where Vg is the gate voltage, φs is the surface potential and Tox is the gate oxide thickness. The model parameters listed in Table I (Eqs. T7–T11) can be calculated from Eox,i according to their universal relationships.

With the degraded Vfb , the device characteristics (current, transconductance, capacitance etc.) and circuit performance are automatically calculated using HiSIM in a consistent way. The HiSIM model containing the universal NBTI model is utilized for simulating the performance degradation of circuit performance. The circuit simulation is performed for a resistive-load inverter (Fig. 11(a)) with an applied voltage of Vdd = 2 V and a load resister of R = 5 × 106 Ω. Delay time degradation (Δtdelay ) is simulated for different cycle time duration of the input signal. Frequency dependence of the output delay (Δtdelay_Vout ) after different durations of the total operation time is simulated in Fig. 11(b). It can be seen that Δtdelay_Vout decreases with increased frequency and tends to be constant in high frequency region. Such results have been verified with measurements from various publications [24]–[26]. In Fig. 12(a), contributions of the interface-state generation (Δtdelay_int ) and the hole-trapping (Δtdelay_trap ) to the output delay are separated. Δtdelay_int shows larger influence than Δtdelay_trap to the output delay (Δtdelay_Vout ) at low frequency. But when frequency increases to the order of MHz, Δtdelay_int becomes ineffective and Δtdelay_trap


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Δtdelay_trap dominate Δtdelay_Vout for low and high frequency conditions, respectively. In Fig. 13(a), the frequency dependence of Δtdelay_Vout is simulated with duty cycles (S/R) of 0.2, 0.5, and 0.8. Larger Δtdelay_Vout is observed for a larger duty cycle due to longer stress time and shorter recovery time duration. As shown in Fig. 13(b) and (c), larger duty cycles result in a higher proportion of Δtdelay_int because of its slow recovery characteristic. IV. C ONCLUSION

Fig. 12. (a) Frequency dependence of separated contributions from the interface-state generation and the hole-trapping to the output delay time. (b) Corresponding proportional contribution of Δtdelay_int and Δtdelay_trap to Δtdelay_Vout .

Universal properties of the developed NBTI model are verified with measured data published by different authors. The universal model is demonstrated to reproduce the measured Vth degradation accurately, in spite of different dielectric materials and fabrication processes. The dynamic NBTI effect and circuit aging degradation are predicted by implementing the universal NBTI model into the compact MOSFET model HiSIM for circuit simulation. ACKNOWLEDGMENT C. Ma is supported to perform this work as a Research Fellow of Japan Society for the Promotion of Science (JSPS). R EFERENCES

Fig. 13. (a) Frequency dependence of Δtdelay_Vout with duty cycle (stress/recovery) of 0.8, 0.5 to 0.2. (b) Frequency dependence of separated contributions of Δtdelay_int and Δtdelay_trap to the output delay Δtdelay_Vout with duty cycles of 0.2 and 0.5. (c) Corresponding proportion of Δtdelay_int and Δtdelay_trap to Δtdelay_Vout .

becomes dominant. A clearer view is obtained in Fig. 12(b) by investigating the proportional contribution of Δtdelay_int and Δtdelay_trap to Δtdelay_Vout . It is obvious that Δtdelay_int and

[1] A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, “Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, relaxation,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2143–2154, Sep. 2007. [2] T. Grasser, H. Reisinger, P. J. Wagner, and B. Kaczer, “Time-dependent defect spectroscopy for characterization of border traps in metal-oxidesemiconductor transistors,” Phys. Rev. B, vol. 82, no. 24, pp. 245318-1– 245318-10, Dec. 2010. [3] V. Huard, M. Denais, and C. Parthasarath, “NBTI degradation: From physical mechanisms to modeling,” Microelectron. Reliab., vol. 46, no. 1, pp. 1–23, Jan. 2006. [4] S. Mahapatra and M. A. Alam, “Defect generation in p-MOSFETs under negative-bias stress: An experimental perspective,” IEEE Trans. Device Mater. Rel., vol. 8, no. 1, pp. 35–46, Mar. 2008. [5] H. Küflüoglu and M. A. Alam, “A generalized reaction-diffusion model with explicit H-H2 dynamics for negative-bias temperature-instability (NBTI) degradation,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1101–1107, May 2007. [6] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, no. 1, pp. 1–18, Jul. 2003. [7] T. Aichinger, M. Nelhiebel, and T. Grasser, “On the temperature dependence of NBTI recovery,” Microelectron. Reliab., vol. 48, pp. 1178–1184, 2008. [8] H. Luo et al., “Modeling of PMOS NBTI effect considering temperature variation,” in Proc. ISQED, 2007, pp. 139–144. [9] S. Mahapatra, V. D. Maheta, A. E. Islam, and M. A. Alam, “Isolation of NBTI stress generated interface trap and hole-trapping components in PNO p-MOSFETs,” IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 236–242, Feb. 2009. [10] T. Grasser et al., “A two stage model for negative bias temperature instability,” in Proc. IEEE IRPS, 2009, pp. 33–44. [11] V. Huard, “Two independent components modeling for negative bias temperature instability,” in Proc. IEEE IRPS, 2010, pp. 33–42. [12] C. Ma et al., “Modeling of NBTI stress induced hole-trapping and interface-state-generation mechanisms under a wide range of bias conditions,” IEICE Trans. Electron, vol. E96-C, no. 10, pp. 1339–1347, 2013. [13] C. Ma et al., “Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot carrier effects in the circuit simulation,” in Proc. IEEE IRPS, 2013, pp. 2A.3.1–2A.3.6.

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[14] Y. Nissan-Cohen, J. Shappir, and O. Frohman-Bentchkowsky, “Dynamic model of trapping-detrapping in SiO2 ,” J. Appl. Phys., vol. 58, no. 6, pp. 2252–2261, 1985. [15] Z. Ji, L. Lin, J. F. Zhang, B. Kaczer, and G. Groeseneken, “NBTI lifetime prediction and kinetics at operation bias based on ultrafast pulse measurement,” IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 228–237, Jan. 2010. [16] H. Reisinger et al., “Analysis of NBTI degradation and recoverybehavior based on ultra fast Vt-measurements,” in Proc. IEEE IRPS, 2006, pp. 448–453. [17] [Online]. Available: http://home.hiroshima-u.ac.jp/usdl/HiSIM2/ HiSIM2_pub.html [18] M. Miura-Mattausch, H. J. Mattausch, and T. Ezaki, The Physics and Modeling of MOSFETs. Singapore: World Scientific, 2008. [19] J. B. Velamala et al., “Compact modeling of statistical BTI under trapping/detrapping,” IEEE Trans. Electron Devices, vol. 60, no. 11, pp. 3645–3654, Nov. 2013. [20] T. Grasser et al., “The paradigm shift in understanding the bias temperature instability: From reaction-diffusion to switching oxide traps,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3652–3666, Nov. 2011. [21] T. Grasser et al., “Analytic modeling of the bias temperature instability using capture/emission time maps,” in Proc. IEEE IEDM, 2011, pp. 274.1–27.4.4. [22] T. Grasser et al., “The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability,” in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 16–25. [23] C. Shen et al., “Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectric,” in IEEE IEDM Tech. Dig., 2006, pp. 333–336. [24] J. C. Liao, Y. K. Fang, C. H. Kao, and C. Y. Cheng, “Dynamic negative bias temperature instability (NBTI) of low-temperature polycrystalline silicon (LTPS) thin-film transistors,” IEEE Electron Device Lett., vol. 29, no. 5, pp. 477–479, May 2008. [25] C. Y. Lu, H. C. Lin, Y. F. Chang, and T. Y. Huang, “DC and AC NBTI stresses in PMOSFETs with PE-SIN capping,” in Proc. IEEE IRPS, 2006, pp. 727–728. [26] W. Abadeer and W. Ellis, “Behavior of NBTI under AC dynamic circuit conditions,” in Proc. IEEE IRPS, 2003, pp. 17–22.

Chenyue Ma received the B.E. degree from Xidian University, Xi’an, China, in 2007; the Ph.D. degree in microelectronics from Peking University, Beijing, China, in 2012; and the Ph.D. degree from Hiroshima University, Higashi-Hiroshima, Japan, in 2013. Her research interests include reliability characterization and modeling of semiconductor devices and circuits.

Hans Jürgen Mattausch (M’96–SM’00) received the Ph.D. degree from the University of Stuttgart, Stuttgart, Germany, in 1981. From 1982 to 1996, he was with Siemens AG, Munich, Germany, where he was involved in the development of CMOS technology, memory and telecommunication circuits, power semiconductor devices, chip-card ICs, and compact models. Since 1996, he has been with Hiroshima University, Higashi-Hiroshima, Japan, where he is researching in the fields of VLSI design, nanoelectronics, and compact modeling. He is currently a Professor with the Research Institute for Nanodevice and Bio Systems, the HiSIM Research Center, and the Graduate School for Advanced Sciences of Matter, Hiroshima University. Dr. Mattausch is a member of the Institute of Electronics, Information and Communication Engineers.

Kazuya Matsuzawa was born in Tokyo, Japan, in 1962. He received the B.S. and M.S. degrees in electrical engineering from Keio University, Tokyo, Japan, in 1985 and 1987, respectively, and the Ph.D. degree from Hiroshima University, Hiroshima, Japan, in 2006. In 1987, he joined the Process Research Development of the Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Since 1997, he has been with the Advanced LSI Technology Laboratory, Research and Development Center, Toshiba Corporation, Yokohama, where he is currently working on the development of physical models for the device simulation.

Seiichiro Yamaguchi received the B.E. degree in applied physics from Waseda University, Tokyo, Japan, in 1985. In 1985, he joined Fujitsu Limited and had worked in the field of the modeling and simulation of devices. Since 1999, he has been engaged in the development of advanced CMOS technologies. In 1998, he transferred to Fujitsu Semiconductor Limited, where he is currently the Assistant Vice President of the Technology Development Division. Furthermore, he takes part in some collaborative research with universities as the Visiting Researcher of the Semiconductor Technology Academic Research Center (STARC).

Teruhiko Hoshida was born in Osaka, Japan, in 1974. He received the Master’s degree from Osaka Prefecture University, Sakai, Japan, in 2000. In 2000, he entered ROHM and has engaged in the analog IP development and construction of LSI circuit design environment there until now.

Masahiro Imade received the B.E. and M.E. degrees in molecular engineering from Kyoto University, Kyoto, Japan, in 1998 and 2000, respectively. Since 2000, he has been with Panasonic Corporation, Osaka, Japan. From 2012 to 2013, he was a Visiting Researcher with the Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan. His current research interests include compact modeling, thermal analysis, and reliability simulation for devices in analog circuits.

Risho Koh (M’14) received the B.E. degree in electrical engineering and the M.E. and Ph.D. degrees in electronics from Kobe University, Kobe, Japan, in 1986, 1988, and 1999, respectively. In 1988, he joined NEC Corporation, Kawasaki, Japan. In NEC Corporation, He was engaged in the research and development of bulk and SOI MOS transistors. His present activity in the Renesas Electronics Corporation is the research and development on the compact model extraction for MOSFETs. Since 2012, he has also been with the Semiconductor Technology Academic Research Center, Yokohama, Japan, as a Visiting Research Staff. Dr. Koh is a member of the Institute of Electronics, Information and Communication Engineers, the Japan Society of Applied Physics, and the Physical Society of Japan.


Takahiko Arakawa was born in Kagawa, Japan, in 1958. He received the B.S. degree in electronic engineering from Hiroshima University, Hiroshima, Japan, in 1981 and the Dr. Eng. degree from Tokushima Bunri University, Tokushima, Japan, in 2000. He joined the LSI Research and Development Center, Mitsubishi Electric Corporation, Itami, Japan, in 1981 and transferred to the Renesas Electronics Corporation in 2010. Since 2009, he has been with the Semiconductor Technology Academic Research Center, Yokohama, Japan, as a Promoter of joint research with universities. Dr. Arakawa is a member of the Institute of Electronics, Information and Communication Engineers of Japan.

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Mitiko Miura-Mattausch (M’96–SM’00–F’07) received the Dr.Sc. degree from Hiroshima University, Hiroshima, Japan. From 1981 to 1984, she was a Researcher for solid-state physics with the Max Planck Institute, where she was working with nonlinear phenomena in solid-state materials. From 1984 to 1996, she was with the Corporate Research and Development, Siemens AG, Munich, Germany, where she worked on the hot-electron problems in MOSFETs, the development of bipolar transistors, and the analytical modeling of deep submicrometer MOSFETs for circuit simulation. Since 1996, she has been a Professor with the Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter, Hiroshima University, Hiroshima, Japan, where she is currently leading the ultrascale device laboratory. Her experimental and theoretical work focuses on advanced MOSFET features under radio-frequency operation as well as on MOSFETs with a thin active layer. Dr. Miura-Mattausch is a Distinguished Lecturer of the IEEE Electron Device Society.