Universal Platform for Software Defined Radio - CiteSeerX

Universal Platform for Software Defined Radio Ryuji Kohno1 Shinichiro Haruyama3 Francis Swarts3 Lachlan B. Michael3

Masayoshi Abe2 Noboru Sasho2 Robert M-Zaragoza3 Elvino Sousa4 Pieter Van Rooyen3 Yukitoshi Sanada3 Hamid Amir-Alikhani 5 Veselin Brankovic 5 1: Yokohama National University, Japan 2: Semiconductor Company, Core Technology Network Co., Sony Corporation, Japan 3: Advanced Telecommunication Laboratory, Sony Computer Science Laboratories, Inc., Japan 4: Dept. of Electrical and Computer Engineering, The University of Toronto, Canada 5: Telecommunication Research & Development Stuttgart, Sony International (Europe) GmbH, Germany Abstract In this paper, we propose a novel wireless radio platform suitable for software defined radio. This platform is capable of handling multiple radio standards. The pro-

acceptance among companies all over the world. Thus, a multiband multimode radio system is required to create a comfortable mobile computing environment and the reconfigurability of SDR is the answer to this problem. The technical reason behind the poularity of the SDR

posed platform consists of a new broadband radio frequency (RF) front-end supported by a reconfigurable digital signal processor (DSP) or field programmable gate array (FPGA) technology. The advantages of our platform compared to other SDR architectures are presented in this paper.

concept is the development of reconfigurable devices for signal processing such as digital signal processors (DSP) and field programmable gate arrays (FPGA). The latest DSP’s operate at speeds up to 1.1 GHz and offer performance of nearly 9 billion instructions per second. FPGA’s can now provide densities of up to 2 million gates with low

key words: Software Defined Radio, Universal

power consumption. These numbers are ever improving.

Platform, Multimode Multiband Receiver, Direct

[4][5].

Conversion, Five Port MMIC

Therefore, the real challenges facing SDR are the RF front-end, which is able to use the reconfigurability of the

1

Introduction

After the first technical paper was presented in 1992, software defined radio (SDR) has been receiving much attention among researchers working on wireless communications [1] [2]. Behind this popularity, there is a conceptual reason and a technical reason [3]. The conceptual reason is that various wireless standards have been established through generations of wireless communication systems. Even in the same generation, several standards have been created in different regions. As an example, the standardization efforts surrounding IMT2000/UMTS have tried to resolve the dispute over what the third generation standard should entail. Despite all of this, it still seems as if three slightly varying CDMA standards will be introduced in the near future. For wireless LAN, not only IEEE standards, but also de facto standards such as Bluetooth have gained wide

signal processing devices mentioned above and providing multimode and multiband communications. In this paper a novel universal platform is proposed for SDR. The proposed platform consists of a new broadband RF frontend followed by reconfigurable devices such as DSPs and FPGAs. The RF front-end employs the direct conversion approach using an original five port MMIC [6].

2

Direct Conversion MMIC based on Multiport Technology

In order to realize a multimode multiband SDR, the RF front-end should be able to support a wide range of frequencies and bandwidths. This task may be difficult with conventional RF front-end architectures [7]. The block diagram of a conventional heterodyne receiver is shown in Fig.

1. This architecture requires

frequency-dependent passive components such as dielec-

IF Mixer

RF RF Filter Mixer

Directional Coupler

RF Signal

AGC

Divider

Phase Shifter

Divider

LO Signal

A/D A/D 1st

LNA

IF Filter RF Osc.

P1

2nd

IF Filter

P2

P3

IF Osc.

Figure 1: Block Diagram of the Conventional Heterodyne Receiver.

Figure 3: Proposed Topology of the Five Port Direct Conversion Receiver MMIC. off frequency. They are converted to digital signals by IQ analog-to-digital converters (ADCs) and fed to the digi-

RF Mixer LPF AGC

tal stage. The desired signal is selected by the softwareA/D

defined filter with programmable cutoff frequency. The DC technique inherently has no image response,

RF Osc. LNA

and the fixed-frequency image rejection filters can be eliminated. Furthermore, the anti-alias LPF can be designed with active, variable-bandwidth filters such as a switched

/2

capacitor embedded in an LSI chip. However, imperfect components cause residual or latent image responses at A/D LPF AGC RF Mixer

zero Hz. In the DC receiver, such distortion is mainly produced in the mixer. Therefore, a highly linear mixer that reduces second-order distortion is required.

Figure 2: Block Diagram of the Direct Conversion Receiver.

The proposed topology for the five port direct conversion receiver MMIC is shown in Fig. 3. This receiver MMIC is based on the linear operation of the device, and

tric filters in the RF stage and surface acoustic wave

related non-linear effects may be omitted [6]. The power

(SAW) filters in the first IF stage. A ceramic or crys-

level of the local oscillator (LO) is much smaller com-

tal filter is also needed in the second IF stage. The center

pared to the classical approach. Therefore, the DC off-

frequencies and bandwidth of these filters are not flexi-

set problems may be overcome. The other advantage is

ble and not wide enough to support a multiband radio

that the phase shifter in the multi-port may take on any

receiver. Though switched capacitor filter banks and pre-

values, theoretically between 0 and 90 degrees, excluding

cision direct synthesis may be a choice to achieve wider

boundary values. This is an important issue considering

bandwidths and programmability, it is not applicable to

the fact that the conventional I/Q demodulator requires

mobile terminals due to the size and weight.

a 90 degree phase shifter and phase shifters are usually

Thus, the candidate for the RF front-end for SDR is

linear, frequency dependent devices. Thus, the proposed

the direct conversion (DC) principle. The block diagram

DC receiver is able to support a wide band which is more

of a conventional direct conversion receiver is shown in

demanding for conventional I/Q receivers.

Fig. 2. The received signal is down converted directly to baseband by the quadrature mixer. The downconverted

3

Universal Platform

in-phase and quadrature (IQ) signals are prefiltered by the anti-aliasing low-pass filters (LPFs) with variable cut-

The block configuration of the proposed universal platform for SDR which we have developed is shown in Fig.

RF Circuit

A/D

Received Signal Input

I-Q Five Port MMIC Preselect Filter 1

Block

Q

A/D Non-linearity Compensation for Power Detection

Local Filter Gain Control

I

Calculation

A/D

Preselect Filter 2

1 1 P2 P3 + 4κ21 κ22 sin θ R0 Plo 4κ31 κ32 sin θ R0 Plo = hQ0 + hQ1P1 + hQ2 P2 + hQ3 P3

−

Digital Circuit

(3) (4)

where κij is the voltage transfer coefficient of the five port junction, i is the output port of each power detector, j = 1 is the received signal port, j = 2 is the local signal port, θ is the phase shift value of the phase shifter, Pi is the

Local Signal

output voltage of each power detector, Plo is the local osFigure 4: Block Configuration of the Proposed Universal Platform.

cillator signal power, and R0 is a coefficient depending on the power detector load resistance and input resistance of the LO. The coefficients hI i and hQi can be calculated

LO input

directly through a simple calibration procedure. Thus, influences like mismatch of the power sensors and isolation

Calibration Device

amplifier, gain and resistor tolerances, inaccurate assessment of phase shifts and LO level fluctuations may be

Five Port MMIC RF input

LO input

directly considered and calibrated. A single calibration procedure is sufficient if influences due to temperature drifts may be neglected. The remaining difficulty is to take into account the non-linear behavior of the power

A/D

A/D

A/D

sensors. Here, the non-linearity is compensated by means of the digital signal processing.

Digital Signal Processing

The calibration procedure and device are shown in Fig. 5. With 4 known signals, I(1), Q(1), I(2), Q(2), I(3), Q(3), and I(4), Q(4), created by the calibration device, the fol-

Figure 5: Calibration Procedure and Device.

lowing equations are derived. I(1) = hI 0 + hI 1P1 (1)

4. The received signal passes through the pre-select filters, the gain controlled LNA, and is then fed to the proposed five port junction. The output of the power detectors

+hI 2P2 (1) + hI 3P3 (1), Q(1)

the digital signal processing part. In this part, the non-

are calculated from the three output voltages of the power

(6)

I(2) = hI 0 + hI 1P1 (2) +hI 2P2 (2) + hI 3P3 (2),

linearity of the power detectors is compensated and the in-phase (I) and the quadrature (Q) values of the signal

= hQ0 + hQ1 P1 (1) +hQ2 P2 (1) + hQ3 P3 (1),

(PDs), as shown in Fig. 3, is A/D converted and fed to

(5)

Q(2)

= hQ0 + hQ1 P1 (2) +hQ2 P2 (2) + hQ3 P3 (2),

detectors by means of the following equations.

(7)

(8)

I(3) = hI 0 + hI 1P1 (3) I

Q

κ21 κ32 + κ22 κ31 κ21 κ32 + κ22 κ31 P1 − 2 4κ21 κ31 cos θ 4κ11 κ22 κ32 cos θ R0 Plo 1 1 P2 P3 + + (1) 4κ21 κ22 cos θ R0 Plo 4κ31 κ32 cos θ R0 Plo = hI 0 + hI 1 P1 + hI 2 P2 + hI 3P3 , (2) κ21 κ32 − κ22 κ31 P1 κ21 κ32 − κ22 κ31 + 2 = − 4κ21 κ31 sin θ 4κ11 κ22 κ32 sin θ R0 Plo

= −

+hI 2P2 (3) + hI 3P3 (3), Q(3)

(9)

= hQ0 + hQ1 P1 (3) +hQ2 P2 (3) + hQ3 P3 (3),

(10)

I(4) = hI 0 + hI 1P1 (4) +hI 2P2 (4) + hI 3P3 (4), Q(4)

= hQ0 + hQ1 P1 (4)

(11)

+hQ2P2 (4) + hQ3P3 (4).

(12)

From these equations the coefficients hI i and hQi can be determined. The calibration device can consist of 4

[5] C. Dick, F. J. Harris, “Configurable Logic for Digital Communications: Some Signal Processing Perspective,” IEEE Communications Magazine, vol.37, no.8, pp.107-111, August 1999.

switches, 1 attenuator, and 2 phase shifters. [6] M. Abe, N. Sasho, V. Brankovic, and D. Krupezevic,

4

Conclusions

“Direct Conversion Receiver MMIC based on SixPort Technology,” submitted to European Microwave

In this paper, the universal platform for the SDR has

Conference ’00.

been presented. The proposed platform employs the direct conversion approach with the new five port MMIC followed by the reconfigurable reprogrammable devices such as DSPs or FPGAs. The proposed platform is based on the linear operation of the devices. Thus, the DC offset problem may be solved. It is also possible to support very wide bandwidths which is more demanding for conventional I/Q receivers. Therefore, the proposed platform is suitable for multimode and multiband communications.

Acknowledgment We wish to express our deep gratitude to Dr. Tokoro for his encouragement.

References [1] J. Mitola III, D. Chester, S. Haruyama, T. Turletti, and W. Tuttlebee, “Globaliazation of Software Radio,” IEEE Communications Magazine, vol.37, no.2, pp.82-83, February 1999. [2] R. Kohno, “Prespective of Software Radio: Spatial and Temporal Communiation Theory Using Adaptive Array Antenna for Mobile Radio Communications”, Proceeings on Microwave Workshops and Exhibition (MWE’97), Dec. 1997 [3] J. Mitola III, “Technical Challenges in the Globalization of Software Radio,” IEEE Communications Magazine, vol.37, no.2, pp.84-89, February 1999. [4] M. Cummings and S. Haruyama, “FPGA in the Software Radio,” IEEE Communications Magazine, vol.37, no.2, pp.108-112, February 1999.

[7] H. Tsurumi and Y. Suzuki, “Broadband RF Stage Architecture for Software-Defined Radio in Handheld Terminal Applications,” IEEE Communications Magazine, vol.37, no.2, pp.90-95, February 1999.