with a new paradigm in terms of hardware and software development. ...... Universities with a program in Computer Science and Engineering are often faced ..... The ABET (Accreditation Board for Engineering and Technology) organization is.
XUP-UNM EDUCATIONAL PLATFORM – LARGE SCALE PROTOTYPING PLATFORM
BY CRAIG J. KIEF B.S., COMPUTER ENGINEERING UNIVERSITY OF NEW MEXICO, 2002
THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Computer Engineering The University of New Mexico Albuquerque, New Mexico May, 2006
Craig J. Kief Candidate
Electrical and Computer Engineering Department
This thesis is approved, and it is acceptable in quality and form for publication on microfilm: Approved by the Thesis Committee: Dr. Marios S. Pattichis , Chairperson
Dr. L. Howard Pollard Dr. Christos G. Christodoulou Dr. James M. Skinner
Accepted: Dean, Graduate School
Date
Acknowledgements
I heartily acknowledge three individuals that academically drove me to achieve more than I thought I was capable of. Dr. Marios Pattichis who never let me accept that average was good enough and whose sense of humor made even the rough times more enjoyable. Dr. Howard Pollard who made me realize just how quiet and enjoyable donuts and computers could be at six in the morning. And last but not least, Dr. Jim Skinner who gave me the freedom and ability to pursue something that was very important to me. Thanks to Frank Wirtz, Jason Moore, and Anna Acevedo of the Xilinx® Corporation for their technical and material donations and assistance. Thanks to Allison Tafoya, Leslie Vonderheidi, and Joe Leyba for their assistance in helping me with the design and documentation portion of this project. Thanks to Alonzo Vera and Jorge Parra for their skills and technical knowledge in helping with assembly and testing in the final phases. Thanks to Dr. Dave Cook for always being there to help with a smile. Thanks to my mother Carole VanThomas who taught me the importance of education. Finally, I would like to thank my wife Ruth and my daughters Laura and Chelsea whose patience and understanding over the past several years allowed me to be able to pursue this work. Nothing in this world could be as wonderful as the love you have given me.
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XUP-UNM EDUCATIONAL PLATFORM – LARGE SCALE PROTOTYPING PROJECT
BY
CRAIG J. KIEF
ABSTRACT OF THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Computer Engineering The University of New Mexico Albuquerque, New Mexico May, 2006
XUP-UNM EDUCATIONAL PLATFORM – LARGE SCALE PROTOTYPING PROJECT
by
Craig Jonathan Kief
B.S. Computer Engineering, University of New Mexico, 2002 M.S. Computer Engineering, University of New Mexico, 2006
Abstract The use of Field Programmable Gate Arrays (FPGAs) in computer architecture has seen strong growth over the last five years. Reconfigurable logic presents designers with a new paradigm in terms of hardware and software development. To teach these devices, educational institutions need prototyping platforms that will satisfy the needs of undergraduate as well as graduate students, while not being limited by extensive costs. This thesis covers the development of a comprehensive and stand-alone platform that provides a rugged, inexpensive, and robust teaching tool. The board, developed jointly with the Xilinx® University Program (XUP), is termed the XUPUNM prototyping platform.
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The XUP-UNM platform includes two 560-pin Xilinx® Virtex 1000s. Two of these million system gate devices provided the backbone for the eight-layer student platform. The board was designed to allow for programming using the entire suite of Xilinx® design tools including the Integrated Software Environment (ISE), System Generator (Sysgen), and the Embedded Development Kit (EDK). Power to the XUPUNM is provided by a series of cascaded devices. The TPS54616 switching power supply provides precise six amperes 3.3 volt DC power to a 2.5 volt DC voltage regulator. Every device on the board is powered by one of these two supplies. An extensive selection of input and output options are available to the user. The board includes RS-232 Serial and Enhanced Parallel Port (EPP) connectors. The Digilent series of input and output boards mate to the XUP-UNM. For external connectivity, 96pin frame connectors and 140-pin high-speed connectors are also available. For rapid processing, 100 pins are provided to process data between the dual FPGAs. XC18V04 Serial configuration Programmable Read Only Memory (SPROMs) allow for programming the FPGAs using traditional Joint Test Acceptance Group (JTAG) interfacing schemes. Static Random Access Memory (SRAM) provides memory external to the FPGAs for advanced microprocessor type projects.
Fully
functioning
Light
Emitting Diode (LEDs) and push buttons provide simple beginner capabilities for undergraduates. This project was supported by the Xilinx® Corporation’s University Program. All documentation including source code, schematics, bill of materials, and testing programs is available online at www.ece.unm.edu/xup. The completed boards were also tested at West Point Military Academy, the University of Texas (Austin), and the University of
vi
Texas (El Paso). Graduate and undergraduate students from UNM were also involved in all aspects of the project.
vii
CONTENTS Chapter 1 Executive Summary .......................................................................................... 1 1.1 Introduction............................................................................................................... 1 1.2 Methodology ............................................................................................................. 3 1.3 Results....................................................................................................................... 9 1.4 Conclusions and Recommendations for Future Work ............................................ 10 Chapter 2 An Introduction to Programmable Logic ........................................................ 12 2.1 Background ............................................................................................................. 12 2.2 How Programmable Logic Works .......................................................................... 14 2.3 Practical Application of Technology ...................................................................... 18 Chapter 3 Methodology ................................................................................................... 21 3.1 Structured Design Process ...................................................................................... 21 3.2 Requirements Analysis and Available Resources................................................... 22 3.3 Tool Selection ......................................................................................................... 23 3.4 Designing the Board ............................................................................................... 25 3.4.1 General Board Parameters ............................................................................... 26 3.4.2 Virtex 1000 FPGA Devices ............................................................................. 27 3.4.3 Board Material Characteristics ........................................................................ 32 3.4.4 Bypass Capacitance ......................................................................................... 33 3.4.5 Power Section .................................................................................................. 37 3.4.6 JTAG Chain ..................................................................................................... 40 3.4.7 Static Programmable Read Only Memory (SPROM)...................................... 42 3.5 XUP-UNM Reviews and Prototypes ...................................................................... 45 3.5.1 Initial Design Review ...................................................................................... 45 3.5.2 Final Design Review........................................................................................ 46 3.5.3 Initial Prototype Run........................................................................................ 48 3.5.4 Second Prototype Run...................................................................................... 55 Chapter 4 Results ............................................................................................................. 58 4.1 Board Results ......................................................................................................... 58 4.1.1 FPGA Section ................................................................................................. 59 4.1.1.1 Programming the FPGA ........................................................................... 61 4.1.2 Power Section ................................................................................................. 62 viii
4.1.3 Input and Output Section ................................................................................ 63 4.1.4 Memory Section.............................................................................................. 65 4.2 Educational Impact ................................................................................................ 67 4.2.1 Impact to other External Educational Organizations ....................................... 67 4.2.2 Impact Based on my Experiences .................................................................... 68 4.2.3 Impact to the University of New Mexico ........................................................ 69 4.2.4 Impact on Others Involved with the Project .................................................... 70 Chapter 5 Conclusions and Recommendations for Future Work .................................... 72 References......................................................................................................................... 75 Appendices (enclosed CD) ............................................................................................... 78 Appendix A. Specification Document Appendix B. Bill of Materials Appendix C. Schematics Appendix D. 4PCB Quote Appendix E. Final Gerber File Displays Appendix F. Full Production Analysis Appendix G. VHDL Test Code Appendix H. FPGA 1 User Constraint File Appendix I. FPGA 2 User Constraint File
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List of Figures Figure 1. Simple FPGA Dataflow..................................................................................... 16 Figure 2. ISE Design Flow................................................................................................ 17 Figure 3. The Generic Life-Cycle Model [14].................................................................. 22 Figure 4. Sample Gerber Picture....................................................................................... 25 Figure 5. Overview of Board Design................................................................................ 26 Figure 6. Virtex Architecture Overview ........................................................................... 28 Figure 7. Virtex Input/Output Block................................................................................. 29 Figure 8. Two Slice Virtex Complex Logic Block ........................................................... 30 Figure 9. FPGA Connection ............................................................................................. 31 Figure 10. Simple PDS ..................................................................................................... 33 Figure 11. Inductance Versus Via Placement ................................................................... 35 Figure 12. TPS54616 Mounting Design ........................................................................... 38 Figure 13. Swift Software Schematic (courtesy Texas Instruments)................................ 39 Figure 14. Response Graph for TPS54616 (courtesy Texas Instruments)........................ 40 Figure 15. JTAG Representation for Input and Output .................................................... 41 Figure 16. JTAG Chain Configuration Design ................................................................. 42 Figure 17. SPROM Interface Overview (courtesy Xilinx®, Inc.) ..................................... 43 Figure 18. Master-Serial Configuration Mode (courtesy Xilinx®, Inc.) ........................... 44 Figure 19. JTAG Chain Configuration ............................................................................. 45 Figure 20. Top Layer Gerber Picture................................................................................ 47 Figure 21. Layer Seven Gerber Picture............................................................................. 48 Figure 22. BG560 Bottom View....................................................................................... 50 Figure 23. AFX Power Configuration .............................................................................. 52 Figure 24. Daisy Chain of Power Sources ........................................................................ 53 Figure 25. Power Section Layout...................................................................................... 54 Figure 26. Completed XUP-UNM Platform..................................................................... 57 Figure 27. Overall Board Design ...................................................................................... 59 Figure 28. Fully Assembled Board with JTAG Connection............................................. 60 Figure 29. JTAG Chain..................................................................................................... 60 Figure 30. Soldering Power Section ................................................................................. 62 Figure 31. Testing the Power Section ............................................................................... 63 x
Figure 32. Digilent I/O Board Mated During Testing ...................................................... 64 Figure 33. SPROM and Virtex Jumper Design ................................................................ 65 Figure 34. SPROM on Board............................................................................................ 65 Figure 35. V1000 EDK Project......................................................................................... 66 Figure 36. XUP-UNM Platform ....................................................................................... 71 Figure 37. Extend Modeling of Production ...................................................................... 73
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List of Tables
Table 1. Virtex Family Capabilities.................................................................................. 31 Table 2. Bypass Capacitance Selection Criteria ............................................................... 36 Table 3. Capacitor Values Selected .................................................................................. 37
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List of Acronyms ADC
Analog-to-Digital Conversion
AGP
Accelerated Graphics Port
ASIC
Application Specific Integrated Circuit
BGA
Ball Grid Array
BOM
Bill of Materials
CLB
Complex Logic Block
CPLD
Complex Programmable Logic Device
DAC
Digital-to-Analog Conversion
DC
Direct Current
EDK
Embedded Development Kit
EECE
Department of Electrical and Computer Engineering
FPGA
Field Programmable Gate Array
GTL
Gunning Transceiver Logic
IOB
Input and Output Block
IP
Intellectual Property
ISE
Integrated Software Environment
LED
Light Emitting Diode
LUT
Look Up Table
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LVTTL
Low Voltage Transistor Transistor Logic
PCB
Printed Circuit Board
PDA
Personal Digital Assistant
PDS
Power Distribution System
PROM
Programmable Read Only Memory
RAM
Random Access Memory
SPROM
Serial configuration Programmable Read Only Memory
SRAM
Static Random Access Memory
SYSGEN
System Generator
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data Input
TDO
Test Data Output
TMS
Test Mode Select
TRST
Test Reset
UART
Universal Asynchronous Receiver/Transmitter
UNM
University of New Mexico
VHDL
VHSIC Hardware Description Language
VHSIC
Very High Speed Integrated Circuit
xiv
XUP
Xilinx® University Program
xv
Chapter 1 Executive Summary
1.1 Introduction
Universities with a program in Computer Science and Engineering are often faced with the difficult task of providing instruction in a myriad of digital electronic devices under severe constraints associated with cost and schedule. Universities are constantly looking for more efficient methods that will reduce the time and costs associated with teaching these labs without impacting the quality of the education.
In addition,
universities are looking for solutions that can be used to meet the needs of basic undergraduate projects, but that will also be scalable and adaptable to the needs of more advanced undergraduate and graduate students. An important concept in Electrical Engineering undergraduate education today is programmable logic devices. Programmable logic represents the middle ground between hardware and software. Hardware provides a designer the ability to implement functions that will execute extremely fast, but once implemented, the functions cannot be modified. Software provide the designer with the ability to modify functions as necessary, but a function implemented in software will usually execute much slower than if implemented in hardware. Programmable logic provides the unique capability to implement functionality that will execute much faster than software, while still allowing the flexibility to modify the hardware as requirements change. This flexibility allows designers to implement a large portion of the logic while the interfaces are still being finalized. Rather than having to have all of the design 1
completed prior to any construction, programmable logic devices can be modified and changed as they are being developed. Changes to interfaces can be implemented during production, rather than having to start production over. As a result, systems can be delivered to the market more quickly, often providing a business with the competitive edge that can mean the difference between success and failure. When introducing programmable logic into an academic curriculum, it is necessary to encapsulate the amount and scope of material to be covered into a measurable package. Decisions concerning the size and complexity of the projects to be assigned are important, as well as consideration as to the level of detail the student should be exposed to. While some instructors may choose to teach programmable logic as a “black box,” hiding the details of the hardware from the student so as to focus more on the software and functionality of the system, other instructors may decide to teach down to the Complex Logic Block (CLB) level, revealing more of the details of the system. A major problem in the past has been the creation of a development platform for the programmable logic. These platforms need to be rugged, inexpensive, and robust enough to support a wide range of projects being performed by inexperienced students. In addition, they must be complex enough to support the range of projects needed by experienced students. The focus of this thesis is the development of a comprehensive and stand-alone development environment that would provide a rugged, inexpensive, and robust student learning platform. Specifically, the objective was to design, build, and test a circuit card for use in undergraduate and graduate level curriculums. For undergraduates, the board must be rugged enough to withstand the abuses that students exhibit during their early 2
learning stages. For graduate students, the board must be powerful enough to perform a wide range of more advanced Digital Signal Processing (DSP) and microprocessor projects.
1.2 Methodology
The process began with a careful analysis of the requirements of the development environment. Professors were interviewed to gain a complete understanding of their learning objectives and to specify the types of projects the development environment needed to support. Next, the current approach to teaching programmable logic was explored, along with any perceived discrepancies in current approaches. The third step was to design the Development Platform and identify the necessary hardware components for the system. The most expensive components – the Field Programmable Gate Arrays (FPGA) and the Programmable Read Only Memory (PROM) – were donated by Xilinx® Corporation, an industry leader in programmable logic devices. In recognition of the Xilinx’s® contributions and their valuable partnership with UNM, the resulting device has been designated as the XUP-UNM Programmable Logic Development Platform. After evaluating products from several board manufacturers, a programmable logic platform manufacturer by the Diligent Corporation was selected for use. Digilent makes an excellent line of input and output boards along with their line of CPLD and FPGA prototype platforms, but their line of products lack the extensive amount of 3
capabilitites desired by many university programs. It was critical to specify the exact type and number of devices required, since the small quantity ordered for the prototype resulted in much higher prices than normally associated with larger production runs. Software required for the project fell into two categories: software required to design the circuit card and software required to develop the projects. Mentor Graphics Schematic Capture and PCB Expedition were used to design the circuit card. The Xilinx® series of software design tools were used for project development. Assistance in using the software and designing the circuit board was provided by Dr. Pollard of UNM and Mr. Wirtz of Xilinx®. Additionally, three undergraduate students were assigned from the ECE Department to assist in the areas of documentation and prototype board assembly. Once all the resources were arranged, a specification document (see Appendix A) was created to detail how each component is used along with their specific requirements in terms of control, signaling and power. The specification document was created as part of the requirements analysis process and was required to be completed before the first part is placed and routed in software. The specification and design takes into account the desire to support the widest variety of projects in the least amount of space. At the beginning and intermediate undergraduate level, instructors prefer projects that are self contained, using no external interfaces other than power. This desire drives a design that includes a large quantity of buttons and LEDs placed on the surface of the board. Advanced students will also need to explore the interaction of parallel processing, including interprocess communications. To accommodate the parallel processing needs of more advanced students, the board 4
needs to host two at least FPGAs with 100 interconnect wires between them, making it possible to support projects using parallel processes. The physical dimensions of the board’s design (length, width, and height) were determined by a balance of cost and performance. Since cost increases in a direct relation with any of the three dimensions, it was preferable to keep the board small, but the board needed to be large enough such that all silkscreen writing would be visible to the students. Additionally, the height of the board (number of layers) was driven by the number of voltages required and the number of inputs and outputs on the FPGAs. Additional cost drivers are vias (vertical pins used to connect layers) and corners (four are standard, but space constraints can require that the shape of the board be modified to fit in a confined space). The heart of the board is the dual Virtex-1000 FPGA devices. At the beginning of this project, these devices were state-of-the-art with a value of $500 each. These parts are made in a 560-pin ball grid array package, with 560 solder joints located on the bottom of the chip for soldering the chip to the board. These chips are considered to have the processing capacity of one million system gates. UNM received a donation of 500 of these devices at the start of the project. An additional requirement was a highly filtered power supply. Power, noise filtering, and grounding are critical parts to ensuring every device on the board can operate in a powered state. Power must be brought onto the board for all components to function. The important consideration is to attempt to minimize number of different voltages required on a platform, thus simplifying the circuitry involved. The Xilinx® FPGA requires a 3.3-volt (for inputs and outputs) and 2.5-volt (for internal requirements) 5
DC power source. With that in mind, a great deal of effort was placed into ensuring that all devices selected could operate on one of the two voltages required by the FPGAs. Filtering of power for programmable logic is a large part of any board development project and is normally accomplished using bypass capacitance which entails a large quantity of capacitors in various sizes that pass any unwanted frequencies to ground. Different capacitive values filter different unwanted frequency bands. Although the other components usually don’t require this extra power input filtering, the cleaner power source does not cause any additional problems. To ensure adequate access to ground and voltage signals, one entire layer of the board was devoted to each of these components (3.3-volt DC, 2.5-volt DC, and ground). To communicate with (and program) the board a multitude of connection schemes and protocols were implemented.
Communication with the board involves
communication for programming and communication for operations. Communications for programming is the act of initializing the FPGA and memory with an externally generated programming file. Communications for operations is the way that a user would interface between the board and the outside world. To interface with the existing series of Digilent peripheral boards, dual 40-pin connectors were installed. Digilent makes an extensive set of input and output peripheral boards that mate to this type of connector. Digilent has a standard configuration for their 40-pin connectors in terms of programming, signaling, power and ground. This scheme was followed in the XUP-UNM platform. A benefit of dual 40-pin connectors is that UNM has been using the Digilent input and output peripheral boards for many years. The design I choose will allow more advanced students to add plug-in boards to the main
6
XUP-UNM board and quickly add additional functionality.
This means that my board
will be of use to both basic and advanced students, and will allow pre-existing projects using standard Digilent configurations to interface with the new boards. The new boards also had to interface with existing and planned Digilent daughter boards, so that they would not become obsolete in the near future. In advance of the development of Digilent’s new high speed daughter boards, dual 140-pin high-speed connectors were mounted to the top of the board. At the start of this thesis project, Digilent announced that they were to begin development of a new series of 280-pin daughter boards. These boards would mount on top of their new FPGA boards and would provide advanced capabilities in terms of Ethernet, memory, and ADC/DAC. These boards were only in the design stages during this thesis project.
Close
coordination was made with the design engineers at Digilent to ensure that all interfaces for their future products would directly interface into the XUP-UNM platform. This was difficult since the project required designing connectors to interface between the XUPUNM board and Digilent’s high-speed daughter boards – neither of which actually existed. However, by working closely with Digilent, I have been able to build a board which will interface efficiently with both the old and new generation of Digilent boards. This enhances the usefulness and cost-effectiveness of my project in the future. Serial and parallel connectivity was needed on the board to allow for serial interfaces with computers or other devices. Therefore, both 9-pin and 25-pin connectors and associated interface circuitry was placed on the board to ensure the ability to perform operations with devices that use standard serial and parallel connectors. One such device that utilized this interface was the HyperTerminal monitor.
7
The parallel connector
allowed for programming the board through the JTAG chain.
This feature was
implemented on earlier Digilent boards and added the feature of allowing students to program the JTAG chain devices without having to connect or disconnect cables. In a project of this magnitude, verification and validation of the requirements and design was crucial. There is a relatively high cost with building the initial prototype of a board. It was critical to minimize errors before the board was actually built. The cost of finding errors at this stage is much less than having to modify hardware once the board is built. Therefore, a series of formal design reviews were held to ensure that a valid design was captured. This type of validation of requirements to design is important to ensure correct application of resources. The initial design review was conducted with UNM and Xilinx® engineers. This was a review at the initial stages of the specification document, or a requirements review. At this point the focus was design decisions, features desired, and program status. In large projects of this nature, the possibility of making a small error is large. The more sets of trained eyes that look at the work, the greater the chance that errors will not be overlooked. Several critical issues were identified during this phase that led to changes in hardware choices. The final design review was conducted with the initial design review team and additional PCB design engineers from Boeing and Xilinx® corporations. The design review team was provided with the schematics, Bill Of Materials (BOM), specification document, and board layout diagrams one week before the design review to ensure adequate time for review. This review was much longer and went into much greater detail. The inclusion of the additional design engineers helped to identify new and 8
critical problems. The review was focused on the detailed parts of the project (resistor values, terminations, trace length, etc.). By this point it had already been determined what parts would be used, and time was spent to make sure they were correctly implemented.
1.3 Results
After the design review, a series of two prototype runs were completed. A prototype run is nothing more than a very small quantity of the design. In this project, the initial prototype run was for six boards. A complete check of each of the runs was performed prior to soldering on the first component. The first prototype run identified several key problems. The original power design (which allowed one voltage regulator to feed another) would not handle the long term demands of being powered for more than four hours. This was a requirement as students would possibly leave the board powered up and leave it unattended for extended periods. The second prototype run provided platforms that were populated with components and distributed to other locations for testing. The second run solved the power problems that had plagued the first prototype run. Several small problems were still found on this second run but they were considered minor as a workaround solution was available.
9
Testing of the boards consisted of continuity checks with no parts installed. After that was completed, the power section was added. This was an extensive project as it involved hand soldering approximately 120 capacitors that make up the power filtering grid. Voltage stability was measured using test equipment to ensure unwanted transients were eliminated before they reached critical equipment. Next, each component was added and checked for correct operation.
1.4 Conclusions and Recommendations for Future Work
In conclusion, the project was a success in that a stable and sturdy student platform was created. This platform has been used in course work at UNM, West Point, and two universities in Texas. It is robust enough to allow for a wide range of projects and rugged enough to withstand the rigors of student use. The problems with power in the initial design were corrected, and the resulting solution is suitable for both basic and advanced students. There are several ways that my work can be extended in the future. First of all, online tutorials would be a great addition. Providing tutorials for all level of projects from simple to complex would really be a benefit to professors who are considering using the platform for their student projects. In addition to tutorials, increasing the power and robustness of the platform would be a logical step.
Adding a new Virtex2Pro FPGA with its embedded PowerPC
microprocessor would increase the power as well as the robustness of the platform. In 10
terms of peripheral support, adding a VGA or firewire I/O capability would further increase the range of project possibilities. Additional testing would provide additional robustness for the platform. Prior to going into full production, one additional prototype run would ensure all the small items that currently exist are rectified. Prior to this prototype run, an exhaustive series of testing using a regimented test plan should be completed. As a final step, when peripheral support and additional testing have been accomplished, a logical step for this project would be to take the development of the circuit cards into production. At this point, it would be appropriate for a small team to start a company and begin making, marketing, and developing the board commercially. I have already been approached by venture capitalist to proceed into production but at this time, there are no firm plans for this course of action.
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Chapter 2 An Introduction to Programmable Logic
2.1 Background
In 1984, Ross Freeman invented a new technology called the Field Programmable Gate Array. At that time, Feeman, Bernie Vonderschmitt, and Jim Barnett started a company called Xilinx [28].
In 1985, Xilinx® introduced their first product.
The
XC2064 was a radically different approach to prototyping new designs. The XC2064 could operate at 50MHz. It had 68 pins and 64 4-input Look-Up Tables (LUTs). Programmable logic (i.e. boards that can be reconfigured) was motivated because re-programmability is a method for designers to get into a market faster and stay there longer. Programmable logic allows the design engineer to begin creating the interfacing before the final conceptual design is complete. Upon completion of the final design, the engineer creates a description of the desired circuit using a common design methodology (Hardware Descriptive Language, schematic capture, or state machine) and then transfers that to the programmable logic. The beauty of this concept is that if there is a change to the requirements, only the underlying schematic or code need be changed. The hardware can remain as it is. This relates directly to quicker time to market which increases profit. Programmable logic is quickly becoming an item of major importance in any Computer Engineering, Computer Science, or Electrical Engineering curriculum.
FPGAs and
CPLDs have given developers the tools that allow them to more quickly develop products
12
and allow them to change the functionality of a device without the necessity of changing the hardware itself. Previous designs revolved around Application Specific Integrated Circuits (ASIC) implementations. ASIC design methodology is based on the concept of getting the design correct and making a large quantity cheaply. If designed correctly and produced in large quantity, this process allows for inexpensive development of hardware platforms. The problem arises when there is a design change. With ASIC design, the hardware is fixed and unchangeable. Many times, the measure of a company’s success (or failure) is its ability to be first to market with a new product. These older processes require a great deal of time and can be expensive since it is often necessary to discard any unused hardware when the need arises to make minor changes to the design. The Reed Electronics Group pointed this out in their article Narrowing The Cost Differences: FPGAs vs. ASSP. “In the past, the challenge of meeting advanced performance requirements for high-volume products have been most cost-effectively met using either an application-specific integrated circuit (ASIC) or a suitable application-specific standard product (ASSP). While ASICs have historically offered the lowest cost path to achieving the highest level of performance, the benefit has been offset by a lack of design flexibility, lengthy time to market and high development risks. ASSPs, on the other hand, are lower risk in terms of time to market and development success, but still lack the flexibility offered by programmable logic. Off-the-shelf ASSPs and microcontrollers can have an additional liability: obsolescence. Most hard-core embedded processors become obsolete over time and are discontinued. As a result, manufacturers who are using obsolete processors are forced into costly and time-consuming hardware redesigns and software application rewrites. Such a redesign may even require a complete change in the instruction set architecture, from one family of processor to the next, leading to an even greater investment in time and money [15].”
13
Customers now want to add features to their existing hardware (cellular phones, PDAs, etc.) without the necessity of replacing the entire device. Users want to be able to reprogram the device and obtain the new feature without purchasing an entirely new case. Another major advantage to programmable logic is not in the development stage but in the prototyping stage. In December 2003, Electronics Weekly along with the Celoxica Corporation did a survey to try and gain a better understanding of who was using programmable logic instead of ASICs and why. In their report ASICs do battle with FPGAs - a survey by Electronics Weekly and Celoxica into ASIC and FPGA design trends, Electronics Weekly found the prototyping benefit to be a major feature. “The answers to the online survey, completed by 923 people, yielded some surprising results. Over 85 percent of those completing the survey are using FPGAs, while under half (47 percent) are using ASICs in their end product. Just 14 percent use ASICs exclusively, compared to 53 percent who use FPGAs exclusively [8].” In the survey, Electronics Weekly determined that over 85 percent of those in the survey are using FPGAs even if when they are not using them in their end products. This is due to the benefit obtainable in terms of quick prototyping.
2.2 How Programmable Logic Works
A Programmable Logic Device (PLD) is an electronic component used to develop digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined
14
function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed [29]. The beginnings of today’s modern programmable logic devices came in the form of simple devices called Programmable Logic Arrays (PLAs), Programmable Array Logic (PAL) or Generic Array Logic (GAL). These devices were very simple but they showed great promise in that they could combine the functions of several 7400-series TTL chips into a single device. This reduced the total number of devices on a board thus reducing the overall cost. The Xilinx® Corporation took this initial idea and created two radically different variations on the original concept. They introduced a way to modify hardware operation and functionality based on hardware descriptive languages.
They developed two
variations of hardware products. The two variations are the FPGA and the CPLD. The overall concept of programmable logic is the same for both CPLDs and FPGAs. The differences in the devices are in terms of volatility, routing, and other metrics. The choice of which one to use is based on the specific task required. FPGAs were chosen for this project for reasons presented earlier. These two types of devices are important to engineers as they provide them with several benefits over traditional ASIC implementations. Kevin Morris of FPGA Journal explains the benefits to engineers. “As ASIC costs skyrocked, however, many companies started to look at the feasibility of using FPGAs for more than just consolidating the leftover logic from the project that couldn’t, for some reason, go on the ASIC. While the FPGA solution would solve many of the most difficult problems with ASICs: frequent revisions, long lead times, huge NRE charges, and moving standards, FPGAs had their own limitations that prevented them from being useful in key roles in many, perhaps most, applications. Aside from the well-known cost, gate-count and operational frequency limitations, FPGAs were power-hungry, lacked the rich
15
libraries of IP available on ASICs, had little or no memory flexibility, and couldn’t get data on and off the chip at the required speeds. Today’s high-end FPGAs have addressed these issues and are finding their way into a central role in more and more systems [27].” The engineers can start their design and leave some of the internal interfacing issues to later in the project. Since the internal logic is based on a hardware descriptive language, most of the specific details do not need to be finalized before the design of the associated external connectivity. The ability to reprogram the device also allows a way to correct errors that are discovered once the design portion of the project is completed. By giving the ability to reprogram the inner workings of the devices, increased functionality can also be added later in the life cycle of the project to provide for user upgrades. In their simplest form, FPGAs can be thought of in terms of Figure 1 below.
Figure 1. Simple FPGA Dataflow
The flow of information into (and out of) the device is through Input and Output Blocks (IOBs). IOBs form a mechanical ring around the outside of the device and are the only way for data to enter or leave the device.
They provide the interfacing format
conversions for many accepted standards. Once the data is on the device, it is routed via
16
optimization algorithms to slices. Each slice contains a number of Complex Logic Blocks (CLBs). The CLBs are nothing more than Look-Up Tables (LUTs), Carry and Control Logic, and Registers.
All FPGAs contain the same scheme.
The biggest
difference between inexpensive and expensive FPGAs is the number of IOBs and slices. For example, a Spartan 3 FPGA has 108 IOBs, 960 slices, and cost less than ten dollars. The Virtex-4 LX FPGA has 960 IOBs, 89,000 slices, and costs around ten thousand dollars. Additional information on IOBs and CLBs are presented in Section 3.4.2. The FPGAs used for this project are from the Virtex family.
To better
understand how programmable logic works, it is beneficial to first understand how projects can be developed. The easiest way to develop FPGA and CPLD projects for Xilinx® devices is by using the Xilinx® Integrated Software Environment (ISE) suite.
Figure 2. ISE Design Flow
The process shown in Figure 2 (courtesy Xilinx®) is reflective of an ISE programmable logic project. There is a selection of Design Entry possibilities. Several of these include: •
VHDL/Verilog code (Hardware Descriptive Language)
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•
Schematic capture
•
Finite State Machine
Once the design is done, synthesis converts all the design files into a single netlist. Implementation takes the netlist and performs “place and route” which develops the logic into the specific hardware device. There are many sources of student projects involving programmable logic available through the Internet.
As the industry demand has
increased, so has the university desire to provide this valuable knowledge to the students. The introduction of programmable logic at a very early phase of the curriculum is shown in the Berkeley CS152 course [5]. Another example of introducing Xilinx® resources at an early stage is by William Sawyer with his CS223 Digital Design course from Bilkent University [16].
The University of New Mexico [18] completed an extensive set of
tutorials developed for programmable logic.
Each of these series of tutorials leads
students from project design through programming of actual devices.
2.3 Practical Application of Technology
One additional source of background in developing programmable logic into an education environment was done by Clint Cole [6] in his Masters Thesis entitled “Computer Engineering Curricula: Managing Revolutionary Change”. Mr. Cole is the founder of Digilent Incorporated (a major developer of prototyping platforms for Xilinx® hardware).
Through collaborative efforts with Digilent, access to all their design
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references was made available [7]. Their design references, schematics, and manuals were critical in quickly developing proper interfaces. The first Xilinx® VHDL and schematic projects at the UNM Electrical and Computer Engineering Department were developed in 2000. At that time, there were very few prototype platforms that allowed students to make reliable projects that could be used repetitively in a classroom environment. The ability of having projects that can be repeated over and over again with identical results is critical in a classroom laboratory environment, because if all the students in a lab can complete a project and obtain identical results, it adds credibility to the platforms, projects, and learning experience. Digilent designs a series of highly reliable academic programmable logic platforms. Mr. Cole, working on his masters’ thesis, realized the shortcomings in other company’s prototyping platforms.
To allow the academic world to transition from antiquated
hardware and software to modern programmable logic requires two things. It requires a professor willing to embrace teaching modern technology and resources to implement the changes. The ABET (Accreditation Board for Engineering and Technology) organization is responsible for reviewing engineering teaching institutions as new technologies are introduced into the classroom. Specific curricula requirements exist that must be met by all accredited institutions. In a document entitled “Criteria for Accrediting Engineering Programs,” the commission requires that student performance be monitored to ensure that the skills gained are consistent with curricular objectives and with industrial needs. This document states:
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“Engineering programs must demonstrate that their graduates have: a) an ability to apply knowledge of … engineering; b) an ability to design and conduct experiments, as well as to analyze and interpret data; c)an ability to design a system, component, or process to meet desired needs; …; e) an ability to identify, formulate, and solve engineering problems; …; k) an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice [1].” Cole’s series of Digilent and Digilab boards were the “modern engineering tools” UNM was looking for. They allowed the project to move forward with development using tools that were of a high quality and very reliable. According to Cole: “The first step in program development was the design and development of the Digilab kit. Digilab was conceived to provide students with unlimited access to stare-of-the-art design hardware and software” [6]. The XUP-UNM board was designed to be the next phase in this evolutionary process, to continue with interfacing with Digilab, and to allow for more complexity in projects.
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Chapter 3 Methodology
3.1 Structured Design Process
A good final project is best achieved by beginning with a good design process. There are many excellent formal design processes. Since the beginning of this project, a great deal of personal study has gone into many of these processes. Although many are fundamentally designed for software projects, their application to any large-scale project is directly relevant. Sound principles always justify their initial expense. Just to name a few, there is the waterfall method, the spiral method, and the extreme method. All exist with their own collection of positive and negative attributes [4]. The one that seems to be most positive was the generic life-cycle model by Ould and Unwin [14], illustrated in Figure 3.
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Figure 3. The Generic Life-Cycle Model [14] Although designed for software projects, this structured plan of attacking a project allows an engineer to understand the necessity of completing individual portions of the project prior to proceeding to the next step of the project. It also forces the designers to address not only how the individual sections will be designed and tested but also how the system will be tested as a whole. This method allows for analysis of most aspects of the project prior to beginning. The first step in this process is the use of the “User’s View” to develop a Requirements Document (or in the case of this project, a Specification Document).
3.2 Requirements Analysis and Available Resources
The requirements document is meant to develop an understanding of what the final project will accomplish and how it will do so. The requirements document for this project (see Appendix A) explored this question in detail. It explored the theory behind the selection of each part and the purpose within the board design. The requirements 22
document was later translated into a user’s manual to accompany the first delivery of circuit cards.
3.3 Tool Selection
For the board design and layout, development tools manufactured by the Mentor Graphics Corporation were used. For schematic capture, the Design Capture software and for Circuit Card development, the Expedition PCB packages were used. Design Capture is a development tool that lets a designer set up a project schematically. For this step to be successful, the designer needs to have previously made (or have available) “schematic” blocks for each piece of circuitry desired to be used. These blocks are called symbols. For very simple items (capacitors, resistors, etc.), these symbols exist within the standard package. All the others had to be created. Prior to making them, a thorough knowledge of each component was needed. For the newly developed symbols, it is only necessary to show signals that are needed for connectivity to other symbols. Anytime connections existed to voltage or grounds, these would not need to be identified in the design of the symbol. The symbol for the 560-pin FPGA took approximately 75 man-hours to develop.
The other symbols took less - but still
considerable - amounts of time. Once the entire project is designed into schematic form, it is processed to create a common database. Expedition PCB is used to take the common database to the next step. This next step is where the bulk of the work is done. 23
For each symbol, there must be a
corresponding cell (physical footprint on the board). Some cells were simple (resistors) and some were very complicated requiring many person-hours to design (switching power supply, SRAM, FPGA, etc.). Using a package where the bulk of the cells already existed would have reduced development time, but UNM did not have access to this possibility due to cost constraints. The packages existed but were beyond the allocated budget of this project. All of the cells (along with all other design files) are freely available at the University’s XUP website www.ece.unm.edu/xup. The procedure that follows details some of the highlights for the design flow for the Expedition PCB design software. The first time Expedition is launched, all errors associated with the Design Capture portion of the project will need to be cleared. Common errors (or items that could show up erroneously as errors) would be duplicate nets (using the same connection name more than once) and unconnected nets (wires not connected). The next step is to place all the cells onto the virtual board. This takes quite a bit of thought and time as the placement of parts both on top and on the bottom of the board determines trace length (critical design criteria). Once all parts are placed, it is time to have the software begin to connect all the nets within and between layers of the board. Approximately 1300 individual runs existed on the board. This did not include the two voltage planes (3.3 volts DC and 2.5 volts DC) and the ground plane. Performing this placement and spacing of all these runs can take a great deal of time. The software doesn’t always finish successfully and sometimes it is necessary to rearrange parts and rerun the tool. This is because the placement choices may place unobtainable connection restrictions on the design. Once this phase is done, the next major step is the creation of the files that will be sent to the manufacturer to build the bare circuit board (no soldered
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components). These files are called Gerber files (for the “gbr” file extension). RS-274-D is the technical name for Gerber Format, which is the industry standard photo plotting language [9]. It is critical to do a compressive review of the pictorial output of this process as project-ending errors can sometimes be identified here.
Figure 4. Sample Gerber Picture
A sample Gerber file depicting one single layer of the XUP-UNM platform is shown in Figure 4. These files are very difficult for the untrained person to review but are the absolute final step before funds are expended in board production. This is an excellent time to take the physical parts and place them on top of the printed PCB Gerber file output to ensure that the cells were designed correctly and that the actual parts are the same dimensions as what was planned.
3.4 Designing the Board
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This board consists of quite a large selection of parts. The BOM lists over 250 parts (see Appendix B). A greater discussion of parts is included in the Specifications Document (see Appendix A). In some cases, quite a few revisions to the design for major sections occurred over the duration of the project.
Figure 5. Overview of Board Design
Figure 5 shows the hierarchical view that was used in designing the board. A technical description for the implementation of each of these sections is detailed in the specification document (see Appendix A). The discussion that follows will focus on the final configuration and the major sections.
3.4.1 General Board Parameters
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The decision to make the board the chosen size and number of layers was made very early in the design process. As a rule, the smaller the board and less number of layers, the lower the cost. This is because you pay for board fabrication based on the physical size of the board (material costs) and on the complexity of lining up layers of boards together. The minimum size and number of layers is driven by the necessity to run connections to each component’s electrical pins, enough space for placement of every part, and where necessary, enough space to allow for isolation of parts from each other. The size of each Ball Grid Array (BGA) was known. Each BGA would also need 560 connections underneath them.
Since these devices were the largest and most
complicated parts on the platform, they were a leading factor in determining board size, number of layers, and other design considerations. After considering the size of these major sections and all the other associated devices, eight layers were considered the minimum number of layers possible for this project. This decision was made based on advice of senior designers (Frank Wirtz of Xilinx® and Howard Pollard of UNM) providing guidance on the project.
3.4.2 Virtex 1000 FPGA Devices
The Virtex programmable gate array, shown in Figure 6 below, comprises two major configurable elements: Configurable Logic Blocks (CLBs) and input/output blocks (IOBs) [25]. Their functions are: •
CLBs provide the functional elements for constructing logic
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•
IOBs provide the interface between package pins and the CLBs
Figure 6. Virtex Architecture Overview
Figure 6 (courtesy Xilinx®, Inc) shows that the only way that data can get into the processing unit is through the IOBs.
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Figure 7. Virtex Input/Output Block
The three IOB storage elements shown in Figure 7 (courtesy Xilinx®, Inc) function as either edge-triggered D-type flip-flops or as level sensitive latches. The IOBs support a wide variety of I/O signaling standards. Additional information on I/O standards can be found on the Xilinx® website [22]. three flip-flops.
Each IOB has a clock signal that is shared by the
Although not shown, all pads are protected against damage from
electrostatic discharge and from over-voltage transients. All IOBs on the chip support IEEE 1149.1 compatible boundary scan testing. This is how the programming and diagnostics of the chip are performed. Once the data is evaluated, it is passed to the logic blocks for processing.
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Figure 8. Two Slice Virtex Complex Logic Block
The basic building block of the Virtex CLB is the Logic Cell (LC). A Virtex LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flipflop. Each Virtex CLB contains four LCs, organized in two similar slices as shown in Figure 8 (courtesy Xilinx®, Inc) [26]. The function generators are developed as Look-Up Tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16x1-bit synchronous RAM.
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Table 1. Virtex Family Capabilities
As shown in Table 1 above (courtesy Xilinx®, Inc), the XCV1000 device used in this project is the largest device in the standard Virtex family. The significance of the Table 1 is that the device used has over a million system gates of processing power.
For
comparison purposes, a system gate can be thought of as a two-input NAND gate. This translates to the fact that each of XUP-UNM Virtex FPGAs can do the processing power of approximately one million two-input NAND gates worth of work. This is a significant capability given that the average FPGA in a student platform usually ranges from 20 thousand to 200 thousand system gates.
Figure 9. FPGA Connection
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Figure 9 details the desired connections and number of connections that were assigned to each of the connectors. These numbers were based on the requirements of the specific final interfaces.
3.4.3 Board Material Characteristics
It was determined very early in the project that eight layers would be needed to accommodate two voltage planes, a ground plane, and all the additional input and output routing that the board was going to require. A lot of this decision was based on the experience of other engineers (Frank Wirtz of Xilinx® and Howard Pollard of UNM) that had done this type of work before. Prior to actually placing all the symbols on the board and routing them, it is impossible to tell exactly how many layers are the “minimum.” To reduce cost, a rectangular board design with only four corners was chosen. The more corners and cuts, the more the cost increases since it is more difficult (and time consuming) for the machine to manufacture. The quote shown in Appendix D is from the chosen board manufacturer (4PCB Design) and details the prototype choices. The major choices that increased prototyping costs were the silk screening on the top and bottom of the board, and doubling of the traditional board thickness. It was felt these choices would produce a better product that would be easier for students to understand and would stand up more efficiently under long-term student use.
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3.4.4 Bypass Capacitance
The unique architecture of modern programmable gate arrays dictates their input voltages to be exceedingly clean and free of transient noise. To that end, the Xilinx® Corporation produced a document for design engineers to utilize in developing filtering through the use of bypass capacitors [2]. The board designed for this project required two separate voltage levels (3.3 volts DC and 2.5 volts DC). The FPGAs require 3.3 volts DC for input and output and 2.5 volts DC for their inner power. The design was developed so that everything on the board would function by utilizing one or the other of these supply voltages. Although the current draw in the board’s components changes, the power supply/distribution system cannot respond to that instantaneously. Shown below in Figure 10 is a pictorial depiction of the major components of a power distribution system that could easily be related to the XUP-UNM project.
Figure 10. Simple PDS
The power supplies and regulators are the first major portion of any Power Distribution System (PDS). These will be described in much greater detail in the next section. The
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next major section of the PDS is the bypass or decoupling capacitors. Their function is to provide a short energy source to respond very quickly to changing current demands. The inductance shown in Figure 10 above is due to many factors. One of the major factors is that of the inductance involved in the current paths of the circuit board. Smaller physical capacitor size leads to less parasitic inductance. Less inductance leads to less noise on the power system – a desired effect. For these reasons, it was important that the smallest package size available be chosen. The majority of this designs capacitors were of a 0805 package size since it provided the project with the largest selection of available capacitive and voltage values while taking up less space on the board. Although a slight increase in filtering quality might have been obtained by going to a smaller package size (0603 or 0402), it was felt that the increased complexity of dealing with this small of a component would have made any benefit completely overshadowed by the increase in work required to deal with size and mounting issues. The most common package sizes for capacitors and resistors are 0805 (2.0x1.25mm), 0603 (1.6x0.8mm) and 0402 (1.0x0.5mm). Existence of vias in the proximity of the capacitors was another major concern. The connections between layers of the board are accomplished are by means of vias. A via is a metal shaft that runs vertically through the board. Some vias run through the entirety of the board while others are designed only to connect one layer to another. Although there are “blind vias” and “hidden vias” that are invisible from the outer layers, these cost much more money so were avoided.
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Figure 11. Inductance Versus Via Placement
Figure 11 (courtesy Xilinx®, Inc) shows, that the closer a via is to the capacitor, the less amount of undesirable parasitic inductance the path produces.
It is critical for the
capacitors to be as close a possible to the devices served. According to the Xilinx® Corporation (the FPGA manufacturer) [2], the optimal target placement radius for capacitors should usually be in the range of no more than 1.53 inches. The smaller the value of the capacitance, the smaller the radial distance from capacitor to serviced device. Xilinx® provided the example that a 0.001uF capacitor should have a serviced radius smaller than an inch whereas the larger 4.7uF tantalum capacitor could be up to 123 inches in radius (serviced zone). The largest quantity of exceedingly small capacitors (1pF and 0.01uF) were placed directly underneath the most sensitive items (the Virtex FPGAs). To keep the impedance profile smooth and free of resonance spikes, Alexander [2] recommended a series of capacitors for every decade of capacitor value range. 35
Although the exact capacitive value is not critical, it is important to have some member of the family in every range. As seen in Table 2 (courtesy Xilinx®, Inc) below, Xilinx® proposed the following ratios for a generic selection.
Table 2. Bypass Capacitance Selection Criteria
It should be pointed out that this chart was redone by the Xilinx® Corporation in April, 2004 but that the general theme of a wide range of capacitor values remained consistent. The choice of percentages of capacitor values was based on the original document and not necessarily on the percentages shown in Table 2. The original document has been replaced on the Xilinx® web site and is no longer available
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Capacitor Value
Quantity Used
1 pF
38
0.01 uF
19
0.1 uF
36
1 uF
6
10 uF
4
100 uF
3
Table 3. Capacitor Values Selected
Shown in Table 3, is the selection of capacitors for the XUP-UNM board. From a comparison of the two tables, a lot of effort was made to follow the PDS design specified by the FPGA device manufacturer.
3.4.5 Power Section
The board was designed with the overall concept that everything that resided on it could function with only one of two different voltages. The available voltages would be 3.3 volts DC and 2.5 volts DC. The 2.5 volt DC output was developed using a simple voltage regulator that took the 3.3 volts DC and converted this input into a desired 2.5 volt DC output. This is a small enough difference that even at a large current demand, this regulator can perform this task and remain cool. The heart of the voltage section for this project was the Texas Instruments TPS54616 Buck Switching Power Supply [3].
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This powerful package can provide a constant six-ampere output for a long period of time and remain at an acceptable temperature level. Several factors allow this to occur. First, the nature of the switching power supply versus the standard regulator allows for cooler operation. Secondly, the design of the placement layout on the board allowed for greater heat dissipation. This device is actually soldered to vias underneath the chip for heat dissipation. This allows for the heat to flow from the bottom of the device through underlying vias and then to a surrounding heat sink “ring.”
Figure 12. TPS54616 Mounting Design
Shown in the center of the picture (in Figure 12) are the eight vias (pink dots in center) where the bottom of the TPS54616 mounted. The large dark colored square represents the area of the board devoted to heat sink for dissipating the heat developed by this device. Considering that it was designed to operate in the six-ampere range, this amount of board reserved for heat dissipation was considered acceptable. Designing for this device was made easier by utilizing a free software package from Texas instruments. The Swift software package is designed for the TPS54616 [17].
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Figure 13. Swift Software Schematic (courtesy Texas Instruments)
As shown in Figure 13, the software allows a user to enter the desired input voltages (and other data) and then it determines the configuration of capacitors and resistors. It even provides part numbers and manufacturer information. Shown below in Figure 14 is an example of one of the different types of statistical and analytical data that can be obtained during the design phase.
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Figure 14. Response Graph for TPS54616 (courtesy Texas Instruments)
The biggest obstacle I observed in using this software and designing using the TPS54616 was in the placement of parts. I placed the associated capacitors and resistors close to the TPS54616. But, close wasn’t good enough for the device to work. After extensive troubleshooting it was determined that if the capacitors were not located directly underneath the power supply, they were too far away and the unit would never turn on – something the tool never identified.
3.4.6 JTAG Chain
In the 1980s, the Joint Test Acceptance Group (JTAG) developed a system to perform debugging using a boundary scan concept. This approach was sanctioned in 1990 as IEEE standard 1149.1 [10].
A side benefit of this resulting work is a
methodology for programming any item that has an applicable JTAG chain. 40
Figure 15. JTAG Representation for Input and Output
As shown in Figure 15, the chain depends on the successful transference of the input data (TDI) to the output (TDO) [11].
The Test Access Port (TAP) controller is a 16-state
FSM that responds to the control sequences supplied through the Test Access Port [12]. Each of these 16 states is only activated on the rising edge of the TCK signal and is dependent upon the TMS for mode selection. The main portions of the chain on the XUP-UNM consists of six items. Those items are Voltage, Ground, Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). All six items are critical but the voltage and ground were omitted from this visualization for simplicity purposes.
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Figure 16. JTAG Chain Configuration Design
Figure 16 details the six possible items on the XUP-UNM platform that can be programmed using the JTAG chain. These items are the two Virtex FPGAs, the three 18V04 SPROMs, and any item that might be eventually located on the Digilent highspeed bus (HSB) daughter board. As of the time of the second prototype board run, none of these daughter boards had been built. The Digilent Corporation provided all the pin specifications and debugging was deferred. Programming through the exposed JTAG header pins and the 25-pin D connector was accepted as a suitable way to program all devices on the board. The jumpers provided allow the user to include or exclude any specific device on the chain.
3.4.7 Static Programmable Read Only Memory (SPROM)
One feature of using FPGA programmable logic over CPLD logic is that the FPGA devices are volatile. This means that each time the device has the power cycled, the stored program is lost and has to be reloaded. To accommodate this, many designers 42
place memory on the circuit board and connect it through the JTAG chain to allow programming code to the memory and then (upon power cycle) program the FPGA by means of the SPROMs. For this purpose, XC18V00 series SPROMs were chosen [24].
Figure 17. SPROM Interface Overview (courtesy Xilinx®, Inc.)
Figure 17 shows that the basic purpose of this device is to receive information through the JTAG chain, store it in memory, and deliver it in a serial or parallel format. Since the XCV1000 FPGA devices use 6,127,744 configuration bits, each FPGA would require one each XC18V04 and one each XC18V02 PROM solution. To accommodate two of the XCV1000 FPGAs, three each of the XC18V04 devices were used. This was done by cascading the devices together in a daisy chain configuration.
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Figure 18. Master-Serial Configuration Mode (courtesy Xilinx®, Inc.)
Figure 18 shows how it was necessary to configure the wiring of the input and output of the memory to the FPGA devices. The master-serial configuration was chosen to provide the capability for programming using the JTAG chain. This also allowed all devices to share a global clock.
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Figure 19. JTAG Chain Configuration
Figure 19 shows the entire JTAG chain. The three XC18V04s are on the left side. The JTAG chain on the XUP-UNM platform recognizes each of the XC18V04 devices along with the FPGA devices.
3.5 XUP-UNM Reviews and Prototypes
3.5.1 Initial Design Review
The initial design review is the process of performing a first check to ensure the project is proceeding properly and that the engineer and the customer are working towards a common goal that will satisfy system level requirements. This step should allow everyone to step back from the project and take a long look at why the project is being done, what is being done, and how is it is being accomplished. This review was accomplished early in the spring of 2003. 45
Finding items at this stage saves countless hours and money as compared to finding the problems later in the process. The cost of finding problems at this stage is lower because the board has not yet been constructed – the only resource needed is person-hours for labor. If problems are found later, in addition to the person-hours, you also have costs associated with necessary modifications to hardware. For a circuit board assembly project, this review should have a large portion of circuit board design and assembly engineers on the team.
3.5.2 Final Design Review
This is the phase in the project (before prototype boards are ordered) where a last check is done to ensure that everything is correct. Conceptual ideas are no longer critical at this point in the process. Only the technical aspects of the project (e.g., voltage levels, impedance, etc.) are reviewed. As with the initial design review, team selection is critical. An ideal team for this size project would be five circuit board design engineers. The people should be given schematics, Gerber (board layout) files, parts lists, and specification documents with at least a week to review them prior to the meeting. Gerber files are difficult for the inexperienced person to review.
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Figure 20. Top Layer Gerber Picture
As an example, Figure 20 is the Gerber visual file for the top layer of the XUP-UNP platform.
Everywhere a dot occurs, there is usually a via running between layers.
Figures 20 and 21 are not the kind of images where the average person can look at and identify problems.
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Figure 21. Layer Seven Gerber Picture
The review team consisted of experienced design engineers including Frank Wirtz, Reno Sanchez and Rick Morrales from Xilinx®, Howard Pollard from UNM, and an engineer from Boeing. They immediately found critical problems. Over a dozen items were identified during this final design review that had to be dealt with prior to ordering prototypes. Ordering prototypes is very expensive. The prototype run for only eight boards cost approximately $4,000. The later in this type of process those items are identified, the more time that is required to make minor changes.
3.5.3 Initial Prototype Run
The difference between a prototype and production run is determined by the number of boards and the quality produced by the board house. For bare boards, the
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designer can usually order 100 boards for the same price as 8 boards. The big difference between them is related to the cost of parts to populate the boards.
The cost of
purchasing electronic parts in small quantities is significantly greater than that of purchasing in bulk quantity. For this reason, it is necessary to keep the number of prototype boards to be ordered to the bare minimum – usually just enough required for system testing. In August of 2003 (nine months after the start of the project) the first run of prototype boards were delivered.
Problems were found – some that should have been
discovered before ordering the first run and some that could never have been anticipated. The biggest problem encountered with the first run of boards was in the mounting of the 560-pin BGA devices (Virtex FPGA). Most of the design assistance locally came from the Xilinx® CPLD division. Their experience with very large BGAs was limited. The mounting of the Virtex devices is a very complicated process.
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Figure 22. BG560 Bottom View
Shown above in Figure 22 is the bottom of a 560-pin BGA Virtex 1000 device. Each dot is a small ball of solder. As shown, there are 560 small round solder joints. Mounting of the device to the board entails reaching a temperature where all of the solder balls melt and adhere to the board pads at the same instant. The way it is accomplished at the local fabrication facility is that a “hood” is placed over the device as it sits on the board. Extremely hot air is then forced between the device and the board. At the correct temperature, the solder melts and a bond is created. To do this, the board is exposed to fairly high temperature. If a standard run of prototype boards (eight-layer) is ordered, the boards come in a thickness of 0.062 inches (with a tolerance of ten percent). This initial prototype run of boards measured 0.059 inches (called 59 mils). Although this was
50
within the limits of tolerance for prototype boards, it was not thick enough for mounting the devices. Before the temperature reached the level required to melt the solder balls, the board began to warp. Any warping of the boards meant that not all the solder balls would adhere properly. This made the first run unusable for all FPGA device mounting. Another problem noted was in the power section. The original design called for dual power regulators – one for each voltage required. Both regulators used a common input DC voltage jack with a 6 volt DC input. One regulator was to supply the 3.3 volts DC and the other was to supply the 2.5 volts DC. The problem that was found was in the 2.5 volt DC regulator. Since the regulator was using a 6 volt DC source and providing a 2.5 volt DC output, it had to dissipate 3.5 volts DC through the form of heat. This regulator operated excessively hot and was not acceptable for long-term student operations. Some options that were considered to solve the power problems included: 1. Put two separate input power jacks on the board. This would have been the simplest change to implement (and the cheapest). It would have put the work on the user to obtain a power supply with two separate outputs. This was the way that the Xilinx® corporation handled input power on their commercial AFX Virtex platforms.
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Figure 23. AFX Power Configuration
The interconnections of the VCCInt (2.5 volts DC) and 3.3V (3.3 volts DC) at the top of Figure 23 are visible. Although this is the way Xilinx® designed their Virtex 1000 prototype platform [19], this method was rejected since it was felt that it was better to have a single input jack – less chance of error with students in the laboratory. 2. Cascade the existing power regulators from one output into another input. This would basically mean that power would be provided to the board with a single 5 volt DC input that would go to the 3.3 volt DC regulator. This regulator would only be dropping 1.7 volts DC in the form of heat – and the lower voltage meant less heat. It was determined that this amount of heat would not be a problem. One of the outputs from this regulator would be a 3.3 volt DC input into the 2.5 volt DC regulator. Once again, this regulator would only be required to dissipate a small amount of voltage in the form of heat. Although this solution seemed 52
reasonable, it was also rejected.
The reason it was rejected was based on
feedback from a senior power design engineer (Rick Ballentine of Xilinx®) that advised that when using a standard 3.3 volt DC regulator output as an input, cascading noise generated from the initial stage into the secondary stage is unacceptable. This would result in a very noisy output from the 2.5 volt DC regulator. 3. The third option that was considered and finally accepted was based on input from Rick Ballentine who worked at Xilinx® Canada. His suggestion was to use a very clean switching power supply on the entrance to the board. This suggestion would use a Texas Instruments TPS54616 Buck Switching power supply [3]. This solution had a similar theme to option two in that it cascaded devices allowing a single input voltage jack.
Figure 24. Daisy Chain of Power Sources
The major difference between option two and this option was that the switching power supply provides an extremely clean output level of up to six amperes. Since this output is very clean, it can be used as an input to the 2.5 volt DC regulator without cascading or introducing an unacceptable level of input noise. 53
The block level design is shown in Figure 24 above. Although the 2.5 volt DC output only has one purpose (providing the input ring Vcc Internal source), if that purpose isn’t done correctly then the entire board will not work. A lot of the design work that is completed with a switching power supply is done using the Swift download software. This software is discussed in greater detail in the attached specification document (appendix A). The layout of the power supply on the board was complicated since it involved placing parts associated with it in very close proximity. At the same time, a large isolation area was needed to allow for proper device cooling.
Figure 25. Power Section Layout
The blue section shown in Figure 25 is the heat dissipation ring for the TPS54616. The pink section shown in Figure 25 is the mounting location for the 2.5 volt DC regulator. Additional information on this implementation scheme can be found in the power section of the attached specification document.
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3.5.4 Second Prototype Run
In December 2003, a second set of prototype boards were ordered. This run of boards was purchased from the same company that had provided the original prototype run. The first order had problems that should have been prevented through a cursory examination by the board house before fabrication.
The board manufacturer
acknowledged these shortcomings in their work and provided UNM with the second prototype run at a substantially reduced price. Although minor problems were found (which are covered later), this prototype run was considered to be solid. This is based on feedback from the University of Texas (Austin), the University of Texas (El Paso), West Point Military Academy and its use in UNM classroom environments (see “Conclusions and Recommendations” section for additional detail). A problem found in this run had to do with placement of capacitors associated with the switching power supply section. The Swift software [17] package detailed the parts needed but not their collective proximity on the PCB. I discovered that if C130 (10 uF – see schematics appendix for details) was more than one inch from the TPS54616 Power Pad supply, the system would not develop any output voltage. The capacitor value has a very limited range for providing filtering and my placement exceeded this limit. This limit (or placement of any other Power Pad supporting parts) is not discussed in any of the Power Pad technical documents. This problem took approximately 30 man-hours to diagnose and was temporarily resolved by moving the two parts closer to each other. 55
Another problem that was noted was in the serial (9-pin) and parallel (25-pin) connectors. Since these part cells were within the standard package for Expedition, their correctness hadn’t been questioned.
It was discovered that the signal assignment
associated with their placement was 180 degrees out of phase. Both of these connectors would be correct if mounted upside down (on the bottom of the board). Even though these two problems seem nontrivial, they aren’t considered board failures since there are valid work-around options.
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Figure 26. Completed XUP-UNM Platform
57
Chapter 4 Results
4.1 Board Results
The board was completed and is shown in Figure 26. Results will be broken down into four major categories: •
FPGA Section
•
Power Section
•
Input/Output Section
•
Memory Section
The overall board design is shown in figure 27. The FPGA section is the two Virtex 1000 devices in the center of the board. The power section is on the left hand side of the diagram. The input and output section consists of the pushbuttons, LEDs, serial section, parallel section and all the associated connectors. The memory section consists of the SPROMs and the SRAM.
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Figure 27. Overall Board Design
4.1.1 FPGA Section
The board was fully tested using a systematic approach of first testing each module and then testing the system as a whole. The FPGAs were a very critical portion of the project. All testing and assembly was done with the purpose of being able to test the communications to (and between) these 560-pin devices.
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Figure 28. Fully Assembled Board with JTAG Connection
Figure 28 shows the board with enough parts installed to begin debugging using the JTAG programming cable (attached on lower right). Figure 28 does not show the 96-pin DINN connectors installed at the bottom of the board since they were not available when this portion of the testing was being done. The board was connected through the Xilinx software and the JTAG chain was probed.
Figure 29. JTAG Chain
Figure 29 shows the feedback from the Xilinx iMPACT software. By being able to see all three of the XC18V04 serial proms and the two XCV1000 FPGA devices, initial
60
checks proved that the entire chain was accessible. To program the devices, you highlight them and download the test programs to them. The iMPACT software is a tool used for configuration and programming of all Xilinx PLDs (FPGAs and CPLDs) and PROMs. iMPACT features a series of design wizards that easily guide the user through each step of the configuration process. With iMPACT, users: •
Can quickly shift among the various programming modes.
•
Receive instant visual feedback on all operations and testing.
•
Have support for a host of ouput file types including STAPL and SVF [30] The testing proceeded by developing a series of tests using VHDL that provided
signals to each of the modules and each of the connectors. A large portion of this code is contained in the UCF pin descriptions in the specification document. 4.1.1.1 Programming the FPGA The iMPACT software described in section 4.1.1 is what is commonly referred to as Xilinx® “back end tools.” It’s purpose is to transfer the program down to the devices on the board. Although it is the program to deliver the files to the devices, it can not be used to create the files. To create the projects, Xilinx® has provided a wide variety of design tools. Some of them are: •
EDK – used to design virtual microprocessors that can be instantiated on the programmable logic devices
•
ISE – used to develop projects using VHDL, Verilog, Finite State Machine, or Schematic implementations of projects
61
•
Sysgen – uses a collection of prepackaged cores that are tuned specifically for a particular FPGA. These cores use the traditional Simulink design environment.
4.1.2 Power Section
One of the first checks was associated with the power section.
Figure 30. Soldering Power Section
Using microscopes for soldering (Figure 30), the power section was assembled one piece at a time. After that, a Tektronics 2465 oscilloscope was used to measure the voltages. A critical measurement was the output of the switching power supply.
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Figure 31. Testing the Power Section
Figure 31 shows the procedure that was used to check out each of the individual voltages on the board. The FPGA voltages had to be within 5% of the specified 3.3 and 5 volt DC values [26]. The voltages measured were 3.301 volts DC (from the switching power supply) and 2.504 volts DC (from the cascaded voltage regulator). By then measuring the AC ripple, it was possible to determine the level of unwanted noise in the outputs. The output of the switching power supply only had 70 millivolts of ripple, which was well within the levels of tolerance. Once the voltage section was verified as correct, the board was assembled with the rest of the components (checking each module as it was installed).
4.1.3 Input and Output Section
The input and output section comprised the greatest portion of the board in terms of area and time for soldering and testing. Between the 96-pin DINN connectors, the 40-
63
pin, and the 140-pin Digilent HSB connectors, there were over 500 solder joints to make. The voltages and grounds for each of these connections were checked using a Fluke voltmeter. Once voltage and continuity checks were completed, a series of VHDL files containing counters were used to “pulse” each of the input and output pins. This methodology allowed for analysis of the signal level and quality. Another of the requirements for the project was to interface with the Digilent series of prototype platforms. As of the time of this testing, Digilent still has not released their first series of high-speed daughter boards to mount to the 140-pin connectors on top of the board. Figure 32 shows the Digilent DIO1 input and output board mated to the platform.
Figure 32. Digilent I/O Board Mated During Testing
The benefit of this series of Digilent boards is the ability to have additional capabilities (wire wrapping, switches, seven-segment display, etc. ) by merely using plug and play modules that are currently available at UNM.
64
4.1.4 Memory Section
Three types of memory reside on the board. The XC18V04 devices are SPROM memory that is used to program the FPGAs upon power cycle. The SRAM has the capability to provide memory external to the FPGA. The FPGA also has the capability to provide memory internal to the device. Figure 33 details out how the FPGA and SPROMs are included or excluded on the JTAG chain.
Figure 33. SPROM and Virtex Jumper Design
The XC18V04 is 4Mbit memory that was developed in a way that the programming signals cascade through the devices so that a single JTAG connection is all that is desired to program them.
Figure 34. SPROM on Board
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Figure 34 shows how the SPROMs were placed on the board. The JTAG feedback from the programming software shows how the devices are read back. To test them, a programming file was downloaded to each device. Once this was done, jumpers were removed and the power to the board was recycled. This forced the FPGAs to reprogram themselves from the stored program on the SPROMs. Another desire was to have the ability to have memory that was external to the FPGA. The Cypress 128x16k devices were chosen because cores (precompiled VHDL) existed for this type of memory. Although the footprint was placed on the board, the part was not populated. The electrical connections were verified but due to the belief that this was a part of the board that would rarely be needed, installation was left for the user that might need it for a specific purpose. The final type of memory is that created on the FPGA itself. To test this, a virtual microprocessor project was created.
Figure 35. V1000 EDK Project
66
Figure 35 shows the EDK (Embedded Development Kit) project that was developed to test various portions of the board. The project uses native FPGA components to develop a “virtual microprocessor” within the CLBs of the device. The Microblaze core block in the center of Figure 35 is this microprocessor. The project [31] was designed to print a text string to the screen of a hyperterminal and also to blink a single LED. There were 16k of RAM created upon the FPGA Connectivity through the UART to the hyperterminal was completed and LEDs were exercised (by choosing one LED after another for testing).
4.2 Educational Impact
From an educational point of view, there were a variety of impacts that developed from this project. They were: •
Impact to other external educational organizations
•
Impact based on my experiences
•
Impact to the University of New Mexico
•
Impact on others involved with the project
4.2.1 Impact to other External Educational Organizations
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This board was deployed to four different locations for assistance with debugging and analysis of functionality. It was sent to three universities (University of Texas (El Paso), University of Texas (Austin), West Point Military Academy), and the Digilent Corporation. The selection of universities was based on their ongoing programmable logic research. Initial feedback from these agencies is very positive. According to Colonel Bryan Goda, an instructor at West Point, “This board has great potential within an undergraduate curriculum. We are looking forward to seeing what it can do [13]”. At the other schools, the board is being used for upper level projects. The boards were distributed to the various institutions and then a series of courses were presented and sample projects disseminated. Once each school was capable of powering up the platform and downloading a sample project, little contact was maintained. Occasional follow up was performed to see if any problems were identified. There was a great deal of difficulty in obtaining documented results from these institutions. Most of the interactions were focused on providing assistance with their graduate projects and not with the hardware platform itself. The Digilent Corporation evaluated the board to ensure it was in compliance with their interfaces (current and planned).
4.2.2 Impact Based on my Experiences
This was a tremendous experience from an engineer’s standpoint. Seldom are students allowed to complete such a project involving so many differing facets of the 68
industry. The students that worked on the project were exposed to all aspects of the process including bill of materials (suppliers, costs, quality), design process (specification documents), PCB design including the software, fabrication and assembly process. The supply portion forced decisions on parts based on not only cost but heat consumption and space on boards. When dealing with a traditional schematic approach, these factors are not an issue. Dealing with the design process supplied insight into the real-world time constraints facing the industry. Exposure to the entire PCB manufacturing process gave an insight into what was required to take the final product from concept to sales. Appendix F provides a complete analysis of what is required to go into production with this product and some estimation of expected costs and projected revenues.
All this
documentation including (Specification and Users Manual, Schematics, Gerber files, Bill of
Materials,
etc.)
are
available
online
at
the
UNM-XUP
website
(www.ece.unm.edu/xup). After being approached by venture capitalists interested in developing the project commercially, the decisions about starting a company were also experienced.
4.2.3 Impact to the University of New Mexico
The University of New Mexico ECE Department also gained from this project. The project forged a good working relationship between the department and several local companies (Xilinx®, MPC Design, Electronic Parts, etc.) where future endeavors could be pursued. This has lead to new PCB collaborative projects being investigated. This project also provided an insight into the equipment that would be necessary for future 69
projects of this type, which helped to justify the purchase of sophisticated microscopes for soldering. The board is also being used in course work in the Senior Design course at the University of New Mexico. All documentation for these projects and all additional documentation (specification/users manual, schematics, Gerber files, etc.) are available online.
4.2.4 Impact on Others Involved with the Project
Others also benefited from this project including undergraduate and graduate students. Three undergraduate students were involved in the initial phases of the project as part of their Senior Design course. Each of them were assigned a specific area of the board to specialize in. One had the power section, one had the serial section and the last had the parallel section. This allowed each of them to be part of the project and become personally vested in the overall success. Several graduate students were also involved in the project. Their roles included assistance in troubleshooting and assembly. This type of experience would not normally be available in a classroom environment. Everyone involved with the project gained from the experience.
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Figure 36. XUP-UNM Platform
71
Chapter 5 Conclusions and Recommendations for Future Work
Although the board was constructed to be solid and dependable, there are still issues that cause me to recommend that one final prototype run of this platform be performed prior to proceeding to production. The major problem at this phase of the project is the quantity of work required to completely debug the board. Between the serial, parallel, SRAM, and the many other components, it could easily take six manmonths to completely debug, find additional issues, document them, and repair the files. If another prototype run were completed, the recursive debugging would have to be completed again to ensure no problems were introduced as a byproduct of any corrections made during this phase of the project. To proceed to production, three possible scenarios seem viable: 1. The entire responsibility for production could be turned over to the local board house. The fabrication facility would take all the documentation, donated parts, and specifications. They would obtain any required components. They handle all inventory and sales. This would be an effort that would result in the least amount of work for the design engineer. It would also result in the most expensive retail cost for the board. A complete study of proceeding with this possibility was conducted as part of a graduate level course in manufacturing methods. Additional details are contained in appendix F. 2. The major responsibility could be turned over to the board house. The major difference is that the design engineer would provide them with all the parts for assembly. This would reduce the price per board cost but would result in a 72
significant cost in terms of man-hours. It would be a very daunting task to order, inventory, and track all 250 different parts for 100+ boards. The board house would again be responsible for all inventory and shipments. 3. The design engineer could take on the majority of the work. The design engineer would handle all inventory, packaging, shipment, and sales. The board house would only be responsible for the manufacturing of the boards and mounting the parts. This would be the most labor-intensive option for the design engineer but would provide the most inexpensive option for the board. It is estimated that it would take approximately ten thousand dollars to make an initial production run of 100 boards (see Appendix F). The full process of taking this product into production was evaluated as part of a Graduate level course project in Modern Manufacturing Methods.
Figure 37. Extend Modeling of Production
Figure 37 shows a high-level diagram of the production modeling that was performed using the Extend software package. Through this simulation, the production level of effort was identified. It allowed analysis to be performed that would improve the estimation of man hours that would be involved. An estimation of labor required from UNM for this is that it would take a minimum of four individuals working twenty hours a
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week to control parts inventory, board inventory, debugging, sales, documentation updates, and coordination between all agencies if option three were chosen (less for options one and two). I believe these four individuals would need to be engaged for a period of one year. If this initial run of 100 boards were done, it would seem reasonable to envision the boards being made available for sale for around one hundred and fifty dollars (given that XUP would donate all the Virtex 1000 and XC18V04 devices).
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References [1] Accreditation Board for Engineering and Technology organization, Criteria for Accrediting Engineering Programs, Available: http://www.abet.org/criteria.html , 20032004 [2] M. Alexander, “Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors,” Xilinx® Application XAPP623, Available: http://www.xilinx.com/bvdocs/appnotes/xapp623.pdf, 2005 [3] “TPS54616 - Low Input Voltage 6A Synchronous Buck Converter with 3.3V Output,” Buck Switching Power Supply, Texas Instruments, Available: http://focus.ti.com/docs/prod/folders/print/tps54616.html [4] D. Budgen, Software Design, Addison-Wesley Publishing, 1995 [5] B. Brodersen, “CS152 – Computer Architecture,” Available: http://bwrc.eecs.berkeley.edu/classes/cs152/handouts/lab3.htm [6] C. Cole, “Curricula: Managing Revolutionary Change,” Masters Thesis, Dept Elect. Eng., Washington State University, Pullman, WA, 1999 [7] “Complete listing of reference material for design,” Digilent Incorporated, Available: http://www.digilentinc.com/Materials/BoardProducts.html [8] R. Ball, “Asics do battle with FPGAs - a survey by Electronics Weekly and Celoxica into ASIC and FPGA design trends,” Electronics Weekly, Available: http://www.electronicsweekly.com/Article35704.htm , 2005 [9] “Geber Format Definition,” Holophase Incorporated, Available: http://www.holophase.com/gerbfmt.htm, 2005 [10] TI Test Symposium, Available: http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/ti_jtag_seminar.pdf , 1997 [11] J. Hong, Department of Electrical Engineering, National University of Kaohsiung, Available: http://larc.ee.nthu.edu.tw/~cww/n/625/6251/BSjhhong0209.pdf , 1998
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[12] JTAG – “General description of the TAP Controller states”, Xilinx® record number 3203, Available: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=32033 , May, 2003 [13] C. Kief, “Board of Education”, Xcell Journal, Available: http://www.xilinx.com/publications/xcellonline/xcell_51/xc_xup51.htm, 2004 [14] M.A. Ould and C. Unwin, Testing in Software Development, Cambridge University Press, 1986 [15] “Narrowing The Cost Difference: FPGAs Versus ASSPs,” Reed Electronics Group Online, Available: http://www.epn-online.com/page/15836/narrowing-the-costdifference--fpgas-versus-assps-cyclone-ii-and-nios-ii-benefits.html, 2004 [16] W. Sawyer, Digital Design Course, Bilkent University, Available: http://www.cs.bilkent.edu.tr/~will/courses/CS223/ [17] Swift design version 3.3, Available: http://www.ti.com , June 2004 [18] Single link for all Xilinx® based tutorials, Available: http://www.eece.unm.edu/xup/xup_unm_links.htm [19] “Xilinx® prototyping platforms users guide for Virtex and Virtex-E series FPGAs,” Xilinx® Product Specification DS020, December 1999 [20] “Board Routability Guidelines with Xilinx® Fine-Pitched BGA Packages,” Xilinx® Application Note XAPP157, November 2004 [21] Xilinx® Corporate Backgrounder, Available: www.xilinx.com , July 2003 [22] Xilinx® SelectIO Ultra Technology, Available: http://www.xilinx.com/products/virtex2pro/selectioultra.htm [23] Xilinx® Press Releases, Available: http://www.xilinx.com/prs_rls/prs_rls.htm, October 2004
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[24] “XC18V00 Series In-System Programmable Configuration PROM,” Xilinx® Product Specification DS026, April 2004 [25] “Virtex Field Programmable Gate Arrays,” Xilinx® Product Specification DS003-1, April 2001 [26] “Field Programmable Gate Arrays,” Xilinx® Product Specification DS003-2, December 2002 [27] K. Morris, “Glue to Glory,” FPGA Journal, Available: www.fpgajournal.com/articles/gluetoglory.htm [28] Important Dates in Xilinx® History, Available: www.xilinx.com/company/xilinxstory/timeline.htm [29] Wikipedia English Dictionary, Available: http://www.wikipedia.org [30] Xilinx® Product and Services, iMPACT, Available: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=dr_dt_im pact , May 2005 [31] XUP-UNM Website, AFX-V1000 Microblaze Project, University of New Mexico, Craig Kief, Available: http://www.eece.unm.edu/xup/afxv1000microblaze.htm, October 2004
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Appendices All appendices are included in attached CD Appendix A. Specification Document Appendix B. Bill of Materials Appendix C. Schematics Appendix D. 4PCB Quote Appendix E. Final Gerber File Displays Appendix F. Full Production Analysis Appendix G. VHDL Test Code Appendix H. FPGA 1 User Constraint File Appendix I. FPGA 2 User Constraint File
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