RTD-based MOBILE to a circuit consisting of three or more. RTDs in series. The switching sequence in series-connected. RTDs begins also with the RTD with ...
Useful Logic Blocks Based On Clocked Series-Connected RTDs Héctor Pettenghi, María J.Avedillo, and José M. Quintana Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, SPAIN FAX: +34-955056686, E-mail: {hector, avedillo, josem,}@imse.cnm.es
Abstract
I I . OPERATING P RINCIPLE
This paper presents novel and extremely compact implementations, based of the multi-threshold threshold gate concept, for some useful building blocks for logic design. The circuits consist of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs). They exhibit the self-latching property allowing their use in nanopipelined architectures enabling higher frequency operation of systems. Index Terms: Resonant Tunneling Diodes, MOBILE, Multi-threshold Threshold gate, nanopipeline
I. I NTRODUCTION Resonant tunnelling devices are nowadays considered the most mature type of quantum-effect devices. They are already operating at room temperature and the existence of a III-V large scale integration process allows us to explore novel circuit architectures [1]. Resonant tunnelling diodes (RTDs) exhibit a negative differential resistance (NDR) region in their current-voltage characteristics which can be exploited to significantly increase the functionality implemented by a single gate in comparison to MOS and bipolar technologies. In particular, a number of self-latching Threshold Gates (TGs) based on RTDs monolithically integrated with three-terminal devices which implement complex logic functions have been fabricated and have demonstrated high speed and robust operation [1]. Circuits structures for Multi-Threshold Threshold Gates (MTTGs) [2], which are a generalization of threshold gates able to implement a broader class of functions, have been recently proposed [3], [4]. In this paper we describe several different useful building blocks for logic design which have been designed on the basis of the MTTG concept: an universal two-input block, a two-input programmable gate and a modified full-adder. We provide analysis of circuits and simulations using the HSPICE models developed within the LOCOM european project [5] for RTD and HFET devices. These models have been extensively and experimentally validated. An n-bit adder by chaining the modified full-adder cells is proposed which takes advantage of the self-latching property of the proposed building blocks.
Circuit applications of RTDs are mainly based on the MOnostable-BIstable Logic Element (MOBILE) [6]. The MOBILE (Figure 1) is a rising edge triggered current controlled gate which consists of two RTDs connected in series and driven by a switching bias voltage ( V b i a s ) . When V b i a s is low both RTDs are in the on-state (or low resistance state) and the circuit is monostable. Increasing V b i a s to an appropriate value ensures that only the device with the lowest peak current switches (quenches) from the on-state to the off-state (the high resistance state). Logic functionality is achieved by embedding an input stage which modifies the peak current of one of the RTDs since this is proportional to RTD areas. In this configuration, the peak current of the driver NDR can be modulated using the external input signal Vi n . During a critical period when Vb i a s rises, the voltage at the output node Vo u t goes to one of the two stable states (low or high), corresponding to “0” and “1” in binary logic. The value of the output depends on whether the external input signal Vi n is “1” or “0” since this determines which NDR device has the lowest current. For V b i a s = 1 the ouput node maintains its value even if the input changes. That is, this circuit structure is self-latching allowing to implement pipeline at the gate level without any area overhead associated to the addition of the latches. This nanopipelined architecture allows very high throughtoutput. A four phase clock (evaluation, hold, reset and wait) scheme is used. This means data can be processed at a frequency deterVb i a s
load RTD 2
Vo u t RTD 1 Vi n
driver
Figure 1.- MOBILE inverter
mined by the operation speed of four chained MOBILE gates. Very recently a CAD algorithm to synthesize nanopipelined networks have been proposed [7]. The circuit structures we propose extends the concept of RTD-based MOBILE to a circuit consisting of three or more RTDs in series. The switching sequence in series-connected RTDs begins also with the RTD with the smallest peak current [8]. If this peak current can be controlled by external inputs, this sequence can be varied and different functions can be obtained at the output nodes. That is, the idea is that when using three or more series connected RTDs there are two or more nodes which can be used to implement functions. III. U NIVERSAL LOGIC BLOCK Figure 2 shows the circuit structure for a two input universal logic block. Any two input function can be implemented by a single such block and inverters. Area for RTDs are depicted in terms of an unitary RTD area, Au . This unitary area is selected according to the technology and to the required design trade-offs involving speed, power and robutness againts parameter variations. Transistor are sized such that RTDs are the current limiting devices in the series connection of the RTD and the transistor. Table depicts which RTD stage quenches for each input combination and the voltage levels in each of the output nodes. It can be concluded that node y implements the EXOR function while node z implements the NAND function. Figure 2b shows simulation results for this circuit implemented using LOCOM technology and loaded with MOBILE inverters. Input waveforms are shown on the middle. Top trace depicts the clocked supply voltage and the output waveforms are shown on the bottom. Correct operation is observed for every input combination. Note the time scale. In addition, performance has been validated through Monte Carlo simulations carried out assuming gaussian distribution for the more relevant parameters including simultaneously RTD areas, peak voltages of RTDs, bias voltages, threshold voltage and area of transistors
Vbias 6Au 2Au
x1x 2
quenched RTD
z
y
00
RTD1
high
low
01
RTD2
high
high
10
RTD2
high
high
11
RTD0
low
low
4Au
y Au
Au 4.5Au
x1
x2
a
b Figure 2.- Two-input Universal Block Other RTD-based programmable gates have been reported. The design we propose here in presents advantages over each of them. It avoids the use of series connected transistors in the input stages of [9]. The programmability is digital instead of analog as it is in [10]. It is more compact than the one described in [11]. Vbias c0
c1
I V . PROGRAMABLE LOGIC GATES Figure 3 shows the circuit structure of a programmable gate with two control inputs able to implement five distinct logic functions: two-input AND (node y), two-input OR (node y), two-input EXOR (node y), two-input NAND (node z) and two input NOR (node y). The logical values for the control lines are given in the associated table. Figure 4 shows simulations results for this circuit. Control values have been specfied to sequentially implement AND, OR, NAND/EXOR, and NOR operations. Correct operation has been also validated through Monte Carlo simulations.
z
2Au
0.5
0.5
Function
c1c0
z
AND
00
0.2
NAND/ EXOR
01
OR
10
NOR
11
1.1
0.5
y 0.2
0.2
0.4
0.2 0.4
x1
x2
Figure 3.- 2-input 2-control programmable gate realizing five functions.
V I . CONCLUSIONS Extremely compact implementations of three useful building blocks for digital design with RTDs have been proposed. They are suitable for high speed applications. Existing nanopipelined structures for complex arithmetic circuits can take great advantage of the one single stage full adder proposed here in. A CKNOELEDGEMENT This effort was partially supported by the EU QUDOS project IST 2001-32358 REFERENCES Figure 4.- Waveforms for programmable gate An-1 Bn-1 A1 B1
Modified FA A0
&
B0
exor S0
Modified FA
Maj
Maj C2’
Cn-1’
exor
V
S n’ exor
S1
Sn-1
bias
x3
Vb i a s out
out
x
1
x
x x2 1
2 x3 Figure 5.- Proposed nanopipelined n-bit adder V . ADDERS
Figure 5 shows a a nanopipelined carry propagation n-bits adder. It is implemented by chaining modified full adder cells which are driven by complemented inputs. A modified full adder produces as outputs the complement of the sum and the carry of its three inputs. Unlike previously reported MOBILE based solutions for full adders, which requires a two-level network [1], this modified full adder comprises a single level of gates. This means, the proposed adder halves the number of pipeline stages in the implementation of adders and consequently its latency is also halved. Nanopipelined architectures for multipliers and divisors recently reported Eq. [7] can take advantage of these advanced proposed adders.
[1] C. Pacha et al.: “Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunnelling Devices,” IEEE Trans. on VLSI Systems, Vol. 8, no. 5, pp. 558-572, Oct. 2000. [2] D. R. Haring: “Multi-Threshold Threshold Elements,” IEEE Trans. on Electronic Computers, Vol. EC-15, No. 1, pp. 4565, February 1966. [3] M.J. Avedillo, J.M. Quintana, and J.L. Huertas, “Beyond Threshold Logic: Multi-threshold Threshold Gates,” 11th MEL-ARI/NID Workshop, Toulouse (France), Feb. 2003. [4] M.J. Avedillo, J.M: Quintana, H. Pettenghi, P.M. Kelly, and C.J. Thompson, “Multi-threshold Threshold Logic Circuit Design Using Resonant Tunneling Devices,” Electronics Letters, Vol. 39, pp. 1502-1504. [5] W. Prost et al.: EU IST Report LOCOM no. 28 844, Dec. 2000. [6] K.J. Chen, K. Maezawa and M. Yamamoto: “InP-Based High Performance Monostable-Bistable Transition Logic Elements (MOBILEs) Using Integrated Multiple-Input Resonant-Tunneling Devices,” IEEE Electron Device Letters, Vol. 17, no. 3, pp. 127-129, March 1996. [7] P. Gupta, N. K. Jha: “An Algorithm for Nano-pipelining of Circuits and Architectures for a Nanotechnology”, Proceedings DATE, 2004. [8] K.J. Chen, T. Waho, K. Maezawa and M. Yamamoto: “An Exclusive-OR Logic Circuit Based on Controlled Quenching of Series-Connected Negative Differential Resistance Devices,” IEEE Electron Device Letters, Vol. 17, no. 6, pp. 309-311, June 1996. [9] P.M. Kelly, C.J. Thompson, T.M. McGinnity, and L.P. Maguire, “Investigation of a programmable threshold logic gate array,” Proc. Int. Conf. on Electronics, Circuits, and Systems (ICECS), pp. 673-676, 2002. [10] K.J. Chen and G. Niu, “Logic synthesis and circuit modellinf of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices,” IEEE Journal of Solid State Circuits, Vol. 38, no. 2, pp. 312-318, February 2003. [11] J.M. Quintana, M.J. Avedillo and H. Pettenghi: “Programmable Logic Gate based on Resonant Tunneling Devices”, ISCAS 2004, to appear, 2004.
