Year 2 Laboratory Experiment E2 ... VLSI Design Laboratory Experiment Day 2 ...
Page 3 of 8. Figure 2. Transmission Gate Symbol. Create tgate layout: Click ...
Department of Electronics and Physical Sciences University of Surrey Year 2 Laboratory Experiment E2 Full-Custom VLSI Design of a 1-bit Shift Register Using the Cadence CAD System User Manual Laboratory experiments E1 and E2 will give you practical experience with using state-of-the-art computer aided design (CAD) software. The first laboratory session E1 will be an introduction to the Cadence CAD system using the austriamicrosystems design by designing a complementary metal-on-silicon (CMOS) inverter and CMOS NAND gate. Both designs will be fully verified and simulated to ensure design accuracy and functionality. The second laboratory session E2 will take the knowledge and experiences gained during the E1 laboratory experiment and develop them further by designing a 1-bit dynamic shift register and simulate it to demonstrate correct functionality. Table of Contents Year 2 Laboratory Experiment E2.................................................................................1 VLSI Design Laboratory Experiment Day 2 .................................................................2 Creating the Transmission Gate.................................................................................2 Creating the One-bit Dynamic Shift Register............................................................4 Create the one-bit dynamic shift register schematic ..............................................4 Create the one-bit dynamic shift register layout ....................................................5 Simulating the One-bit Dynamic Shift Register ........................................................5
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VLSI Design Laboratory Experiment Day 2 Creating the Transmission Gate The same process that was followed in creating the NAND gate will now be followed for creating the transmission gate (sometimes called pass gate or t-gate). However, as the transmission gate is a very simple design, we will not simulate it as it is clear from the layout whether you have connected it together correctly. The transmission gate forms the storage element of the 1-bit shift register. The transmission gate is different to the inverter and NAND gate as it has no direct connection to either the power rail or the ground rail, except for the substrate. Instead the pMOS gate is connected to nCLK and the nMOS gate is connected to CLK. Then the appropriate source and drain are tied together to create the input signal A, and the remaining source and drain tied together to make the output Q. Create tgate schematic: Use the Library Manager to create a transmission gate schematic view called tgate. Be careful to use the right transistor widths. Your completed schematic should be similar to that in Figure 1. Click Check and Save.
Figure 1. Transmission Gate (tgate) Schematic
Create tgate symbol: Click Design, Create Cellview, then From Cellview. Click OK. Modify design so it looks like a symbolic t-gate. Click Save. Your t-gate symbol should look something like that in Figure 2. Close Symbol.
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Figure 2. Transmission Gate Symbol
Create tgate layout: Click Tools, Design Synthesis, then Layout XL. In Virtuoso Layout Editor, click Design, then Gen From Source. Use the same dimensions and placement of the power and ground bus bars. Remember to change pin labels. Run Assura verifications. Your design should look something like that in Figure 3.
Figure 3. Transmission Gate Layout
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Creating the One-bit Dynamic Shift Register The final stage of this laboratory experiment is to bring together all the schematics, layouts, and simulations you have carried out and use the knowledge you have gained to construct a 1-bit shift register.
Create the one-bit dynamic shift register schematic
Use the Library Manager to create a one-bit dynamic shift register schematic view called onebitsr as shown in Figure 4. CLK1
CLK2
A
Q
nCLK
CLR
nCLK
Figure 4. Basic Schematic of One-bit Dynamic Shift Register
As you can see from the diagram this 1-bit shift register requires two t-gates gates, one NAND gate and 3 inverters (1 on the output, and 1 for each nCLK). Use all the elements from your library. Your completed schematic should be similar to that in Figure 5. Click Check and Save. No symbol creation is needed.
Figure 5. One-bit Dynamic Shift Register Schematic
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Create the one-bit dynamic shift register layout
Click Tools, Design Synthesis, then Layout XL. In Virtuoso Layout Editor, click Design, then Gen From Source. Make the same modifications to the input pins, output pins, vdd!, and gnd! pins in the Layout Generation Options window as before. Due to our standard cell arrangement, no vdd! or gnd! bus bars need created, only the pin area needs stretched. Complete the layout. Your finished design should look like that in Figure 6. Note that the top-level input and ouput pins will be pretty small at this point so they will be hard to find. Use Connections, Show Incomplete Nets to assist in making all the connections. Use the Path tool as before to make connections, staying on layer MET2 or higher. Watch out for overlapping metal traces. Again, don’t forget to change the pin labels to PIN(M2) when finished.
Figure 6. One-bit Dynamic Shift Register Layout
Run Assura verification tools: Run Assura DRC, LVS, and RCX using the same procedure as before. Don’t forget to change the Extraction Mode to RC.
Simulating the One-bit Dynamic Shift Register Setup simulation: In the Virtuoso Schematic Editor, click Tools, Analog Environment. Under Setup, Design, choose av_extracted. Under Setup, Stimuli, create a 3.3V global source in Global Sources as before.
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The set of other stimuli is a bit more difficult, as there are now four. Now you’ll have four inputs to configure. For CLK1, click Enabled then choose Function: Pulse. Enter the following values for the 10 fields: 3.3, , 0.0, 0.0, 3.3, 2ns, 0.1ns, 0.1ns, 1ns, 4ns. For CLK2, click Enabled then choose Function: Pulse. Enter the following values for the 10 fields: 3.3, , 0.0, 0.0, 3.3, 0.0ns, 0.1ns, 0.1ns, 1ns, 4ns. Your corresponding Setup Analog Windows should look like those in Figure 7.
Figure 7. Setup of CLK1 and CLK2 Stimuli
Now, A and CLR must be defined. For A, click Enabled then choose Function: pwl (piece-wise linear). Starting with Number of pairs of points, enter the following values for the 15 fields: 7, 0.0ns, 0.0, 1.5ns, 0.0, 1.6ns, 3.3, 6ns, 3.3, 6.1ns, 0.0, 8ns, 0.0, 8.1ns, 3.3. For CLR, click Enabled then choose Function: pwl. Starting with Number of pairs of points, enter the following values for the 11 fields: 5, 0.0ns, 3.3, 11ns, 3.3, 11.1ns, 0.0, 17.5ns, 0.0, 17.6ns, 3.3. Your corresponding Setup Analog Windows should look like those in Figure 8.
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Figure 8. Setup of A and CLR Simuli
Setup Analysis: Click Setup, then Choose Analyses button. Ensure tran is selected, enter 0.000000025 (which is 25ns, seven leading zeros) and enable Enabled at the bottom of the window. Click OK. Setup Outputs: Click Outputs, To Be Plotted, then Select on Schematic. Click inputs CLK1, CLK2, A, CLR then output Q. Run Simulation: Click on the Netlist and Run button, which looks like a green traffic light. You should get a simulation output similar to that in Figure 9. Click on the Strip Chart Mode to see the inputs and output separately, to make it easier to analyze.
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Figure 9. One-bit Shift Register Simulation Output
If your results do not match these you have made a mistake somewhere and need to go back and re-check your work. Most likely you have made an error in the simulation setup of the stimuli, so re-check that first before re-examining your design. Upon achieving the correct simulation output, you have successfully completed the two laboratory experiments by designing a full custom 1-bit dynamic. If you’d like, make any graph labels and save the simulation session. Then close all of your other windows. The last window you should close is icfb.
The E1 & E2 lab experiments are developed by: David Barnhart and Dr Tanya Vladimirova VLSI Design and Embedded Systems Research Group Surrey Space Centre December 2006
Acknowledgements: • •
Alistair Young developed the 1st version of the labs as part of his final year project in May 2004. Thanks are due to Georgi Kuzmanov for help with the installation, troubleshooting and maintenance of the Cadence CAD software
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