The Design of Integrated 3-GHz to 11-GHz CMOS Transmitter for Full-Band Ultra-Wideband (UWB) Applications Wen-Chieh Wang, Chang-Ping Liao, Yi-Kai Lo, Zue-Der Huang, Fadi R. Shahroury and Chung-Yu Wu Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan Email:
[email protected],
[email protected] Abstract—The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-µm CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature upconversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14-band operation for UWB applications. The transmitter has an average conversion gain of 12.8 dB with the gain ripple of around ±1.4 dB among the whole frequency band. The average input 1-dB compression point (IP– 1dB) of the 14 bands is –12.2 dBm and the average output 1-dB compression point (OP–1dB) of the 14 bands is –0.4 dBm. The transmitter dissipates the power of 53.1 mW from the supply voltage of 1.2 V and occupies the chip area of 1930×1635 μm2. This chip is designed in 0.13-µm 1P8M CMOS technology and under fabrication.
I. INTRODUCTION Recently, the fast growth in the field of RF and wireless applications has attracted a great deal of research effort on designing high performance and low cost RF integrated circuits and systems using the advanced CMOS technologies. To achieve very high data rates over short range distances, UWB technologies are extensively investigated. Fig. 1 shows the band structure for Multi-band-OFDM (MB-OFDM) UWB applications. There are 14 bands within the frequency range from 3168 MHz to 10560 MHz. The center frequency of each band is given by m×(264 MHz) for m = 13,Ξ, 39. Besides, each band is composed of 128 sub-channels with the channel bandwidth of 4.125 MHz. According to the FCC regulation, the transmitted power spectra density (PSD) should not exceed –41 dBm/MHz. The required output power and OP–1dB of the transmitter is –10 dBm and –6 dBm, respectively [1]. So far, many development of MB-OFDM UWB transceiver operated over 3.1 GHz to 9.2 GHz has been proposed [1]–[3]. Nevertheless, the demand for higher frequency bands is still appealing because operating in the higher frequency bands can alleviate the interference problems in massive wireless applications. Consequently, a 14-band
Group I
Group III
Group IV
Group V
2
3
4
5
6
7
8
9
10
11
12
13
14
3432
3960
4488
5016
5544
6072
6600
7128
7656
8184
8712
9240
9768
10296
(MHz)
Figure 1. The band structure of the MB-OFDM UWB system.
I/Q Quadrature Up-Conversion Mixer
INIF
XFMRRF +
−
INCLK
poly-phase filter
XFMRIF I
+
Q
−
3-11 GHz LO
XFMRCLK +
6-22 GHz
Q
I
OUTRF
Balanced RF Pre-Amplifier
Divide-by-2 −
14-Band UWB Transmitter
Figure 2. The architecture of the proposed direct-conversion full-band UWB transmitter.
MB-OFDM UWB transmitter is proposed and designed in this paper. The transmitter can be operated within the frequency between 3 GHz and 11 GHz. This UWB transmitter with fullband configuration also has simple structure that smaller chip area can be achieved. In section II, operational principles and circuit realization are presented. The results of simulation are reported in Section III to verify the performances of the proposed UWB transmitter. Finally, the conclusion is given in Section IV. II. OPERATIONAL PRINCIPLES AND CIRCUIT REALIZATION Fig. 2 shows the architecture of the proposed directconversion full-band UWB transmitter. The circuits are designed to cover the operating frequency range from 3 GHz to 11 GHz. The proposed full-band transmitter consists of a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a poly-phase filter. The quadrature LO and IF signals are required so that the I/Q mixer performs the single-sideband (SSB) up-conversion. The frequency of the differential input clock signal from 6 GHz to 22 GHz is
This work was supported by the National Science Council (NSC), Taiwan, under the Grant NSC-96-2221-E-009-179.
978-1-4244-1684-4/08/$25.00 ©2008 IEEE
Group II
1
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V DD L1
L2
L3
L4
R1
R2
R3
R4
LOIP
LO IM
LOQM
LOQp
M1,2,5,6
7.2 / 0.12
M3,4,7,8 M9,11
5.4 / 0.12 16.2 / 0.12
M10,12
5.4 / 0.12
L1-L4
4.14 nH
R1-R4
603 Ω
R B1-RB2 C B1-CB2
50 Ω 1.1 pF
L10 C1 C2
5.096 nH 790 fF 1.85 pF
RB7 CPAD1 VB4
20.6 kΩ 43 fF 0.6 V
VDD L9
L7
VDD
R7
VB4 M24
RB7 C1
M22
C2
M21
86.4/ 0.12
M22 M23 M24 L7
115.2 / 0.12 27 / 0.12 21.6 / 0.12 2.37 nH
R7
55 Ω
L8 L9
0.557 nH 1.33 nH
M23
CPAD1
OUT
IN L10 M1 R B2
VB1 RB1
M3
M2
M4
M5
M7
M6
INP
M8
CB2
L8
INP M9
INM
M10
M 11
IN M
M12
Single-Ended RF Amplifier
CB1
IN
Figure 3. Circuit diagram of the CML 2:1 frequency divider with inductance peaking technique.
L5
L6
R5
R6
MIXOUTP
MIXOUTM
OM
OP VB2 RB6
RB5
V B4
CB6
VDD
LOIP M15
LOIM
M20 M16
N1
LOM
CB5
IF M
CB4
M17
IFP
RB3
28.8 / 0.12 96 / 0.36
L5-L6 R5-R6
4.16 nH 100 Ω
RB3-RB6 CB3-CB6
20.6 kΩ 1.1 pF
VB2 VB3 VB4
0.68 V 0.85 V 0.41 V
LOP
LOQP
LOM
LOQM
IF M
IF QM
IFP
IFQP
M14
RB4
VB3 I-Path Mixer
OUTM
OUT
Due to the parasitic capacitors at the drains of M1–M8, the impedance at these nodes is reduced with the increasing of operating frequency. Because the impedance of the inductor increases with the increase of frequency, the inductance peaking configuration is adopted as the load of the frequency divider to compensate the influence of parasitic capacitors [4]. The load resistors R1–R4 are added to increase the low frequency gain. However, the values of R1–R4 are limited by the voltage headroom. In this frequency divider, L1–L4 are chosen as 4.14 nH and R1–R4 are chosen as 603 ȍ. The four outputs of the frequency divider behave as quadrature LO signals for quadrature up-conversion mixer that is to be discussed in the following.
N2
M13
CB3
28.8 / 0.12
M18
IFIM IF IP
OM
M13-M14 M15-M18 M19-M20
VB4
VDD
M19
OP
Single-Ended RF Amplifier + Output Buffer
Output Buffer
Figure 5. Circuit diagram of balanced RF amplifier.
VDD
LOP
OUTP
M21
Q-Path Mixer
Figure 4. Circuit diagram of the quadrature up-conversion mixer.
divided by the 2:1 frequency divider to obtain the quadrature LO signals from 3 GHz to 11 GHz. Besides, the quadrature IF input signals are generated through the 90° phase shifter that is realized by poly-phase filter. The differential RF signals from the output of the quadrature mixer are amplified through a balanced RF amplifier to drive the output load. The off-chip transformers XFMRIF and XFMRCLK are used to perform single ended to differential transformation for the IF signal and the clock signal, respectively. Meanwhile, the off-chip transformer XFMRRF is used to deal with differential to single ended transformation for the RF output signal. Detailed operational principles of the 2:1 frequency divider, quadrature up-conversion mixer, balanced RF amplifier, and poly-phase filter are described in the following subsections. A. 2:1 Frequency Divider The circuit diagram of the current-mode logic (CML) 2:1 frequency divider is shown in Fig. 3. The frequency divider is based on the master-slave D-type flip-flop in which the inverted outputs of the slave stage are connected to the inputs of the master stage. M1–M4 and M9–M10 form the master stage whereas M5–M8 and M11–M12 form the slave stage. CB1 and CB2 are the input ac coupling capacitors. M9–M11 are biased through the resistors RB1–RB2. The value of RB1 and RB2 are chosen as 50 ȍ so that the simple input matching can be realized for high frequency input signals.
B. Quadrature Up-Conversion Mixer Fig. 4 illustrates the circuit diagram of the quadrature upconversion mixer including I–path and Q–path Mixers. With the quadrature signal operation, the single sideband (SSB) mixer is realized. Based on the operational principles of Gilbert mixers [5], the double-balanced active mixer in each path consists of a transconductance or driver stage, which is a differential pair, and two switching pairs that are driven by the strong LO signals. M13–M14 are biased in the saturation region and performed as the differential input transconductance stage which is used to convert the IF voltage signal to current signal. The converted current signals are fed to the switching pairs. The switching pairs are composed of M15–M18 which are biased in the triode region. The current signals are switched between the two outputs alternatively according to the phase of the LO signals. The commutation of the IF signal in accordance to the LO signal realize the function of mixer. With the advantage of differential configuration, the leakage of LO and IF can be reduced in this double balanced mixer. M19–M20 work as current source and inject currents to the nodes N1–N2. With the current bleeding technique realized by M19–M20, the conversion gain can be enhanced. CB3–CB6 are ac coupling capacitors, and RB3–RB6 are large resistors to bias the transistors. The technique of inductor peaking is also applied to the load of the SSB mixer to extend the operation frequency further. In this design, L5–L6 are chosen as 4.16 nH and R5–R6 are chosen as 100 ȍ. The mixer of each path consumes 8.1 mA from 1.2-V power supply.
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RP1
RP2
RP3 IF0
CP1 RP1 IFP
RP2
CP3 RP3 IF90
+
−
CP2
CP1 RP1
CP2 RP2
CP3 RP3
IFM
IF180 CP1 RP1
CP2 RP2
CP3 RP3 IF270
CP1
CP2
CP3
RP1
5k ohms
RP2
5k ohms
RP3
5k ohms
CP1
440 fF
CP2
240 fF
CP3
120 fF
Figure 6. 3-stage cascaded passive poly-phase filter. Figure 7. Layout diagram of the 14-band UWB transmitter.
C. Balanced RF Amplifier Fig. 5 shows the circuit diagram of balanced RF amplifier which is formed by two single-ended RF amplifiers. M21–M22 are biased in the saturation region and operated as the common source amplifiers with source degenerative inductors L8–L9. The technique of current-reuse is applied to M21 and M22 so that larger transconductance of the input stage can be achieved without additional power dissipations. C1, C2 and C10 are the inter-stage matching network. Following the input stage is the common-gate amplifier formed by M23. The technique of inductance peaking realized by L7 and R7 is also applied here to extend the range of operating frequency. M24 is designed as a common-drain amplifier to drives the output load of 50 ȍ for measurement. One single-ended RF amplifier and output buffer drains 12.6 mA from the supply voltage of 1.2 V. The total power consumptions of the balanced RF amplifier with output buffer are about 30.2 mW. D. Passive Poly-Phase Filter Shown in Fig. 6 is the 3-stage cascaded passive poly-phase filter [6]. For testing purpose, this passive poly-phase filter is designed to provide four quadrature IF signals for the quadrature up-conversion mixer. The value of RP1, RP2, and RP3 are 5k ȍ. The value of CP1, CP2, and CP3 are 440 fF, 240 fF and 120 fF, respectively. The three poles of the poly-phase filter can be found at 72 MHz, 132 MHz, and 265 MHz. The image rejection ratio (IRR) can be used to verify the accuracy of the quadrature signals. The higher the IRR, the more accurate quadrature signals can be obtained [7]. III.
SIMULATION RESULTS
The integrated CMOS transmitter for full-band UWB applications is designed in 0.13-µm 1P8M CMOS technology with the supply voltage of 1.2 V. The layout diagram of the proposed UWB transmitter is shown in Fig. 7. The circuit occupies the chip area of 1930×1635 μm2 including testing pads. The simulated sensitivity curve of the frequency divider is shown in Fig. 8 which reveals that the frequency divider can deal with the frequency of input clock signal from 1 GHz to 22 GHz. With the LO input power of 0 dBm, the quadrature up-conversion mixer provides the average gain of 1.1 dB with
Figure 8. Sensitivity curve of the 2:1 frequency divider.
the gain variation of ̈́1 dB from 3 GHz to 11 GHz. Besides, the balanced RF amplifier provides the average gain of 12.4 dB with gain variation of ̈́2 dB over the frequency from 3 GHz to 11 GHz. The 3-stage cascaded passive poly-phase filter can achieve the IRR larger than 38 dB from 60 MHz to 290 MHz with about 7-dB signal loss. The 3-stage cascaded passive poly-phase filter consumes no power. The linearity performance is verified through Harmonic Balance (HB) analysis. As depicted in Fig. 9, after the compensation of 7-dB losses from the poly-phase filter and input transformer XFMRIF, the UWB transmitter of the 7th band exhibits an IP–1dB of –11 dBm and OP–1dB of 0.7 dBm where the frequency of LO is at 6.6 GHz. The frequency of input clock signal is 13.2 GHz with the signal power of 6.5 dBm. Shown in Fig. 10 is the conversion gain versus frequency of the integrated UWB transmitter, this UWB transmitter exhibits the average conversion gain of 12.8 dB over the frequency from 3 GHz to 11 GHz with the gain variation of ±1.4 dB. This figure also shows that the performance of OP–1dB over the whole 14 bands where the signal power of input clock signal is 6.5 dBm. However, for the 14th band, the supply voltage of divider is slightly increased from 1.2 V to 1.3 V so that the divider can work well and provide sufficient LO signal magnitude to drive the
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TABLE I.
Technology
PERFORMANCE SUMMARIES AND PRIVIOUSLY PUBLISHED WORKS This work
[2]
[3]
0.13 μm 1P8M CMOS
90nm CMOS
0.13 mm CMOS
1.2 V
1.1 V
1.5 V
Bandwidth
3 GHz ~ 11 GHz
3.1 GHz ~ 9.5 GHz
3 GHz ~ 5 GHz
Average Gain
12.8 dB
-
-
Gain Ripple
̈́ʳ1.4 dB
ˀ
ˀ
Average IP1dB
-12.2 dBm
-
-
Average OP1dB
-0.4 dBm
-2.8 dBm *
5 dBm
Power
Supply Voltage
2.9 mA (3.5 mW) 16.2 mA (19.4 mW) 25.2 mA (30.2 mW) 0 53.1 mW
-
-
131 mW **
97.5 mW
Chip Area
1930 ͪ 1635 μm2
-
-
Note
14 Bands
12 Bands
3 Bands
Divider Mixer RF Amplifier Poly-Phase Filter
Total
* −2.8 dBm is estimated from its OIP3 of 7.2 dBm
** including synthesizer as well in the transmit mode
th
Figure 9. The linearity performance of the 7 band of the UWB transmitter.
IV. CONCLUSION The integrated CMOS transmitter for 14-band MB-OFDM UWB applications has been proposed and designed. The technique of inductance peaking is adopted to widen the operating frequency band so that 14 bands of UWB systems can be covered at the same time. The average conversion gain is around 12.8 dB with the gain ripple of ±1.4 dB. The average OP–1dB is about –0.4 dBm that satisfies the linearity requirement of the UWB transmitter. The experimental chip has been designed and under fabrication. ACKNOWLEDGMENT The authors would like to thank the United Microelectronics Corporation (UMC) for the fabrication of testing chip. The authors would also like to thank Ansoft Taiwan for the support of tools HFSS and Designer/Nexxim. REFERENCES
Figure 10. The conversion gain and OP–1dB of the 14-band UWB transmitter.
[1]
quadrature up-conversion mixer. From these simulation results, this transmitter satisfies the required linearity performance and can cover the 14-band operations. From the supply voltage of 1.2 V, the power dissipations of the frequency divider, quadrature up-conversion mixer and balanced RF amplifier are 3.5 mW, 19.4 mW and 30.2 mW, respectively. The total power dissipation is about 53.1 mW. In Table I, the performance of the designed transmitter is summarized and compared with the performance of the previously published works. The power dissipation of this work is much smaller than [2] [3]. This is the first integrated UWB transmitter covering 14 bands. The linearity performance of this work is comparable to other works [2] [3] and meets the requirement of UWB applications [1].
[2]
[3]
[4] [5]
[6]
[7]
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B. Razavi, et al., “A UWB CMOS transceiver,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2555–2562, Dec. 2005. A. Tanaka, H. Okada, H. Kodma, and H. Ishikawa, “A 1.1V 3.1-to9.5GHz MB-OFDM UWB Transceiver in 90nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 398–407. C. Sandner, et al., “A WiMedia/MBOA-Compliant CMOS transceiver for UWB,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2787– 2794, Dec. 2006. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, New York: Cambridge Univ. Press, 1998. B. Gilbert, “A precise four quadrant multiplier with subnanosecond response,” IEEE J. Solid-State Circuits, vol. SC–3, pp. 365–373, Dec. 1968. F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 873–887, June 2001. C.-Y. Chou, and C.-Y. Wu, “The design of wideband and low-power CMOS active polyphase filter and its application in RF doublequadrature receiver,” IEEE Trans. CAS–I: Regular Papers, vol. 52, no. 5, pp. 825–833, May 2005.
