Vector Control of Single Phase Induction Motor

Vector Control of Single Phase Induction Motor Project Report

This project report is submitted in partial fulfillment of the requirements for the award of Master of Technology in Electronics Design and Technology

Submitted by Lalit Patnaik

Under the guidance of Dr. L Umanand Dr. NVC Rao

CENTRE FOR ELECTRONICS DESIGN AND TECHNOLOGY INDIAN INSTITUTE OF SCIENCE BANGALORE - 560012 June 9, 2009

Acknowledgement I wish to express my sincere gratitude to my guides, Dr. L. Umanand and Dr. N. V. C. Rao, for giving me the opportunity to work on such an intruiguing project. I’m especially indebted to Dr. Umanand for the able guidance, enlightening suggestions, thought-provoking ideas and, above all, the freedom he offered during the course of the project. I would also like to thank all the faculty of CEDT for the queries and suggestions raised during various phases of the project. Their inputs helped in adding new dimensions to my thought process. I sincerely appreciate the contribution of all my lab-mates - especially Rachit, Rijil, Das, Siva, Chintan, Tanmoy, Sudhin, Prasanna and Tanmoy - for all the help and support. If there were times when I got stuck, it was mostly a discussion with one among them that helped me move on. I’m grateful to Chipkraft Technologies and PC Process Pvt. Ltd for fabricating my PCBs in time. I thank Farnell Electronics for the speedy delivery of all my components. I thank the CEDT workshop staff and CEDT office staff for their help whenever called upon. Thanks are also due to all my classmates for their handy inputs and also for creating an environment conducive for learning. I have been very lucky indeed to have always had the full encouragement and support of my parents in all my endeavours. My heartiest gratitude and love to them.

Lalit Patnaik

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Contents 1 Introduction

1

2 System Description

3

I

2.1

Objective and Block Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

2.2

EMI Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.3

Front-End Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.4

Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

2.5

Micro-controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

2.6

Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

Study Phase

6

3 Market Survey

7

3.1

Comparision of Microcontroller/DSP Chips . . . . . . . . . . . . . . . . . . . . .

7

3.2

Comparision of Intelligent Power Modules . . . . . . . . . . . . . . . . . . . . . .

8

3.3

Comparision of UPFC Controller Chips . . . . . . . . . . . . . . . . . . . . . . .

8

4 Literature Survey

9

4.1

AC Induction Motor Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

Equivalent Circuit of Single Phase Induction Motor . . . . . . . . . . . . . . . . . 12

4.3

V/f Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4

Vector Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Wish Specifications

9

16

5.1

Wish Specifications for the Product . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2

Tentative Specifications for the Internal Blocks . . . . . . . . . . . . . . . . . . . 17 5.2.1

Motor Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 iii

CONTENTS

CONTENTS

5.2.2

Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2.3

Front-end Converter Specifications . . . . . . . . . . . . . . . . . . . . . . 18

5.2.4

EMI Filter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.5

DC/DC Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.6

Micro-controller/DSP Specifications . . . . . . . . . . . . . . . . . . . . . 19

II

Design Phase

20

6 Target Specifications

21

6.1

Product Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2

Induction Motor (off-the-shelf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3

Front-End Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.4

Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.5

Software (Motor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 Design of Front-End Converter

25

7.1

Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2

Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.1

Design of Boost UPFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2.2

Design of Boost Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.3

Design of DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2.4

Design of NTC Thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Design of Inverter

36

8.1

Circuit Schematic and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2

Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Design of Sensing Circuits

39

9.1

Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.2

Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10 Design of Micro-controller Circuit

42

11 Software Design

44

11.1 Open Loop Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2 Closed Loop Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Lalit Patnaik

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CONTENTS

CONTENTS

12 Industrial Design

47

III

48

Engineering Phase

13 CiPoS Board

49

13.1 PCB Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3 Connector Details 13.4 Bill of Materials

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

13.5 Corrections in CiPoS board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.6 PCB Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14 dsPIC Board

60

14.1 PCB Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 14.3 Connector Details 14.4 Bill of Materials

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14.5 Corrections in dsPIC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.6 PCB Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 15 Software

85

15.1 Tools used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 15.2 Open Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 15.2.1 Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 15.2.2 Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 16 System Wiring

96

17 Experimental Results

98

A UPFC Design M-code

99

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List of Figures 2.1

Block schematic of the complete system . . . . . . . . . . . . . . . . . . . . . . .

3

4.1

A typical stator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2

A typical squirrel cage rotor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3

Torque-speed curves of different types of single phase induction motors . . . . . . 11

4.4

Equivalent circuit of single phase induction motor . . . . . . . . . . . . . . . . . . 12

4.5

Equivalent circuit of single phase induction motor with stationary rotor . . . . . 12

4.6

Torque-speed and current-speed characteristics of a single phase induction motor

4.7

Voltage and torque versus frequency with V/f control

4.8

Typical V/f profile for a variable speed ACIM application . . . . . . . . . . . . . 14

4.9

Torque profiles for variable frequency operation . . . . . . . . . . . . . . . . . . . 15

7.1

Circuit schematic of the front-end converter . . . . . . . . . . . . . . . . . . . . . 26

7.2

Circuit schematic for boost UPFC and its controller . . . . . . . . . . . . . . . . 27

7.3

Ferrite EE-core dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1

Circuit schematic showing the connection of the inverter and the motor . . . . . 36

8.2

Circuit schematic for inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1

Circuit schematic for voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2

Circuit schematic for current sensing . . . . . . . . . . . . . . . . . . . . . . . . . 41

13

. . . . . . . . . . . . . . . 13

11.1 Open-loop control strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2 Closed-loop control strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.3 PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.1 Industrial design for the product . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 OrCAD schematic for CiPoS board . . . . . . . . . . . . . . . . . . . . . . . . . . 50 vi

LIST OF FIGURES

LIST OF FIGURES

13.2 OrCAD Layout for CiPoS board: TOP routing layer . . . . . . . . . . . . . . . . 51 13.3 OrCAD Layout for CiPoS board: BOTTOM routing layer . . . . . . . . . . . . . 51 13.4 CiPoS board: SST layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.5 CiPoS board: SSB layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.6 CiPoS board: DRD layer with drill chart . . . . . . . . . . . . . . . . . . . . . . . 53 13.7 CiPoS board: SMT layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.8 CiPoS board: SMB layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.9 Photograph of the asssembled CiPoS board with heat sink . . . . . . . . . . . . . 55 13.10CiPoS board: Input and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.1 OrCAD schematic for dsPIC board: page-1 . . . . . . . . . . . . . . . . . . . . . 62 14.2 OrCAD schematic for dsPIC board: page-2 . . . . . . . . . . . . . . . . . . . . . 63 14.3 OrCAD schematic for dsPIC board: page-3 . . . . . . . . . . . . . . . . . . . . . 64 14.4 OrCAD schematic for dsPIC board: page-4 . . . . . . . . . . . . . . . . . . . . . 65 14.5 OrCAD Layout for dsPIC board: TOP routing layer . . . . . . . . . . . . . . . . 66 14.6 OrCAD Layout for dsPIC board: BOTTOM routing layer . . . . . . . . . . . . . 67 14.7 OrCAD Layout for dsPIC board: GND plane layer . . . . . . . . . . . . . . . . . 68 14.8 OrCAD Layout for dsPIC board: POWER plane layer . . . . . . . . . . . . . . . 69 14.9 dsPIC board: SST layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.10dsPIC board: SSB layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.11dsPIC board: DRD layer with drill chart . . . . . . . . . . . . . . . . . . . . . . . 72 14.12dsPIC board: SMT layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.13dsPIC board: SMB layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.14Photograph of the asssembled dsPIC board . . . . . . . . . . . . . . . . . . . . . 75 14.156-wire cable for RJ-11 socket: ICD2 Debugging/Programming Interface . . . . . 78 16.1 System Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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List of Tables 3.1

Comparision of Microcontroller/DSP Chips . . . . . . . . . . . . . . . . . . . . .

7

3.2

Comparision of Intelligent Power Modules . . . . . . . . . . . . . . . . . . . . . .

8

3.3

Comparision of UPFC Controller Chips . . . . . . . . . . . . . . . . . . . . . . .

8

5.1

Motor specifications (given) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2

Inverter specifications (tentative) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3

Front-end converter specifications (tentative) . . . . . . . . . . . . . . . . . . . . 18

5.4

EMI filter specifications (tentative) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5

DC/DC converter specifications (tentative) . . . . . . . . . . . . . . . . . . . . . 18

5.6

Micro-controller/DSP specifications (tentative) . . . . . . . . . . . . . . . . . . . 19

6.1

Motor Specifications*: Name Plate Details . . . . . . . . . . . . . . . . . . . . . . 22

6.2

Front-End Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.3

Inverter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.4

Software Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13.1 7-pin Relimate Connector: PWM signals and Fault Output . . . . . . . . . . . . 56 13.2 3-pin Combicon Connector: DC supplies to control part of CiPoS board . . . . . 57 13.3 Bill of Materials for CiPoS Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.1 dsPIC Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.2 J1: 6-pin RJ-11 connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.3 J2: 6-pin Bergstrip connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.4 J3: 2-pin Combicon connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.5 J4: 7-pin Relimate connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6 J9: 3-pin Combicon connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.7 J10: 3-pin Combicon connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 viii

LIST OF TABLES

LIST OF TABLES

14.8 J15: 2-pin Relimate connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 14.9 Bill of Materials for dsPIC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Chapter 1

Introduction The world’s energy needs are increasing while the reserves of the primary energy resource, the fossil fuels, are dwindling at an alarming rate. Renewable energy and energy efficiency are the twin solutions to this problem. While renewable energy has received some attention, making homes, vehicles, and businesses more energy efficient is a largely untapped solution to addressing global warming, energy security, and fossil fuel depletion.

Electric motors consume more than 50% of the world’s electrical energy [1], which makes motor efficiency very important from the point of view of energy efficiency. Many home appliances such as air conditioners, refrigerators, washing machines, celing fans etc. use induction motors. The traditional appliance controller in an air conditioner or refrigerator is a simple circuit, which switches the compressor on and off to maintain the temperature within the target range, much like an on/off controller with hysteresis. When the system starts operation, the compressor runs continuously but once temperature reaches the target range, it runs at a low duty cycle. When the system operates with a low on/off duty cycle, the compressor runs for a large fraction of time away from its most efficient operating point. Moving from the conventional fixed-speed motors to variable-speed operation could save as much as 30 percent of energy consumed [2]. In the case of ceiling fans, for lower than full speed operation, speed setting is generally done by increasing the slip speed of the induction motor which is a very inefficient method. Here as well, the use of a variable voltage variable frequency motor drive would be a much more efficient solution.

With stringent government regulations and consumers preferring “greener” appliances, the mantra of appliance makers is to enhance efficiency and reduce the audible noise of their products. Thus, there is an urgent need for efficient motor-control techniques in appliances using motors. Deploying advanced motor-control techniques, such as a Vector Control, also called Field-Oriented Control (FOC), meets this goal. Utilizing vector control, the motor-controller adjusts motor speed and torque for the most efficient operation possible. It controls the amplitude, frequency and phase of the stator voltages in such a way as to keep the stator and rotor magnetic fields at 90 degrees to each other. Thus the flux and torque producing components of the stator current are decoupled leading to excellent control dynamics comparable to that of a separately excited DC motor. The torque pulsations are also reduced leading to lesser vibration and lower audible noise. 1

Chapter 1. Introduction Vector Control - if at all employed - has largely been used with three-phase motors in industrial applications. On the other hand, there are probably more single phase induction motors in use today than the total of all the other types of motors put together. Almost all the home appliance applications use single phase induction motors due to lower cost and non-availability of three-phase power outlets in most user premises. The present project intends to extend the use of vector control to single phase induction motors (used as two-phase motor) with the objective of getting better motor efficiency and control dynamics. This in turn would translate into a better efficiency of the appliance in which the motor is being used.

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Chapter 2

System Description 2.1

Objective and Block Schematic

Single phase induction motors commonly employ a start and/or run capacitor to get good starting torque and/or good running performance. The objective of the project is to retrofit the start and run capacitor with the proposed product so as to get higher efficiency and better performance. The performance indices are control dynamics (rise time, settling time, and peak overshoot), current waveshape and audible noise of the motor. The major challenge here lay in making the size of the product small enough to be mounted on the motor itself. Such a set-up would lead to the concept of a smart motor that just needs a single phase power input and a speed reference control input which it follows very closely. Figure 2.1 shows the block schematic of the proposed vector controlled appliance motor-control system.

Figure 2.1: Block schematic of the complete system

3

2.2. EMI Filter

2.2

Chapter 2. System Description

EMI Filter

Depending on the type and rating of the appliance, an off-the-shelf EMI filter can be used in order to limit the conducted noise emission within the EMC regulations. The insertion loss for the EMI filter is dictated by the difference between the permitted conducted emissions for household appliances (60dBuV as per CISPR14/EN55014/FCC15) and the actual conducted emission of the product.

2.3

Front-End Converter

The front-end converter consists of three parts: 1. Diode Bridge Rectifier 2. Boost Unity Power Factor Converter (UPFC) 3. DC-DC Converter The diode bridge rectifies the mains voltage. A boost unity power factor converter (UPFC) is used on the output side of the diode bridge in order to draw a unity power factor current from the mains. The switch (MOSFET) in the UPFC is controlled by an off-the-shelf UPFC controller chip. The ripple in the DC link is filtered by a DC link bulk capacitor. On the same core as the inductor of the boost UPFC, a few other windings are wound so as to get isolated 3.3V, ±5V and 15V supplies by tranformer action. These shall be used to power the microcontroller, the D/A converter (included for system debugging purpose), the current and voltage sensors and associated signal conditioning circuits, the UPFC controller and IGBT gate drive circuits. Using such auxiliary windings to derive the dc supplies is a much simpler, cheaper and elegant solution as compared to a multiple-output DC-DC converter taking the high voltage DC link as the input. Also, the efficiency of a single converter is always better than two cascaded converters. But the drawback is that if the boost converter stops switching action due to certain fault conditions, all the control circuits will experience a power outage.

2.4

Inverter

The DC link voltage obtained at the output of the front-end converter is used by the inverter bridge to obtain a Variable-Voltage-and-Variable-Frequency (VVVF) power supply that drives the motor. A bleeder resistor, also known as a brake chopper, is connected across the dc link capacitor so as to ensure that the DC link voltage does not rise to dangerous levels. The bleeder resistor may be switched in or out of the circuit depending on the sensed dc bus voltage magnitude. A CiPoS Integrated Power Module (IPM) is used to implement the inverter bridge. Use of IPMs eases design and delivers additional benefits such as reduced component count, reduced size and increased reliability as opposed to using discrete switches [2]. Lalit Patnaik

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Chapter 2. System Description

2.5

2.5. Micro-controller

Micro-controller

A dsPIC micro-controller takes care of the control and diagnostics. It takes the feedback signals (stator currents, dc bus voltage, fault singal etc.) and implements the vector control algorithm. The speed reference signal required by the vector control algorithm is assumed to be available as the output of an appliance control algorithm. Programming the microcontroller and debugging of the software code is done through Microchip’s proprietary In-Circuit Debugger, MPLAB ICD-2.

2.6

Algorithm

The details of the control algorithm are discussed in Chapter-11. The algorithm is implemented on the micro-controller wherein separated PWM signals are sine-wave modulated using either sine-triangle modulation (SPWM) or space vector modulation (SVPWM) and applied to the windings of the motor. Center-aligned PWM is used in order to have reduced EMI being emitted by the product [3]. The control algorithm can be run either in open-loop or in closed loop. In open-loop operation, the required voltage space vector position (γ) is calculated by integrating the speed reference. In closed-loop operation, knowledge of the rotor flux position is required to do the domain transformations (d-q domain to α-β doamin and vice-versa). Also, the stator currents are sensed and fed back to PI controllers for generating proper voltage references. Single phase motors are not usually mounted with an optical encoder. Hence, for closed loop operation, there is no direct rotor speed feedback available and the closed-loop vector control algorithm will need to be speed-sensorless. Rotor speed and rotor flux position (ρ) should be estimated using the knowledge of the stator voltages, stator currents and the mathematical model of the motor. The speed reference for the vector control scheme comes from an appliance control algorithm. This algorithm, that is a part of an outer loop, would generally be a simple state-machine that is appliance-specific and can be implemented on the same micro-controller that runs the vector control algorithm. E.g. for the simple case of a ceiling fan, the speed reference is directly available from the fan regulator input from the user.

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Part I

Study Phase

6

Chapter 3

Market Survey 3.1

Comparision of Microcontroller/DSP Chips Generation CPU Peak MMACS/MIPS Frequency(MHz) RAM OTP ROM Flash PWM CAP/QEP ADC ADC Conversion Time Timers Package

Unit Cost

TMS320F281x 1 C28xx 150 MMACS 150 36 KB 2 KB 256 KB 16-Ch 6/2 1 16-Ch 12-Bit 80 ns 3 32-Bit GP,1 WD 179-Ball BGA 176-Pin LQFP 128-Pin LQFP $15.97

dsPIC33FJXXXMCXXX dsPIC33F 40MIPS 40 30KB(includes 2KB of DMA RAM) N/A 256KB 8 Std PWM + 8 motor control PWM 8/0 2 24-ch 12-bit 500ksps @ 12bit / 1.1Msps @ 10bit 9 16-bit timers/ 4 32-bit timers 100-Pin TQFP 80-Pin TQFP 64-Pin TQFP $9.10

Table 3.1: Comparision of Microcontroller/DSP Chips

7

3.2. Comparision of Intelligent Power Modules

3.2

Chapter 3. Market Survey

Comparision of Intelligent Power Modules

Storage temperature range, C Max. blocking voltage of IGBT, V DC output current of IGBT, A Repetitive peak collector current of IGBT, A Max. switching frequency, kHz Power dissipation per IGBT, W

CiPoS IKCS12F60AA -40 to 125 600 12 18 20 35

Mitsubishi PM10CSJ060 -40 to 125 600 10 20 20 39

Table 3.2: Comparision of Intelligent Power Modules

3.3

Comparision of UPFC Controller Chips

UVLO Thresholds On/Off(V) Operating Supply(Max)(V) Startup Current(mA) Operating Supply Current(mA) Duty Cycle(Max)(%) Practical Operating Frequency(Max)(MHz) Pin/Package

UC3854 16/10 35 0.25 10 95 0.115 DIP16,SOIC16

UC3853 11.5/9.5 40 0.25 10 95 0.115 DIP8,SOIC8

Table 3.3: Comparision of UPFC Controller Chips

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Chapter 4

Literature Survey 4.1

AC Induction Motor Fundamentals

AC induction motors are the most widely used motors for appliances, industrial motion control and automation. The primary advantages of induction motors (squirrel-cage type) as opposed to DC motors are as follows: • Rugged and simple construction (robust, long life) • Low cost (no permanent magnets) • Low maintenance (No commutators and brushes) • Lighter in weight for the same power rating (high torque/weight ratio) • Smaller in size for the same power rating (high torque/volume ratio) • More efficient • Can be used in hazardous (explosive or corrosive) environment • Easy to provide cooling as the windings are on the outside of the motor For a comprehensive treatment of the construction, working principle and classification of threephase as well as single-phase induction motors, refer [4] [5] [6] [7]. Figure 4.1 and 4.2 respectively show the typical stator and rotor of an induction motor. The defining equations for an induction motor are given below. Ns =

%slip =

120f p

Ns − Nb × 100 Ns

Bm ∝ 9

V f

(4.1)

(4.2)

(4.3)

4.1. AC Induction Motor Fundamentals

Chapter 4. Literature Survey

Figure 4.1: A typical stator

Figure 4.2: A typical squirrel cage rotor

Td ∝ Bm Ir cos θ

(4.4)

dωm dt

(4.5)

Td = Tl + J

where, Ns = Synchronous speed of the stator magnetic field, in RPM f = Supply frequency, in Hertz p = Number of poles on the stator Nb = Base speed, in RPM Bm = Amplitude of the magnetic flux density in the stator core, in Tesla Td = Instantaneous value of the developed motor torque, in Nm Ir = Rotor current, in Amperes θ = Phase angle between flux and rotor current, in radians Tl = Instantaneous value of the load torque, in Nm J = Moment of inertia of the motor-load system, in kg-sq.m ωm = instantaneous angular velocity of the motor shaft, in rad/sec The torque-speed characteristics of different types of single phase induction motors [4] are shown in figure 4.3. Lalit Patnaik

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4.1. AC Induction Motor Fundamentals

Figure 4.3: Torque-speed curves of different types of single phase induction motors A few important points to note about the induction motor: • Induction motors, at rest, appear just like a short circuited transformer and if connected to the full supply voltage, draw a very high current known as the Locked Rotor Current (LRC) and produce a torque which is known as the Locked Rotor Torque (LRT) or Starting Torque. The LRC of a motor can range from 500% of Full-Load Current (FLC) to as high as 1400% of FLC. Typically, good motors fall in the range of 550% to 750% of FLC. In order to limit the inrush current during starting various soft-starting techniques are employed. The LRT of an induction motor can vary from as low as 60% of the Full Load Torque (FLT) to as high as 350% of FLT. Typically, LRTs for medium to large motors are in the order of 120% of FLT to 280% of FLT [4]. • Percentage of slip varies with load on the motor shaft. As the load increases, the slip also increases. While large industrial motors can have a slip less than 1%, the typical full load slip for fractional horsepower motors is about 3-5% while shaded pole motors operate at a higher slip of about 7-10% • The efficiency as well as power factor of fractional horse power single phase induction motors is low (about 0.6). Integral horse-power single phase induction motors can have efficiency and power factor above 0.8. Efficiency of large three-phase induction motors could be as high as 0.9 [1]. • A single phase induction motor always receives pulsating electric power whereas it delivers constant mechanical power. Hence both the stator and rotor vibrate at twice the line frequency. Two-phase and three-phase motors have far less vibrations as the total instantaneous power they receive from all the phases is more or less constant. Lalit Patnaik

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4.2. Equivalent Circuit of Single Phase Induction Motor

4.2


Equivalent Circuit of Single Phase Induction Motor

The equivalent circuit of a single phase induction motor for steady state operation (supply is at fixed frequency and motor rotates at constant speed) is given in figure 4.4. This equivalent circuit is based on the concept of two revolving fields. The subscript ‘F’ stands for the forward revolving field while the subscript ‘B’ stands for the backward revolving field. The various notations used are defined as follows: 2r1 = Stator resistance 2r2 = Rotor resistance referred to the stator 2jx1 = Stator leakage reactance 2jx2 = Rotor leakage reactance reffered to the stator 2rm = resistance corresponding to the windage, friction, and iron losses 2jxm = magnetizing reactance In practice, x1 =x2 . The actual motor parameters can be extracted by conducting blocked rotor and light load tests. If the motor is stationary, s=1 and the equavent circuit is as shown in figure 4.5. Given the motor nameplate ratings and its equivalent circuit one can calculate the power output , efficiency and power factor at any speed.

Figure 4.4: Equivalent circuit of single phase induction motor

Figure 4.5: Equivalent circuit of single phase induction motor with stationary rotor

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4.3

4.3. V/f Control

V/f Control

Figure 4.6: Torque-speed and current-speed characteristics of a single phase induction motor

Figure 4.7: Voltage and torque versus frequency with V/f control The generic speed-torque characteristics of a single phase induction motor is shown in figure 4.6. The induction motor draws the rated current and delivers the rated torque at the base speed. When the load is increased beyond the rated load, while running at base speed, the speed drops and the slip increases. The motor can take up to 2.5 times the rated torque with around 20% drop in the speed. Beyond the breakdown torque (or pull-out torque), any further increase of load on the shaft can stall the motor. The torque developed by the motor is directly proportional to the magnetic field produced by the stator. So, the voltage applied to the stator is directly proportional to the product of stator flux and angular velocity. This makes the flux produced by the stator proportional to the ratio of applied voltage and frequency of supply (equation 4.3). By varying the frequency, the speed of the motor can be varied (equation 4.1). Therefore, Lalit Patnaik

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4.3. V/f Control


by varying the voltage and frequency by the same ratio, flux and hence, the torque can be kept constant throughout the speed range. This makes constant V/f the most common speed control of an induction motor. Figure 4.7 shows the relation between the voltage and torque versus frequency in the case of V/f control. At base speed, the voltage and frequency reach the rated values as listed in the nameplate. We can drive the motor beyond base speed by increasing the frequency further. However, the voltage applied cannot be increased beyond the rated voltage. Therefore, only the frequency can be increased, which results in the field weakening and the torque available being reduced. Above base speed, the factors governing torque become complex, since friction and windage losses increase significantly at higher speeds. Hence, the torque curve becomes nonlinear with respect to speed or frequency. The shape of the V/f profile (also called ‘Volts per Hertz’ profile) is often altered in specific frequency ranges to optimize the drive performance in a particular speed range [8]. For example, the shape of the profile shown in Figure 4.8 has been adjusted to provide higher voltages in the low frequency range. This modification provides a boost to the motor torque when the motor starts from rest to help overcome load friction and inertia. Within the mechanical limits of the motor, you can also increase the drive frequency beyond the nameplate value to achieve a higher speed. However, the available voltage may be limited, so motor torque will also be lower.

Figure 4.8: Typical V/f profile for a variable speed ACIM application If the input frequency to the motor is changed, the synchronous speed of the motor also changes accordignly. The frequency change has the effect of moving the torque profile curve to the left or right. If the motor input frequency is continuously adjustable, a family of torque profile curves will be created as shown in Figure 4.9. V/f control works very well for slowly changing loads such as fans or pumps [9]. But, it is less effective when fast dynamic response is required. In particular, high current transients can occur during rapid speed or torque changes. The high currents are a result of the high slip factor that occurs during the change. Fast dynamic response can be realized without these high currents if both the torque and flux of the motor are controlled in a closed loop manner. This Lalit Patnaik

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4.4. Vector Control

Figure 4.9: Torque profiles for variable frequency operation is accomplished using Vector Control techniques. Vector control is also commonly referred to as Field Oriented Control.

4.4

Vector Control

While V/f method controls the frequency and amplitude of the motor drive voltage, the vector control method controls frequency, amplitude as well as phase of the motor drive voltage. In other words, V/f control is a cycle-by-cycle control where as vector control is an instant-byinstant control. Ultimately, the components of the rotor current need to be controlled. The rotor current cannot be measured because the rotor is a steel cage and there are no direct electrical connections. Since the rotor currents cannot be measured directly, the application program calculates these parameters indirectly using parameters that can be directly measured. Using the Park transformation, as explained in section 11.2, the flux and torque producing components of the rotor current are extracted from the measured values of the stator currents. These components act as the feedback signals that are compared with the available references as shown in figure 11.2. Vector control makes it possible to control the induction motor in a manner similar to the control scheme used for the separately excited DC motor and therefore achieve the same levels of dynamic performance [10]. The purpose of vector control is to achieve fast dynamics without current surges. Organizing sudden step changes in the rotor currents (so as to get step change in torque) represents both the essence and the challenge of the vector control method [6]. The advantages of using vector control can be summarized as follows: • Higher efficiency which translates to lower energy consumption and lower operating costs • Reduced current spikes which translates to reduced cost of drive components • Excellent control dynamics

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Chapter 5

Wish Specifications 5.1

Wish Specifications for the Product

• Target application: Home appliances that use single phase induction motors e.g. air conditioners, refrigerators, washing machines, ceiling fans etc. • Rating: 0.37kW/0.5hp • Purpose: Increases efficiency and reduces audible noise of the home appliance • Connection: Between 230V mains and single phase induction motor of the home appliance • Mounting: In piggyback fashion on the motor (Instead of the start capacitor) • Features: – Inherent soft starting ensures minimal current surges during starting and transients, thus obviating the use voltage stabilizers. – Small form factor in order to enable mounting on the motor – Good efficiency even at low loads (fraction of full load)

16

Chapter 5. Wish Specifications

5.2 5.2.1

5.2. Tentative Specifications for the Internal Blocks

Tentative Specifications for the Internal Blocks Motor Specifications Type Frame Size kW / hp Amperes Hertz Volts Type Base Speed Insulation Class No. of poles Duty Enclosure Start Capacitor

Single Phase Induction Motor B56 0.37 / 0.5 3.8 50 220/230 Capacitor Start 1425 rpm B 4 Continuous SPDP 60-80 uF, 275V

Table 5.1: Motor specifications (given)

5.2.2

Inverter Specifications Input Voltage Output Voltage Continuous load capacity Output frequency Control method Switching frequency Temperature Range Cooling

380-420 V DC Two Phase AC 0 - Input Max 0.37 kW (3.8 A) 0 - 100 Hz in steps of 0.01 Hz Externally controlled SVPWM 10 kHz -25 to + 75 deg C Natural cooling

Table 5.2: Inverter specifications (tentative)

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5.2.3


Front-end Converter Specifications Input voltage Output voltage Output voltage ripple Switching frequency Power Input power factor

180-260 V (AC mains) 400 V (DC) 20 V 20 kHz 0.37 kW 1

Table 5.3: Front-end converter specifications (tentative)

5.2.4

EMI Filter Specifications Rated voltage Rated Current Insertion Loss

230 V AC 5A -

Table 5.4: EMI filter specifications (tentative)

5.2.5

DC/DC Converter Specifications Input Voltage, DC No. of outputs Output Voltage, DC Output Current, max Output voltage ripple Switching Frequency Temperature Range Cooling Method

380-420 V 2 15V, 5V 10mA, 500mA 50 mV 20 kHz -20 to +75 deg C Natural Cooling

Table 5.5: DC/DC converter specifications (tentative)

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5.2.6


Micro-controller/DSP Specifications Architecture CPU Speed (MIPS) Memory Type Program Memory (KB) RAM Bytes Temperature Range, deg C Operating Voltage Range, V I/O Pins Pin Count Digital Communication Peripherals Analog Peripherals Motor Control PWM Channels Quadrature Encoder Interface (QEI) Timers

16-bit 30 Flash 12 512 -40 to +125 2.5 to 5.5 20 28 1-UART, 1-SPI, 1-I2C 1-A/D 6x10-bit @ 1000(ksps) 6 1 3 x 16-bit 1 x 32-bit

Table 5.6: Micro-controller/DSP specifications (tentative)

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Part II

Design Phase

20

Chapter 6

Target Specifications 6.1

Product Specifications

• Power Rating = 0.37kW/0.5hp (Motor Shaft Output) • Input Voltage = 200-250V Single-Phase AC • Output Voltages = 0-250V, Two-Phase AC, 0-55Hz • Input Current – Maximum 5A – Power Factor > 0.98 – THD < 20% • EMI Specifications – Conducted Emission = 60 dBuV – Radiated Emission = 40 dBuV (at 3m distance) • Dimensions = 150mm x 100mm x 60 mm (maximum)

21

6.2. Induction Motor (off-the-shelf)

6.2

Chapter 6. Target Specifications

Induction Motor (off-the-shelf ) Type Make Serial No. kW / hp Amperes Hertz Volts Type Base Speed Insulation Class No. of poles Start Capacitor Run Capacitor

Single Phase Induction Motor Priya 0209 0.37 / 0.5 4.5 50 230 Capacitor Start, Capacitor Run 1440 rpm B 4 80 µF, Electrolytic 10 µF, AC

Table 6.1: Motor Specifications*: Name Plate Details *The induction motor specifications mentioned in the study phase were for a different motor which was found to be faulty. Hence a new motor with the above specifications was procured

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6.3

6.3. Front-End Converter

Front-End Converter Input Voltage Input Current Input Power Factor Cooling Outputs Voltages 400V DC +15V DC +15V DC (isolated) ±5V DC (isolated) +3.3V DC (isolated) Output Power Rating

200-250V, Single Phase AC, 50Hz 5A (maximum) >0.98 Natural Cooling Currents 1.5A DC 20mA 10mA 30mA 300mA 520W

Table 6.2: Front-End Converter Specifications

6.4

Inverter Input Voltage Input Current Switching Frequency Cooling Output Power Rating Output Voltages Output Currents

400V DC 3A (maximum) 16kHz* Natural Cooling 500W 0-250V, Two-Phase AC, 0-55Hz 0-3A in each phase

Table 6.3: Inverter Specifications *The choice of switching frequency was originally 10kHz. During testing of the CiPoS inverter board, it was noticed that there is no appreciable rise in the temperature of the device even at full load. Hence the switching frequency was increased in order to have smoother current waveforms and to ease the design of the anti-alias filters. Note that the ADC sampling frequency is same as the PWM switching frequency

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6.5. Software (Motor Control)

6.5


Software (Motor Control) Analog Inputs (12bit resolution)

Digital Inputs

Digital Outputs

Motor speed reference* DC link voltage Auxiliary winding current Main winding current CiPoS Fault dsPIC Reset Manual Switch-1 Manual Switch-2 PWM Outputs to Inverter Gate Drive Bleeder Resistor Control Control and Data Outputs to DAC

Table 6.4: Software Specifications *The motor speed reference is an analog input if it comes from an external potentiometer. Alternatively, it can also be a signal generated within the micro-controller

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Chapter 7

Design of Front-End Converter 7.1

Circuit Schematic

As discussed in section 2.3, the front-end converter consists of three parts namely the diode bridge rectifier, the boost unity power factor controller and the dc-dc converter that generates the dc supplies for the entire control circuitry. The simplified circuit schematic for the front-end converter along with the current drive requirements for all the various DC voltage outputs are shown in figure 7.1. Note that all the current values indicated are absolute maximum values taken from the datasheets of the load elements. All the auxiliary windings are wound on the same core as the boost inductor. The circuit schematic for the boost UPFC along with its controller circuit using UC3853 is shown in figure 7.2[11]. The calculation of the component values is shown in the following section. The supply for the UPFC controller IC is derived from yet another winding on the boost inductor core. But the voltage obtained from this winding is not a regulated one as the VCC pin of UC383 also serves the purpose of providing a voltage proportional to the RMS AC input voltage.for use in certain feed-forward compensation within the IC.

25

7.1. Circuit Schematic

Chapter 7. Design of Front-End Converter

Figure 7.1: Circuit schematic of the front-end converter

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7.1. Circuit Schematic

Figure 7.2: Circuit schematic for boost UPFC and its controller

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7.2. Design Equations

7.2 7.2.1


Design Equations Design of Boost UPFC

The detailed design procedure for Boost UPFC using UC3853 is explained in [12] and based on it, a MATLAB m-file was created to automate the calculation of the circuit element values for a given application. The m-file is included in Appendix-A. Specifications: POU T max = 460 Watts VOU T = 400VDC Line voltage range = 200 to 250VAC Line frequency range = 47 to 53Hz Maximum THD = 20% Power Factor = 0.98 Switching frequency = 75kHz Inductor Selection: POU T =

Pshaf t 373W = 460W = ηmotor × ηinverter 0.9 × 0.9

(7.1)

Assuming the efficiency of the Boost UPFC to be 90%, PIN =

POU T 460W = = 511W ≈ 520W ηupf c 0.9 √

Ipk

2 · PIN = = VIN min

√

(7.2)

2 · 520 = 3.68A 200

(7.3)

Typical value of ∆I, the peak-to-peak high frequency ripple current is about 20% of Ipk . ∆I = 0.2 × Ipk = 0.736A

(7.4)

The peak current in the inductor, ILpk , is the sum of the peak line current and half of the peak-to-peak ripple current. ILpk = Ipk + (∆I/2) = 4.05A (7.5) The value of the inductor is determined by the peak current at low input line voltage, the duty factor, D,at that input voltage and the switching frequency. This value of the duty factor is given by equation 7.6. √ √ VO − 2 · VIN min 400 − 2 × 200 Dmax = = = 0.293 (7.6) Vo 400 The inductance value is given by √ √ 2 · VIN min · Dmax 2 × 200 × 0.293 L= = = 1.5mH ∆I · fS 0.736 × 75 × 103 Lalit Patnaik

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(7.7) June 9, 2009



Output capacitor selection: Since there is no hold-time requirement in this application, the output capacitor selection is based on the second harmonic (100Hz) ripple on the dc link voltage. Based on a thumb rule of 0.2uF/W the required values is given by Co = (0.2µF/W ) × 520W = 104uF

(7.8)

To get reduced dc link voltage ripple a higher value is chosen. So, Co = 220µF Current sense resistor selection: RS , the current sense resistor, is selected to provide 1.0V at the maximum current expected in the inductor. 1V 1V RS = = = 0.25Ω (7.9) ILpk 4.05A Switch and diode selection: The power switch, Q must have a low RDSon rating and a peak voltage rating greater than the output voltage of the converter with some margin for transient overshoot, ripple voltage on the output and appropriate levels of derating. Accordingly, it was decided to use the MOSFET, FCP11N60 from Fairchild. For MOSFET gate protection, a 15V zener diode is added (between gate and source) to prevent VGS from going beyond 15V. The output diode, DOU T (same as D5 in Figure 7.1) must be rated for the peak output current and must be an incredibly fast diode with a reverse recovery time below 100ns. Accordingly, it was decided to use the fast recovery diode MUR860 from ON Semiconductor. Input diodes and capacitor selection: The input diodes that constitute the bridge rectifier should be rated for the maximum voltage at high line and for the maximum current at low line. An integrated diode bridge IC may be used for smaller footprint. Accordingly BR606 was chosen. A 5A fuse and an NTC may be connected between the supply mains and the diode bridge rectifier for protection and inrush current limiting respectively. The choice of the noise suppression capacitance, CIN is a compromise between power factor and EMI performance. A 0.47uF film-type capacitor is used. Multiplier set up: RAC defines the value of the current reference, IAC and should be chosen so as to have a maximum IAC of 500µA as the multiplier block within UC3853 becomes non-linear beyond that current. √ √ VIN max · 2 250 · 2 RAC = = = 707kΩ (7.10) 500µA 500 · 10−6 SMD 1206 resistors have a voltage rating of about 200V. Hence three resistors each of 390kΩ value are used in series to form RAC Current amplifier gain at the switching frequency: The voltage change across the sense resistor due to the down slope of the inductor current at the zero-crossing of the input voltage is given by, ∆VRS = Lalit Patnaik

VO RS 400 × 0.25 = = 0.89V LfS 1.5 × 10−3 × 75 × 103 29/104

(7.11) June 9, 2009



The gain of the current amplifier at the switching frequency is the ratio of the oscillator voltage and ∆VRS . The oscillator voltage in the UC3853 is 5.0Vpk-pk. 5 VOSC = = 5.62 ∆VRS 0.89

(7.12)

RM O = 3.9kΩ

(7.13)

GCA = Current amplifier compensation:

This value of RM O provides DC balancing of the amplifier input bias currents. RCZ sets the gain of the amplifier at the switching frequency. RCZ = GCA · RM O = 5.62 × 3.9k = 22kΩ

(7.14)

Calculate the unity gain crossover frequency of the current loop if CCZ were not present. fCI =

VO · RS · RCZ 400 × 0.25 × 22 × 103 = = 12kHz VOSC · 2πL · RM O 5 × 2π × 1.5 × 10−3 × 3.9 × 103

(7.15)

Choose the value of CCZ to have an impedance equal to or less than RCZ at fCI . CCZ min =

1 2π · fCI · RCZ

=

1 = 603pF 2π × 12 × 103 × 22 × 103

(7.16)

Choose a larger value of capacitance to increase the phase margin. CCZ =680pF The CCP and RCZ pole must be greater than the switching frequency. CCP max =

1 2π · fS · RCZ

=

1 = 96pF 2π × 75 × 103 × 22 × 103

(7.17)

Choose a smaller value of capacitance. CCP = 68pF Voltage amplifier compensation: The voltage loop amplifier is a transconductance amplifier so its compensation is a bit different from other types of amplifiers. The voltage divider consisting of RV I and RV D sets the DC output voltage. UC3853 internal reference voltage is 3.0V. Accordingly, the chosen resistor values are RV I = 1170kΩ = 390kΩ + 390kΩ + 390kΩ (7.18) Three SMD 1206 resistors are connected in series considering the voltage atress on the resistors. RV D = 12k||33k = 8.8kΩ

(7.19)

The gain of the voltage divider is given from the following equation: GV D =

VF B 3 = = 0.0075 VO 400

(7.20)

Output ripple voltage is given by the following equation where fL min is the minimum line frequency. Low line frequency will give the greatest value of VOpk VOpk = Lalit Patnaik

P 2π · 2fL min · CO · VO

=

520 = 10V ˙ 2π · 247 · 220 × 10−6 · 400

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(7.21) June 9, 2009



The amplifier gain calculation includes the gain of the voltage divider. The input range to the multiplier is the active range of the amplifier output voltage on the UC3853. ∆VCOM P is 4.5V on the UC3853. The % ripple used in the equation below is the amplitude of the ripple at the output of the voltage amplifier as a percentage of ∆VCOM P and the percentage is twice that specified for second harmonic voltage since the ripple is reduced by half in the power circuits. The equation uses %ripple in its numeric form. GV =

∆VCOM P · %ripple 4.5 × 0.025 = = 0.01125 VOpk 10

(7.22)

The gain of the voltage error amplifier alone is GV divided by the gain of the voltage divider. GV EA =

0.01125 GV = = 1.5 GV D 0.0075

(7.23)

A network connected from the output of a transconductance amplifier to ground determines its gain and frequency response. The gain of the amplifier is set for loop stability without regard to DC gain or THD. The gain of the amplifier is: GV EA = GM × XCV C

(7.24)

Where GM is the transconductance of the UC3853 voltage amplifier as specified in the data sheet as 485µS. XCV C is the impedance of CV C at the second harmonic of the line frequency (2 · fL min ). Solve the equation for XCV C then convert the impedance to a capacitance value. CV C =

GM 2π · 2fL min · GV EA

=

485 × 10−6 = 0.548µF 2π × 2 × 47 × 1.5

(7.25)

Choose CV C =0.47µF The unity gain crossover frequency of the now completed voltage control loop is found next. The following equation gives the frequency at which the loop gain is equal to one. fV2 I =

(2π)2

P · GM · GV D · CO · CV C · ∆VCOM P · VO

(7.26)

Solve for fV I . r 1 520 × 485 × 10−6 × 0.0075 fV I = = 16Hz (7.27) 2π 220 × 10−6 × 0.47 × 10−6 × 4.5 × 400 RV C is added to the loop compensation to give a pole at fV I . The value of RV C is the resistance equal to the impedance of CV C at fV I . This gives approximately 45◦ of phase margin. A smaller value of RV C will increase the phase margin at the expense of loop bandwidth. RV C =

1 1 = ≈ 22kΩ 2π · fV I · CV C 2π × 16 × 0.47 × 10−6

(7.28)

CV CZ is added in series to RV C to break the DC current path from the output of the voltage error amplifier to ground because the limited current capability of the transconductance amplifier stage. The zero added to the loop compensation increases the DC regulation of the output at the expense of increased peak-to-peak voltage excursions during transients. This zero introduced by CV CZ must be set at least two octaves below fCI to maintain a reasonable phase margin. The value of CV CZ must therefore be at least four times the value of CV C . CV CZ = 4 · CV C = 4 × 0.47 × 10−6 = 1.88µF Lalit Patnaik

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(7.29) June 9, 2009



Choose CV CZ = 4.7µF to give increased phase margin. Voltage Feedforward: The feedforward voltage comes from the bias supply VF F , which is supplied by a winding on the boost inductor. For the example converter, the turns ratio is set to give 15VDC with minimum input voltage after all parasitic losses are taken into account. The second harmonic ripple voltage must be held to 2% peak of VF F min according to the THD budget.The numeric value of THD is used in the equation. The peak-to-peak ripple voltage is given by: VR = π · VF F · T HD = π × 15 × 0.02 = 0.942Vpk−pk

(7.30)

The current drawn by the control circuits is about 15mA. The value of CF F is given by: CF F =

IF F 0.015 = = 170µF VR · 2fL min 0.942 × 2 × 47

(7.31)

Choose CF F =220µF for lower voltage ripple. Starting Resistors: CF F must be charged to 11.5V to start the UC3853 and it is trickle charged from VIN by the current through RB . The current through RB at high line must not exceed the bias current of the UC3853 or VF F will not track the input voltage and feedforward will be lost. The value of RB may not be too large or the delay between the application of power and the start of the circuit will be too long. If the current through RB is less than 500µA at low line the circuit will never start. A 0.6sec delay at low line is chosen as the maximum value. This is an arbitrary decision within the guidelines given. √ √ 0.6 × 2 × 200 tDELAY · 2 · VIN min = = 67kΩ (7.32) RB = V F F · CF F 11.5 × 220 × 10−6 Split this into two 33kΩ resistors in order to reduce the voltage stress on the resistors. At high line this gives 3.4mA of bias current which is less than IF F (15mA) so this value is acceptable. In case UC3853 still fails to come out of under-voltage lock-out the RB value may be decreased so long as the bias current at high line remains below 15mA.

7.2.2

Design of Boost Inductor

The magnetics design of the boost inductor of required value (1.5mH) was carried out using area product method as described below. Keeping in view the product size constraints, the chosen core material is amorphous iron (distributed air gap) as it gives a high maximum flux density of 1.56T. Peak energy stored in the boost inductor is given by, 1 2 1 E = LILpk = × 1.5 × 10−3 × 4.052 = 12.3mJ 2 2

(7.33)

The area product is given by, AP = AW AC = Lalit Patnaik

2E 2 × 12.3 × 10−3 √ = 0.93cm4 = 6 KW KC JBm 0.4 × 2 × 3 × 10 × 1.56 32/104

(7.34) June 9, 2009



where, AW = Window Area AC = Core Area KW = Window Factor√≈ 0.4 for inductor KC = Crest Factor = 2 for sinusoidal current J = Current density in copper wire = 3A/mm2 A slightly larger core is selected to allow for additional turns, insulation tapes and higher wire guage if required later on. Accordingly, the chosen core is MP3510MDGC toroidal core from MetGlas. But due to problems in procurement of MetGlas cores, it was decided to use a standard ferrite EE core available in the power electronics lab at CEDT. The core dimensions are as indicated in figure 7.3

Figure 7.3: Ferrite EE-core dimensions

For the EE core, Bm = 0.3T and hence re-substituting in equation 7.34, the new value of AP is 4.83 cm4 . For the given core dimensions, Window Area, AW =1cm × 3cm = 3 cm2 Core Area, AC = 1.15cm × 1.5cm = 1.725 cm2 Area Product, AP = AW × AC = 10.35 cm4 > 4.83 cm4 Hence, this core will suffice for the application. On the EE core the number of turns and the air gap length were adjusted iteratively to arrive at an inductance value of 1.5mH. The number of turns arrived at is NL =101. As per the current rating, the chosen wire guage is SWG#20. The inductor was than tested with a standard boost converter circuit to check for variations in inductance value at different dc current levels. With variation in IDC from 0.6A to 3.5A, the inductance value changed from 1.63mH to 1.44mH, which is acceptable in the present application. Lalit Patnaik

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June 9, 2009


7.2.3


Design of DC-DC Converter

As shown in Figure 7.1, the DC-DC converter consists of auxiliary windings on the boost inductor core followed by required voltage regulators with filter capacitors. It generates the following DC supplies: • +15V for isolation amplifier (ISO124, both primary side and secondary side) and gate drive circuit within CiPoS IPM • +/-5V for current sensors (ACS712) and signal conditioning circuits • +3.3V for micro-controller (dsPIC33FJ256MC710) and DAC (AD5343) The chosen voltage regulators are: • +15V : UA7815 from TI [13] • +/-5V : UA7805 from TI [13] • +3.3V : TC2117 from Microchip [14] The diodes D6, D7, D8, D9 (in Figure 7.1) are 0.2A fast recovery diodes (1N4148). D5 is a 1A fast recovery diode (1N4934) The required number of turns for the various windings are as follows: For the 15V windings, considering the drop across the diode and the drop-out of the voltage regulator, 19V across the winding is sufficient. But in order to reduce the size of the filter capacitors, a larger voltage ripple should be allowed at the input of the voltage regulators. Hence the winding voltage is chosen as 23V peak. So, the required number of turns is given by N15 =

NL = 7.14 (325/23)

(7.35)

Choose N15 = 8 turns Similarly, the 5V windings are designed for a peak winding voltage of 15V. So, the required number of turns is given by NL N5 = = 4.66 (7.36) (325/15) Choose N5 = 5 turns The 3.3V winding is designed for a peak winding voltage of 6.5V only as the maximum input voltage for the 3.3V LDO is limited to 6V. So, the required number of turns is given by N3.3 =

NL = 2.02 (325/6.5)

(7.37)

Choose N3.3 = 2 turns Lalit Patnaik

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June 9, 2009


7.2.4


Design of NTC Thermistor

In order to limit the inrush current at switch on, an NTC thermistor is provided on the AC side of the diode bridge rectifier. The design of the NTC involves the following steps [15] The rated resistance is given by, √ √ VIN 2 250 × 2 R25 = 1 = 1 = 7Ω (7.38) 2 × (IF SM of diodes) 2 × 100 Joules rating is given by, √ √ 1 1 EN T C = COU T (VIN 2)2 = × 220 × 10−6 × (250 2)2 = 13.7J 2 2

(7.39)

Maximum steady state current is given by, IM AX

√ √ 469 2 POU T 2 = = 3.6A = ηVIN min 0.9 × 200

(7.40)

Based on the above calculations the chosen NTC is SCK104 (10Ω, 4A).

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June 9, 2009

Chapter 8

Design of Inverter 8.1

Circuit Schematic and Explanation

The inverter bridge features a three-arm voltage-source inverter, comprising two power switches per arm, with anti-parallel body- diodes. The inverter connects to the motor windings as shown in figure 8.1. Such a topology was chosen as opposed to an H-bridge topology as it is more reliable and better from EMC perspective [16].

Figure 8.1: Circuit schematic showing the connection of the inverter and the motor The phase relationship between Va , Vb and Vc is also shown in the phasor diagram in figure 8.1. Note that the magnitudes of Va , Vb and Vc are equal in order to have equal voltage stress on all devices, thus improving the device utilization and providing the maximum possible output voltage for a given DC bus voltage. Such a phase relationship ensures that the main winding (connected between phases a and c) and auxiliary winding (connected between phases a and 36

Chapter 8. Design of Inverter

8.1. Circuit Schematic and Explanation

c) voltages are always 90 degree apart thus eliminating the need for a capacitor. The angle θ between phases a and c affects the relative magnitudes of VAU X and VM AIN is hence decided by the ratio α=VAU X /VM AIN . For a given motor, α is a constant. The direction of rotation can be easily reversed by choosing a negative value of θ. The single phase induction motor drives a mechanical load (e.g. compressor of air conditioner or refrigerator). In the demonstration setup, mechanical loading of the motor can be done either by coupling its shaft to an electrically loaded dc generator or by using a prony brake. For the given power rating, the maximum motor winding current is 3.5A. Taking sufficient safety margin (for transients) and thermal derating, an IPM with switch rating of 12A, 600V (IKCS12F60AA) should cater to the needs. The circuit schematic for the inverter board using CiPoS IPM IKCS12F60AA from Infineon is shown in figure 8.2[17]. Apart from the IPM it includes some peripheral circuitry for over-current fault logic, gate drive pull-up etc. The CiPoS IPM has in-built over-temperature protection with hyteresis.

Figure 8.2: Circuit schematic for inverter A bleeder resistor, also known as a brake chopper, is connected across the dc link capacitor so as to ensure that the DC link voltage does not rise to levels at which the capacitor can burst. The bleeder resistor may be switched in or out of the circuit depending on the sensed dc bus voltage magnitude. The control strategy is like that of an on/off controller with hysteresis. The upper Lalit Patnaik

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June 9, 2009


Chapter 8. Design of Inverter

and lower thresholds of the hysteresis band is software programmable and is nominally set at 430V and 400V. The MOSFET for controlling the switching in or out of the bleeder is chosen as FCP11N60 from Fairchild. The MOSFET switching control input comes from the dsPIC micro-controller and a gate driver IC, MCP1402 from Microchip is used to drive the MOSFET. An anti-parallel diode should be connected across the bleeder resistor to avoid voltage spikes due to inductance associated with the bleeder resistor.

8.2

Design Equations

The governing equations for the inverter are as follows: The turns ratio of the auxiliary winding to the main winding is given by α=

VAU X VM AIN

(8.1)

For the given motor, α was determined by running the motor at rated voltage with its start and run capacitors connected and measuring the voltages across the main and auxiliary windings. For experimental observations, the value of α was found to be 0.89. |Va | = |Vb | = |Vc | = V1

(8.2)

VM AIN = Va − Vc

(8.3)

VAU X = Vb − Vc

(8.4)

θ = 180◦ − 2 tan−1 (α)

(8.5)

For the given motor, θ = 180◦ − 2 tan−1 (0.89) = 96.7◦ Using θ = 90◦ would also give satisfactory results. √ 1 + α2 V1 = |VM AIN | 2 Va = V1 × cos(ωt) +

VDC 2

Vb = −V1 × cos(ωt) +

VDC 2

Vc = V1 × cos(ωt ± θ) +

VDC 2

Substituting equations 8.7, 8.8 and 8.9 in equations 8.3 and 8.4, we get θ θ VM AIN = 2V1 sin sin ωt + 2 2 θ θ VAU X = −2V1 cos cos ωt + 2 2 Lalit Patnaik

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(8.6)

(8.7)

(8.8)

(8.9)

(8.10) (8.11)

June 9, 2009

Chapter 9

Design of Sensing Circuits The design of the sensing and analog signal conditioning circuits is discussed in this chapter. The sensed quantities are dc link voltage (VDC ), auxiliary winding current (Iα ) and main winding current (Iβ ). Hence one voltage sensor and two current sensors are required. Quad opamps (TS914 from STMicroelectronics [18]; rail-to-rail voltage swing) are used for the signal conditioning circuits that introduce suitable gain, level-shifting and filtering to the sensor outputs before feeding them to the micro-controller ADC input. Note that even though the sensors will operate on a single supply, the signal conditioning opamps will need dual supplies(±5V). Protection diodes (a pair of schottky diodes in series) are used to ensure that the voltage at the ADC input pin does not go beyond the safe range (-0.3V to +3.6V)

9.1

Voltage Sensing

The circuit schematic for sensing of DC link voltage is shown in figure 9.1. It comprises a high precision resistive divider followed by an isolation amplifier, ISO124 from Texas Instruments [19]. For accurate voltage division, the voltage divider should comprise of metal-film resistors (1% tolerance, 100ppm/◦ C temperature coefficient). The resistance values are selected so as to map the dc link voltage of 0-450V to the micro-controller analog input voltage of 0-3.3V. In order to avoid arcing across the resistors due to high voltage, three 150k resistors (SMD 1206, 1% tolerance) are connected in series. The resistive divider comprising of 450kΩ and 3.3kΩ gives a voltage of 3.27V to the isolation amplifer (Gain=1) at an absolute maximum dc link voltage of 450V. At a nominal dc link of 400V, the isolation amplifer output is 2.91V. The primary and secondary sides of the isolation amplifier are powered up by isolated windings taken from the same core as the boost inductor. In order to prevent folding back of high frequency components onto the low frequency spectrum after A/D sampling, an anti-alias filter needs to be used. A standard 2nd order Sallen Key low pass filter was designed using FilterLab software from Microchip. The design parameters used are: • fCU T OF F = 1kHz • fSAM P LIN G = 16kHz 39

9.2. Current Sensing

Chapter 9. Design of Sensing Circuits

• ADC resolution = 12 bits • SNR = -45dB 5

D

4

3

2

1

fCU T OF F has been taken sufficiently lower than the Nyquist frequency (fSAM P LIN G /2) keeping in view the slow roll off of the anti-alias filter. The element values for the Sallen Key filter are: R1 = 7.5kΩ, R2 = 15kΩ, C1 = 10nF and C2 = 22nF, which leads a second order pole at r 1 1 = 1012Hz. (9.1) fAAF = 2π R1 R2 C1 C2

D

P +15Vb

+15Vc

R75 150k

C

C

C57 1uF

C58 1uF

R48 150k

+3.3V C30

U5 1 2 3 4

R49 150k

1 2 3 4

5 6 7 8

22nF

R51 7.5k

DN3 BAT54S

R52 22k

ISO124 Isolation Amplifer for Voltage Sensing

R50 3.3k

TP3 1 TP

5 6 7 8

7IN+ 7OUT 7IN-

C29 10nF

B

R53 470

R54 470 V_DC

B

N

Figure 9.1: Circuit schematic for voltage sensing A

A

9.2

Current Sensing 5

4

3

2

1

Sensing of stator currents is done using hall-effect current sensor from Allegro : ACS712 [20] which has the following salient features: • Small footprint, low-profile SOIC8 package • 5.0 V, single supply operation • 80 kHz bandwidth • 2.1 kVRMS minimum isolation voltage • 100 mV/A output sensitivity The circuit schematic for current sensing is identical for both Iα and Iβ and is shown in figure 9.2 for one of the two currents). Some signal conditioning circuitry for level-shifting and amplification is added to better utilize the full range of the ADC. The anti-alias filter used is same as that used for the voltage sense circuit. The specific tasks carried out by the signal conditioning circuits are: 1. Remove DC bias of 2.5V from current sensor output Lalit Patnaik

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June 9, 2009

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A

B

Uout to J6 Motor 1 TTC

1 2 3 4

U3

5 6 7 8

5 6 7 8

Current Sensor I_alpha

ACS712

1 2 3 4 +5V

C22 0.1uF

C21 1nF

R17 3.3k

R16 3.3k

+5V

R18 82k

R20 82k

R19 220k

1IN1OUT 1IN+

R21 220k

4

R23 3.3k

R22 3.3k R24 100k

+3.3V

R26 100k

R25 100k

2IN2OUT 2IN+

R27 100k

R40 7.5k

3

C25 10nF

R41 15k

C26

22nF

5IN+ 5OUT 5IN-

R42 470

DN1 BAT54S

+3.3V

2

1

R43 470

TP

TP1

I_ALPHA

1

4. Anti-alias filtering

C

D

5

C

D

Chapter 9. Design of Sensing Circuits

Figure 9.2: Circuit schematic for current sensing

June 9, 2009

A

B

9.2. Current Sensing

2. Amplify with Gain = 2.7

3. Add DC bias of 1.65V

Chapter 10

Design of Micro-controller Circuit The dsPIC micro-controller was chosen because of it’s low-cost, free and exhaustive software and documentation support, cheap programming interface (MPLAB ICD costs about Rs 8000/while a JTAG debugger costs about Rs 75,000/-). The salient features of the chosen microcontroller (dsPIC33FJ256MC710) are as follows: • CPU Speed: 40 MIPS • Temperature range: Industrial (-40C to +85C) • Packaging: 100-pin TQFP (14x14x1 mm) • Architecture: 16-bit, Modifed Harvard • On-chip Flash Memory: 256 Kbytes • On-chip Data SRAM: 30 Kbytes • Motor Control PWM: 8 channels • ADCs: – 2 ADCs, 24 channels – 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion • 83 base instructions: mostly 1 word/1 cycle Along with the dsPIC micro-controller, the other supporting peripheral components are as follows: • Supply de-coupling capacitors for each of the VDD pins • Oscillator circuits: 8MHz and 32kHz • MPLAB ICD2 and PICkit2 debugging/programming interfaces • Manual reset with switch debouncing • Two manually operated switches with debouncing capacitors 42

Chapter 10. Design of Micro-controller Circuit • Power-on LED indicator • Dual-channel 12-bit parallel DAC (AD5343) [21] for debugging purpose The circuit schematics of the dsPIC micro-controller were adapted from the available circuit schematics for the Explorer-16 evaluation board supplied by Microchip.

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June 9, 2009

Chapter 11

Software Design 11.1

Open Loop Control Strategy

Figure 11.1: Open-loop control strategy Before getting into the closed-loop vector control algorithm explained in the next section, one needs to understand the open-loop scalar control algorithm depicted in Figure 11.1. It shows the open loop V/f control scheme which gives performance almost as good as the vector control scheme in steady state. Where vector control improves upon V/f control is in terms of the transient performance. In figure 11.1, VS is obtained from the speed reference ωref , by taking 44

Chapter 11. Software Design

11.2. Closed Loop Control Strategy

a suitable V/f profile for the given motor. A simple approach would be to choose a constant slope till f < frated and then saturate the V/f profile beyond the rated frequency. Figure 4.8 depicts a V/f profile with voltage boosting in the low frequency region. The integration of the speed reference ωref gives the angle γ of the voltage space vector VS at any given instant of time. In the stationary axis, the two phase quantities are obtained as VSα = VS cosγ

(11.1)

VSβ = VS sinγ

(11.2)

The tranformation from α-β to a-b-c is done as per the phasor diagram shown in figure 8.1. An alternate way of doing the open-loop control is to take the reference input as the frequency reference. From the frequency reference one decides the rate at which the PWM compare register needs to sweep across a stored sine look-up-table. Also, by suitably scaling the frequency reference, one arrives at the required amplitude reference for the inverter pole voltages Va, Vb, and Vc.

11.2

Closed Loop Control Strategy

Figure 11.2: Closed-loop control strategy Figure 11.2 shows the closed loop control scheme for the system. ISqref and ISdref are the torque and flux references which are respectively computed from the available speed reference, ωmref and the estimated rotor speed, ωm . The measured values of the stator currents, Iα and Iβ are transformed to the synchronously rotating frame of the rotor flux using the Park Transformation as given by equations 11.3 and 11.4 below. Lalit Patnaik

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11.2. Closed Loop Control Strategy

Chapter 11. Software Design

iSd = iSα cos ρ + iSβ sin ρ

(11.3)

iSq = −iSα sin ρ + iSβ cos ρ

(11.4)

where, ρ is the rotor flux position and is an estimated quantity. The Inverse Park Transformation is given by equations 11.5 and 11.6 below. VSα = VSd cos ρ − VSq sin ρ

(11.5)

VSβ = VSd sin ρ + VSq cos ρ

(11.6)

The classic numerical PI (Proportional and Integral) controller is well suited to regulating the torque and flux feedback to the desired values as it is able to reach constant references, by correctly setting both the P term (Kp) and the I term (Ki) which are respectively responsible for the error sensibility and for the steady state error. The numerical expression of the PI regulator is as follows: k−1 X Uk = Kp ek + Ki ek + en (11.7) n=0

Equation 11.7 can be represented by the following figure:

Figure 11.3: PI controller

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June 9, 2009

Chapter 12

Industrial Design

Figure 12.1: Industrial design for the product Figure 12.1 shows the concept sketches for the industrial design of the proposed product. The salient features are as follows: • Physical dimensions: 150mm x 100mm x 60mm (maximum) • Heatsink is externally mounted on the metallic casing • Two connectors: Power connector (2-line input) and Motor connector (3-line output) • Power-on LED indicator for mains supply and control supply Actual prototype of the product casing depicted above was not ready at the time of writing this report. 47

Part III

Engineering Phase

48

Chapter 13

CiPoS Board The inverter circuit discussed in Chapter-8 is implemented on a single PCB henceforth referred to as the CiPoS board. The circuit schematics of the CiPoS board were adapted from the available CiPoS evaluation board supplied by Infineon. The board was fabricated at ChipKraft Technologies and has the following salient features: • Two-layer board: TOP and BOTTOM routing • Copper thickness: 75µm (2 oz.) • Board thickness: 1.6mm • Substrate: FR4 glass epoxy • Finish: HASL (Hot Air Solder Levelling) • Solder Mask Finish: Green SMOBC (Solder Mask Over Bare Copper) • Track-widths were chosen using nomographs given in ”Printed Circuit Boards - Design and Technology” by Bosshart, Walter C.[22] • Minimum track width: 12 mil • Footprints were made as per the physical dimensions mentioned in the IC datasheets • Board dimensions = 87mm x 37mm The CiPoS board contains the following: 1. CIPOS Integrated Power Module (IKCS12F60AA) [17] 2. Over-current trip circuit using LM2903 dual comparator [23]

13.1

PCB Schematics

Figure 13.1 shows the complete CiPoS board schematics. 49

4

3

2

1

D

1 2 3 4 5 6 7

R1 4700

R4 4700

R5 4700

R6 4700

/UH R7 100 R8 100 /WH R9 100

RMC7

/UL

/VL

C11 4.7u C10 4.7u

R10 100

C9 4.7u

R11 100 R12 100

/WL

C1

J25 1 2 3

R3 4700

/VH

CON7

C

R2 4700

C2

C3

C4

C5

C6

VDD

Vctr

CON3

C12 100u

PMC3

C19 100n

CiPoS IPM IKCS12F60AA J23

D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

J26

P

1 CON1 TT

13.1. PCB Schematics

Lalit Patnaik

5

J24

J27

W

1 CON1 TT

J28

V J29

U

1

1 CON1 TT

CON1 TT

C

C18 220u

CON20

50/104

GND

C17 R14 1.2k R17 3.9k

R20 2k

R15 20k

J22

B

1 2 3 4 5 6 7 8

C14 C15

R16 2k

R19 20k

100n

100n

3 Q1 12N2222

R13 C7 0.03 0.1u

J30

N

1

B

CON1 TT

C16 100n

June 9, 2009

A

A

Title IPM BOARD RMC = Relimate Connector PMC = Powermate Connector TT = Tower Tag

Size A Date:

5

4

3

Document Number IPM1 Sunday, May 10, 2009 2

Figure 13.1: OrCAD schematic for CiPoS board

Rev 1.1

LALIT PATNAIK Sheet

1

1

of 1

Chapter 13. CiPoS Board

2

C8 1n

CON8 Dual Comparator LM393

R21 510k

R23 1k

R22 10k

R18 10k

/Fo C13 100p

100n


13.2

13.2. PCB layout

PCB layout

The figures on the following pages show the different layers of the CiPoS board OrCAD layout. Figures 13.2 and 13.3 show the layout of the TOP and BOTTOM routing layers. Figures 13.4 and 13.5 show the Silk-Screen Top and Silk-Screen Bottom layers. Figure 13.6 shows the Drill layer with the drill chart. Some of the drill sizes mentioned in the drill chart were changed by the fabricator as per the drill sizes available with them. Figures 13.7 and 13.8 show the Solder-Mask Top and Solder-Mask Bottom layers.

Figure 13.2: OrCAD Layout for CiPoS board: TOP routing layer

Figure 13.3: OrCAD Layout for CiPoS board: BOTTOM routing layer

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13.2. PCB layout


Figure 13.4: CiPoS board: SST layer

Figure 13.5: CiPoS board: SSB layer

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13.2. PCB layout

Figure 13.6: CiPoS board: DRD layer with drill chart

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June 9, 2009

13.2. PCB layout


Figure 13.7: CiPoS board: SMT layer

Figure 13.8: CiPoS board: SMB layer

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June 9, 2009


13.2. PCB layout

Figure 13.9: Photograph of the asssembled CiPoS board with heat sink

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June 9, 2009

13.3. Connector Details

13.3


Connector Details

Figure 13.10: CiPoS board: Input and Outputs Inputs: 1. DC Link: 400V (FASTON Tabs - P and N) 2. DC supply for comparators and gate drivers: +3.3V, +15V (3-pin Combicon connector) 3. 6 PWM control inputs - 3 high-side, 3 low-side - from microcontroller board (Pin no.1-6 of 7-pin Relimate connector) Outputs: 1. PWM output - 3 pole voltages (FASTON Tabs - U, V, W) 2. Fault output (over-current trip) to micro-controller board (Pin no.7 of 7-pin Relimate connector) Table 13.1 describes the 7-pin Relimate connector which interfaces the CiPoS inverter board to the dsPIC control board Pin No. 1 2 3 4 5 6 7

Pin Name /UH /VH /WH /UL /VL /WL /Fo

Table 13.1: 7-pin Relimate Connector: PWM signals and Fault Output Table 13.2 describes the 3-pin Combicon connector used to deliver power to the protection, control and drive portions of the inverter board. Lalit Patnaik

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June 9, 2009


13.4. Bill of Materials

Pin No. 1 2 3

Pin Name VDD , +15V VCT R , +3.3V/5V GND

Table 13.2: 3-pin Combicon Connector: DC supplies to control part of CiPoS board FASTON Tabs are provided for connecting the high power inputs and outputs on the board. The tabs corresponding to P and N are the points where the DC link voltage is to be connected. U, V and W are the points where the outputs can be drawn from the inverter board. Note: In order to ensure single point grounding, nets GND and N are connected at a single point in the CiPoS board. Care should be taken not to connect them anywhere else in the system.

13.4

Bill of Materials Ref. R1-R6 R7-R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 C1-C6 C7 C8 C9-C11 C12 C13 C14-C15 C16 C17 C18 C19 J23

Lalit Patnaik

Component 4.7kΩ, 1/8W, 5% 100Ω, 1/8W, 5% 0.03Ω, 5W, 5%,Current Sense Resistor 1.2kΩ, 1/8W, 5% 20kΩ, 1/8W, 1% 2kΩ, 1/8W, 1% 3.9kΩ, 1/8W, 5% 10kΩ, 1/8W, 1% 20kΩ, 1/8W, 1% 2kΩ, 1/8W, 5% 510kΩ, 1/8W, 5% 10kΩ, 1/8W, 1% 1kΩ, 1/8W, 5% 1nF, 25V 0.1uF, 630V, 10%, DC link capacitor 1nF, 50V 4.7uF, 35V, Bootstrap capacitors 100uF, 16V 100pF, 25V 100nF, 25V 100nF, 25V 100nF, 25V 220uF, 35V 100nF, 25V IKCS12F60AA, CiPoS IPM

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Type/Package SMD (1206) SMD (1206) TH SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) SMD (1206) TH SMD (1206) TH (Al Electrolytic) TH (Al Electrolytic) SMD (1206) SMD (1206) SMD (1206) SMD (1206) TH (Al Electrolytic) SMD (1206) TH

June 9, 2009

13.5. Corrections in CiPoS board J22 Q1 J24 J25 U,V,W,P,N

13.5


LM393/LM2903, Dual comparator SMD(SOIC8) BC817, NPN transistor SMD (SOT23) 7-pin Relimate Connector TH 3-pin Combicon Connector TH FASTON Tab Connectors TH (Width=6.3mm) Table 13.3: Bill of Materials for CiPoS Board

Corrections in CiPoS board

Following are the errors in the CiPoS board with the associated remedies 1. C1-C6 are not connected to GND (Error in schematic) Remedy: Short the GND side pad of any one among C1-C6 with the ground copper pour on the bottom layer 2. R14 is not connected to Pin-8,9,10 of Cipos (Incomplete Routing) Remedy: Use jumper wire 3. NPN Transistor (Q1) pads are incorrect (B and E are inter-changed) Remedy: Mount the SMD transistor upside down after bending its terminals backwards. 4. Silkscreens of C7 and R13 are inter-changed Remedy: Be mindful of the above error while assembling C7 and R13 on the board 5. Silkscreen does not appear on the bottom layer and in some parts of the top layer Remedy: Use the OrCAD design files for reference during board assembly. Increase silkscreen thickness to 8mil for future fabrication passes 6. For future fabrication passes, shift silkscreen locations away from vias wherever they coincide 7. The edge of the board on the heat-sink side of Cipos may need to be filed to enable proper contact between Cipos and the heat-sink

13.6

PCB Testing

Following are the steps to be followed for testing the functionality of the CiPoS board. 1. No load testing: (a) Connect +15V and +3.3V/5V DC supplies to the 3-pin Combicon connector. (b) Connect 3-phase PWM outputs from the micro-controller through the 7-pin Relimate connector. Lalit Patnaik

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June 9, 2009


13.6. PCB Testing

(c) Supply a DC link voltage (

+3.3V D1 dsPIC LED

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1N4934 PMC2

+3.3V

+3.3V

+3.3V

37

C3 0.1uF

DAC_DB4 DAC_DB5 DAC_DB6 DAC_DB7

DAC_PD\ DAC_LDAC\ DAC_HBEN DAC_DB0 DAC_DB1 DAC_DB2 DAC_DB3

DAC_CS\ DAC_A0 DAC_WR\ DAC_CLR\

+3.3V

PGC PGD RA9/PMA7 RA10/PMA6

June 9, 2009

C2 0.1uF

C17 0.1uF

C18 47uF

46

62

C4 0.1uF

C5 0.1uF

DAC Interface for Debugging

PWM outputs to Cipos Board DAC Output (For Debugging)

A

RMC2

Title dsPIC Board: Sheet-1

+3.3V DAC_PD\

AD5343 12bit DAC

PWM1H\

1 2

DAC_DB7 DAC_DB6 DAC_DB5 DAC_DB4 DAC_DB3 DAC_DB2 DAC_DB1 DAC_DB0 C64 0.1uF

Size B Date:

5

C20 47uF

FLT_CIPOS\

DAC_HBEN

J4

C6 0.1uF

C19 0.1uF

R14 470

Fault Input (over-current trip) from Cipos Board ->

U8

+3.3V

C1 0.1uF

From Winding L3.3 ->

Document Number dsPIC1

Rev 1.1

Author: LALIT PATNAIK, M.Tech CEDT

Tuesday, May 12, 2009

Sheet 1

1

of

1

Chapter 14. dsPIC Board

30

R15 100

1N4934 R13 10k

Bypass Capacitors 2 16

Power Indicator (GREEN)

+3.3V

D2 L3.3

Digital I/O: PWM outputs, Fault Input

A

D

R7 47k

RJ11

RG15 VSS VDD RC14 PMD5/RE5 RC13 PMD6/RE6 OC1/RDO PMD7/RE7 IC4/RD11 T2CK/RC1 IC3/RD10 T3CK/RC2 IC2/RD9 T4CK/RC3 IC1/RTCC/RD8 T5CK/RC4 INT4/RA15 PMA5/SCK2/CN8/RG6 INT3/RA14 PMA4/SD12/CN9/RG7 VSS PMA3/SDO2/CN10/RG8 OSC2/CLKO/RC15 MCLR OSC1/CLKI/RC12 PMA2/SS2/CN11/RG9 VDD VSS TDO/RA5 dsPIC33FJ256MC710 VDD TDI/RA4 RAD/TMS RA3 INT1/RE8 RA2 INT2/RE9 SCL1/RG2 C1IN+/AN5/RB5 SDA1/RG3 C1IN-/AN4/RB4 SCK1/INTO/RF4 C2IN+/AN3/RB3 SDI1/RF7 C2IN-/AN2/RB2 SDO1/RF8 PGC1/AN1/CN3/RB1 U1RX/RF2 PGD1/ANO/RBO U1TX/RF3

B

R6 1k

1

1 2 3 4

PWM3L\ PWM2H\ PWM2L\ RG13 RG12 RG14 PWM1H\ PWM1L\ RA7 RA6 FLT_CIPOS\ RG1 RF1 RFO

PGD

U1

PGC/RB6 PGD2/OCFA/RB7 PMA7/RA9 PMA6/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREF/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 PMA1/AN14/RB14 PMAO/AN15/CN12/RB15 VSS VDD CN2O/RD14 CN21/RD15 U2RX/RF4 U2TX/RF5

+3.3V

DPST SW

1 2 3 4 5 6

PGC PGD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

R5 4.7k

J1

C9 0.1uF

RG15

+3.3V

R4 100

C8 0.1uF

0

D

Manual Reset

MCLR\_1

MCLR\

NL R3

1

MPLAB ICD2 Connector


Lalit Patnaik

Page1.pdf 5

4

3

2

1

Analog Input from Sensors (with required signal conditioning)

R20 82k

R21 220k

R26 100k

R27 100k +3.3V

D

C21 1nF

J5 Uin from 1 Cipos Board -> TTC J6 Uout to Motor TTC J8

63/104

Wout to Motor

NTC

FUSE

L1

t

F1

1 2 3

3 1 D

B MUR860

1 2

J9

~

SCK 104

D4

-5V

1 2 3 4 5 6 7 8

N

PMC3 AC Mains

+

-

~

C31 0.47uF

BR606

16 15 14 13 12 11 10 9

R72 5.6k

L15C L15B L15A L5B L5A

D

D6

2N2907 Q3

P MUR860

L3.3

BOOST INDUCTOR

Q1 FCP11N60

GATE

R71 6.8k

C32 220uF

P

R56 390k

R59 33k

R57 390k

R76 390k

2

L1 RS

D5 Power LED

On Indicator (RED)

R61 390k

C

R67 3.9k

B

R69 820

0 R70 820

RS

R58 33k

1

Q2 2N2222 R68

PFC Controller Circuit

A

3

N R55 0.25

L1

R73 12k


Lalit Patnaik

Page3.pdf 5

R62 390k

N

C

+/-5V supply for current sense & signal conditioning circuits

R77 22k

D17 1N4001

U9

1 2 3 4

D11 L15A C34 0.1uF

C33 220uF

A

U12 UA7805

RS R63 12k

R64 33k

UC3853

+5V

1 2 3

64/104

1N4148

5 6 7 8

D14 J10

1 2 3

D10

3 2 1

D8 1N5817

1N4148 +3.3V

C47 10uF

C48 0.1uF

R66 22k

BZX84C15 GATE

D9 1N5817

C37 68pF

R65 22k

C50 0.1uF

J11

C35 0.47uF C38 680pF

D21 1N4001

-> To Cipos Board

P

1 TTC C36 3.3uF

J12 N

1

U13 UA7805

15V supply for ISO124 Isolation Amplifer (secondary side) & gate drive circuit on Cipos Board

U11 UA7815

+15Vb

D12 L15B

L5B 1N4148 C51 10uF

C52 0.1uF

C53 10uF

C54 0.1uF -5V

1 2 3

U10 UA7815

1 2 3

D19 1N4001

D15

+15Vc

D13

A

L15C 1N4148

1N4148

June 9, 2009

C39 10uF

C40 0.1uF

C41 10uF

C42 0.1uF

C43 10uF

C44 0.1uF

C45 10uF

C46 0.1uF

Title dsPIC Board: Sheet-3

N

Size B Date: 5

4

3

2

Figure 14.3: OrCAD schematic for dsPIC board: page-3

Document Number dsPIC3 Tuesday, May 12, 2009

Author: LALIT PATNAIK, M.Tech CEDT Sheet 1

1

of

1

Rev 1.1


D20 1N4001

D22 1N4001

1 2 3

15V supply for ISO124 Isolation Amplifer (primary side)

B

D18 1N4001

TTC

A

C49 10uF

PMC3

R60 15

B

L5A

+15Vc

4

3

2

1

Bleeder Circuit (Brake Chopper) for DC Link D

D

P J13 1 TTC +15Vb


Lalit Patnaik

Page4.pdf 5

BLEEDER RESISTOR

J14 1 TTC

C55 0.1uF

U14

C

C56 1uF

1 2 3 4 5

BLEED

Q4 FCP11N60 C

65/104

MCP1402 Gate Driver

R74 15

D16 3 2 1

N

BZX84C15

B

B

A

Title dsPIC Board: Sheet-4 Size A Date: 5

4

3

Document Number dsPIC4

Tuesday, May 12, 2009 2

Figure 14.4: OrCAD schematic for dsPIC board: page-4

Rev 1.1

Author: LALIT PATNAIK, M.Tech CEDT Sheet

1

of 1

1


June 9, 2009

A

14.2. PCB layout

14.2


PCB layout

The figures on the following pages show the different layers of the dsPIC board OrCAD layout. Figures 14.5 and 14.6 show the layout of the TOP and BOTTOM routing layers. Figures 14.7 and 14.8 show the GND and POWER planes. The GND plane contains two split planes. The POWER plane contains five split planes. There are no planes under the high power tracks effectively making that portion of the board a two-layer board. Figures 14.9 and 14.10 show the Silk-Screen Top and Silk-Screen Bottom layers. Figure 14.11 shows the Drill layer with the drill chart. Figures 14.12 and 14.13 show the Solder-Mask Top and Solder-Mask Bottom layers.

Figure 14.5: OrCAD Layout for dsPIC board: TOP routing layer

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June 9, 2009


14.2. PCB layout

Figure 14.6: OrCAD Layout for dsPIC board: BOTTOM routing layer

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June 9, 2009

14.2. PCB layout


Figure 14.7: OrCAD Layout for dsPIC board: GND plane layer

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June 9, 2009


14.2. PCB layout

Figure 14.8: OrCAD Layout for dsPIC board: POWER plane layer

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June 9, 2009

14.2. PCB layout


Figure 14.9: dsPIC board: SST layer

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June 9, 2009


14.2. PCB layout

Figure 14.10: dsPIC board: SSB layer

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June 9, 2009

14.2. PCB layout

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June 9, 2009

Figure 14.11: dsPIC board: DRD layer with drill chart


14.2. PCB layout

Figure 14.12: dsPIC board: SMT layer

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June 9, 2009

14.2. PCB layout


Figure 14.13: dsPIC board: SMB layer

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June 9, 2009


14.2. PCB layout

Figure 14.14: Photograph of the asssembled dsPIC board

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June 9, 2009

14.3. Connector Details

14.3


Connector Details

Table 14.1 enlists all the connectors used on the dsPIC board. Tables 14.2 to 14.8 give the pin details of the various connectors. FASTON Tabs are provided for connecting the high power inputs and outputs on the board. The tabs J5-J8 are for the motor winding currents to be sensed on the dsPIC board. J11 and J12 constitute the DC link output to the CiPoS board. J13 and J14 are meant for connecting the bleeder resistor. Ref. J1

Type 6-pin RJ-11

J2

6-pin Bergstrip

J3

2-pin Combicon

J4 J5 J6 J7 J8 J9

7-pin Relimate FASTON Tab FASTON Tab FASTON Tab FASTON Tab 3-pin Combicon

J10 J11 J12 J13 J14 J15

3-pin Combicon FASTON Tab FASTON Tab FASTON Tab FASTON Tab 2-pin Relimate

Description ICD2 Debugging / Programming Interface PICkit2 Programming Interface Auxiliary Supply for dsPIC Max +6V PWM outputs and fault input Uin from CiPoS board Uout to motor Win from CiPoS board Wout to motor Single phase AC input (Earth pin is unsused) DC supplies to CiPoS board DC link to CiPoS board To bleeder resistor DAC output for debugging

Table 14.1: dsPIC Board Connectors Pin No. 1 2 3 4 5 6

Pin Name MCLR\ 1 +3.3V GND PGD PGC -

Table 14.2: J1: 6-pin RJ-11 connector The 6-wire CAT-5 cable to be used between the ICD2 debugger and the target board is shown in Figure 14.15. Note the difference between the cables used for the evaluation board (Explorer16) and the present dsPIC board. The orientation of the end connectors shown in figure 14.15 assumes no twists in the cable.

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June 9, 2009


14.3. Connector Details Pin No. 1 2 3 4 5 6

Pin Name PGC PGD GND +3.3V MCLR\ 1

Table 14.3: J2: 6-pin Bergstrip connector Pin No. 1 2

Pin Name +5V GND

Table 14.4: J3: 2-pin Combicon connector Pin No. 1 2 3 4 5 6 7

Pin Name PWM1H PWM2H PWM3H PWM1L PWM2L PWM3L FLT CIPOS\

Table 14.5: J4: 7-pin Relimate connector Pin No. 1 2 3

Pin Name Line Neutral Earth

Table 14.6: J9: 3-pin Combicon connector Pin No. 1 2 3

Pin Name +15V +3.3V GND

Table 14.7: J10: 3-pin Combicon connector Pin No. 1 2

Pin Name DAC VOUTA DAC VOUTB

Table 14.8: J15: 2-pin Relimate connector Lalit Patnaik

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June 9, 2009

15cm



For use with the evaluation board For use with the dsPIC board

Figure 14.15: 6-wire cable for RJ-11 socket: ICD2 Debugging/Programming Interface

14.4

Bill of Materials

Item No. 1

Qty 3

2

2

3 4 5 6

1 1 1 3

7

9

8 9

1 9

10

4

Lalit Patnaik

Ref. R1 R3 R68 R4 R15 R5 R6 R7 R8 R10 R13 R9 R11 R14 R42 R43 R46 R47 R53 R54 R12 R16 R17 R22 R23 R28 R29 R34 R35 R50 R18

RESISTORS Component 0Ω 0Ω 0Ω 100Ω 100Ω 4.7kΩ 1kΩ 47kΩ 10kΩ 10kΩ 10kΩ 470Ω 470Ω 470Ω 470Ω 470Ω 470Ω 470Ω 470Ω 470Ω 1MΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ 3.3kΩ, 1% 82kΩ 78/104

Type/Package SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 SMD, 0805 June 9, 2009


11

4

12

8

13

4

14

5

15 16

1 3

17 18

1 2

19 20

1 3

21

5

22

2

23

2

24

1

Lalit Patnaik

14.4. Bill of Materials R20 R30 R32 R19 R21 R31 R33 R24 R25 R26 R27 R36 R37 R38 R39 R40 R44 R51 R71 R41 R45 R52 R63 R73 R64 R65 R66 R77 R67 R69 R70 R72 R48 R49 R75 R56 R57 R61 R62 R76 R58 R59 R60 R74 R55

82kΩ 82kΩ 82kΩ 220kΩ 220kΩ 220kΩ 220kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 6.8kΩ 6.8kΩ 6.8kΩ 6.8kΩ 12kΩ 12kΩ 12kΩ 12kΩ, 1% 12kΩ 33kΩ, 1% 22kΩ 22kΩ 22kΩ 3.9kΩ 820Ω 820Ω 5.6kΩ 150kΩ, 1% 150kΩ, 1% 150kΩ, 1% 390kΩ 390kΩ 390kΩ, 1% 390kΩ, 1% 390kΩ, 1% 33kΩ 33kΩ 15Ω 15Ω 0.25Ω, Wire wound

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SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, TH

0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206

June 9, 2009

14.4. Bill of Materials 25

Chapter 14. dsPIC Board 1

1

31

2

9

3

4

Lalit Patnaik

NTC

C1 C2 C3 C4 C5 C6 C8 C9 C10 C11 C12 C17 C19 C22 C24 C34 C40 C42 C44 C46 C48 C50 C52 C54 C55 C59 C60 C61 C62 C63 C64 C7 C39 C41 C43 C45 C47 C49 C51 C53 C13

SCK 105, 10Ω, 5A NTC Thermistor CAPACITORS 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 0.1uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 10uF, 25V 22pF, 25V

80/104

TH

SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD,

0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805

June 9, 2009


4

2

5

3

6

3

7 8 9 10 11

1 1 1 1 3

12

2

14.4. Bill of Materials C14 C15 C16 C21 C23 C25 C27 C29 C26 C28 C30 C35 C36 C37 C38 C56 C57 C58 C18 C20

12

1

C32

13

1

C33

14

1

C31

1

3

DN1

DN2

DN3

2

2

3

2

4

1

D1 D5 D2 D3 D4

5

2

D6

Lalit Patnaik

22pF, 25V 22pF, 25V 22pF, 25V 1000pF, 25V 1000pF, 25V 10nF, 25V 10nF, 25V 10nF, 25V 22nF, 25V 22nF, 25V 22nF, 25V 0.47uF, 25V 3.3uF, 25V 68pF, 25v 680pF, 25V 1uF, 25V 1uF, 25V 1uF, 25V 47uF, 25V, Al Electrolytic 47uF, 25V, Al Electrolytic 220uF, 450V, Al Electrolytic 220uF, 50V, Al Electrolytic 0.47uF, 400V, Polyester DIODES SDM40E20LS/BAT54S, 2 Schottky Diodes in series SDM40E20LS/BAT54S, 2 Schottky Diodes in series SDM40E20LS/BAT54S, 2 Schottky Diodes in series Green LED Red LED 1N4934 1N4934 BR608, 6A, 600V Bridge Rectifier MUR860

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SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, SMD, TH

0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805

TH TH TH TH

SMD, SOT23

SMD, SOT23

SMD, SOT23

TH TH TH TH TH TH, TO220AC

June 9, 2009



6

2

7

2

8

5

9

6

D7 D8 D9 D10 D16 D11 D12 D13 D14 D15 D17 D18 D19 D20 D21 D22

1

2

2

1

Q1 Q4 Q2

3

1

Q3

1 2 3

1 1 2

4 5

1 2

6 7 8

1 1 2

9

2

10

1

1 2 3

Lalit Patnaik

MUR860 1N5818 1N5818 BZX84C15 BZX84C15 1N4148 1N4148 1N4148 1N4148 1N4148 1N4001 1N4001 1N4001 1N4001 1N4001 1N4001 TRANSISTORS MOSFET, FCP11N60 MOSFET, FCP11N60 BJT(NPN), 2N2222/BC817 BJT(PNP), 2N2907/BC807

TH, TO220AC TH, DAX2/DO41 TH, DAX2/DO41 SMD, SOT23 SMD, SOT23 TH, DO35 TH, DO35 TH, DO35 TH, DO35 TH, DO35 TH, DO41 TH, DO41 TH, DO41 TH, DO41 TH, DO41 TH, DO41

TH, TO220AB TH, TO220AB SMD, SOT23 SMD, SOT23

INTEGRATED CIRCUITS U1 dsPIC33FJ256MC710 SMD, TQFP100 14x14 U2 LM1117/TC2117 3.3V SMD, SOT223 U3 ACS712 SMD, SOIC8 U4 ACS712 SMD, SOIC8 U5 ISO124 TH, DIP U6 TL084 / TS914 SMD, SOIC14 U7 TL084 / TS914 SMD, SOIC14 U8 AD5343 12bit DAC SMD, TSSOP20 U9 UC3853 SMD, SOIC8 U10 UA7815 SMD, TO263AA U11 UA7815 SMD, TO263AA U12 UA7805 SMD, TO263AA U13 UA7805 SMD, TO263AA U14 MCP1402 SMD, SOT-23-5

CONNECTORS, SWITCHES & CRYSTALS 1 F1 Fuse holder TH 1 J1 RJ11 (6-pin) socket TH 1 J2 6-pin Berg Strip TH

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14.5

4

3

5 6

1 2

7 8 9

1 1 8

10

1

11

3

12 13 14

1 1 1

14.5. Corrections in dsPIC board TP1 TP2 TP3 J3 J9 J10 J15 J4 J5 J6 J7 J8 J11 J12 J13 J14 L1

1-pin of Berg Strip TH 1-pin of Berg Strip TH 1-pin of Berg Strip TH 2-pin Combicon Conn. TH 3-pin Combicon Conn. TH 3-pin Combicon Conn. TH 2-pin Relimate Conn. TH 7-pin Relimate Conn. TH FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) FASTON Tab TH (Width=6.3mm) 16-pin bobbin TH (for EE core) S1 DPST Switch TH S2 DPST Switch TH S3 DPST Switch TH S4 Power Switch, 5A TH Y1 32kHz TH Y2 8MHz TH Table 14.9: Bill of Materials for dsPIC Board

Corrections in dsPIC board

Following are the errors in the dsPIC board with the associated remedies 1. Pin-2 of combicon connector, J10 and anode of the green LED, D1 are not connected to the +3.3V power plane. Remedy: Use a jumper wire 2. The track connecting the source of the bleeder MOSFET, Q4 to net N is not wide enough for high currents Remedy: Add a jumper wire in addition to the narrow track

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14.6. PCB Testing

14.6


PCB Testing

Following are the steps to be followed for testing the functionality of the dsPIC board. 1. Testing of dsPIC mocro-controller: (a) Connect the ICD2 debugger/programmer to the RJ-11 socket (J1) of the dsPIC board using the cable shown in figure 14.15. (b) Connect an external DC supply (4.5-6V) to the Combicon connector, J3. (c) Check whether MPLAB IDE correctly identifies the device and programs it (with a simple PWM code). (d) Remove the ICD2 cable and check whether the PWM outputs (at J4) are coming as expected. 2. Testing of front-end converter: (a) Connect single phase AC supply to the Combicon connector, J9 on the dsPIC board through a variac. ˜ (b) Connect a resistive load 1000Ω on the DC link terminals, P and N (FASTON Tabs J11 and J12). (c) Gradually increase the voltage input through the variac and check that the voltage and current waveforms correspond to that for a rectifier. (d) Beyond 200V ac input, check that the UPFC controller (UC3853) comes out of undervoltage lockout and that the voltage and current waveforms are in phase with very little harmonic distortion. (e) Check that when the UPFC converter is in action, all the DC supplies (+15V, ±5V, +3.3V) are obtained as expected. 3. Testing of voltage sensing circuit: (a) Check that the UPFC is in action and the DC supply (±5V) is available (b) Measure the voltage at TP3 and check whether it is accurate (0.0073 × actual VDC ) 4. Testing of current sensing circuit: (a) Check that the UPFC is in action and the DC supply (±5V) is available (b) Pass a known current through (J5-J6) (c) Measure the voltage at TP1 and check whether it is accurate (270mV/A × actual current + DC bias of 1.65 V) (d) Repeat the above steps for the second current sensor too (current through J7-J8, measure at TP2) The dsPIC micro-controller part of the dsPIC board has been tested with a sample PWM code. MPLAB IDE correctly identifies the device and successfully programs it. The program runs as expected on power on.

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Chapter 15

Software 15.1

Tools used

Following is the summary of the software tools used: • Integrated Development Environment: MPLAB IDE v8.10 • Assembler: MPLAB ASM30 Assembler • Compiler: MPLAB C30 Compiler • Linker: MPLAB LINK30 Object Linker • Debugger / Programmer: MPLAB ICD2

15.2

Open Loop Control

15.2.1

Pseudo Code

Following is the pseudo-code of the software programmed into the flash memory of the target device for open-loop V/f control. MAIN PROGRAM: Initialize processor by setting/resetting the suitable configuration bits Store constants in program memory (Flash) Configure PLL, ADC (in DMA mode) and PWM Wait for ADC and PWM interrupts ADC INTERRUPT SERVICE ROUTINE: Read speed reference voltage from one channel of ADC Calculate the required frequency and amplitude values Saturate the amplitude if required

85

15.2. Open Loop Control

Chapter 15. Software

PWM INTERRUPT SERVICE ROUTINE: Adjust pointers for sine LUT Get value from sine LUT and scale it Move the scaled value into the PWM compare register

15.2.2

Assembly Code

Following is the dsPIC33F assembly code (with descriptive comments) that implements the above pseudo code. ;********************************************************************** ; V/f Control of Single Phase Induction Motor (Open Loop) ; Author: Lalit Patnaik ; Date : 27th May 2009 ;***********************************************************************/

;****************************************************************************** ; Notes: * ; ====== * ; The A/D is enabled to sample one port on the Explorer 16 Developer’s * ; Board 100 PIN connected to AN5 (R6 potentiometer is used to vary the * ; frequency). * ;****************************************************************************** .equ __33FJ256MC710, 1 .include "p33FJ256MC710.inc" .global __reset ;.............................................................................. ; Configuration bits: ;.............................................................................. config __FBS, RBS_NO_RAM & BSS_NO_FLASH & BWRP_WRPROTECT_OFF ; no boot RAM ; no Boot sector and ; write protection disabled config __FSS, RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF ; no secure RAM ; no secure segment ; write protection disabled config __FOSCSEL, IESO_ON & FNOSC_PRIPLL ; The chip is started using FRC then switch Lalit Patnaik

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15.2. Open Loop Control ; to XT w/ PLL

config __FWDT, FWDTEN_OFF

;Turn off Watchdog Timer

config __FGS, GSS_OFF & GCP_OFF & GWRP_OFF ;Set Code Protection Off for the ;General Segment config __FOSC, FCKSM_CSDCMD & OSCIOFNC_OFF & POSCMD_XT ; clock switch & monitoring disabled ; remapable I/O enabled ; OSC2 pin is clock O/P ; oscilator is XT config __FPOR, PWMPIN_ON & HPOL_ON & LPOL_ON & FPWRT_PWR128 ; PWM mode is Port registers ; PWM high & low active high ; alternate I2C mapped to SDA1/SCL1 ; FPOR power on reset 128ms ;.............................................................................. ; Uninitialized variables in Near data memory ;.............................................................................. .section .nbss,bss,near ; This variable is added to the 16-bit sine wave table pointer at each ; PWM period. A value of 246 will provide 60 Hz modulation frequency ; with 16 KHz PWM Frequency: .space 2 ; 2 bytes reserved ; This variable is used to set the modulation amplitude and scales the ; value retrieved from the sine wave table. Valid values range from 0 ; to 32767 Amplitude: .space 2 ; 2 bytes reserved ; This variable is the pointer to the sinewave table. It is incremented ; by the value of the Frequency variable at each PWM interrupt. Phase: .space 2 ; 2 bytes reserved ;.............................................................................. ; Uninitialized variables in DMA RAM memory ;.............................................................................. .section .dmaram,bss,address(0x7800) ; dma_pot_read is uninitialized at start of DMA RAM i.e. 0x7800 dma_pot_read: .space 2 ; 2 bytes reserved

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;.............................................................................. ; Constants stored in Program space ;.............................................................................. .section .const,psv .align 256 ; This is a 64 entry sinewave table covering 360 degrees of the ; sine function. These values were calculated using Microsoft ; Excel and pasted into this program. SineTable: .hword 0,3212,6393,9512,12539,15446,18204,20787,23170,25329 .hword 27245,28898,30273,31356,32137,32609,32767,32609,32137,31356,30273,28898 .hword 27245,25329,23170,20787,18204,15446,12539,9512,6393,3212,0,-3212,-6393 .hword -9512,-12539,-15446,-18204,-20787,-23170,-25329,-27245,-28898,-30273 .hword -31356,-32137,-32609,-32767,-32609,-32137,-31356,-30273,-28898,-27245 .hword -25329,-23170,-20787,-18204,-15446,-12539,-9512,-6393,-3212

;.............................................................................. ; Constants stored in Program space ;.............................................................................. ; ACIM V/Hz parameter ; if ACIM has 230V and 50Hz then V/Hz const = 230/50 = 4.6 ; then constant is 4.6 * 0.244140625 * 256 / max_volt ; max_volt = 0.244140625*256*4.6 ; So, V/Hz constant = 1 .equ ACIM_V_per_Hz_const, 0x7FFF

; ; ; ;

; This constant is used to scale the sine lookup value to the valid range ; of PWM duty cycles. This is based on the value written to PTPER. We will ; use PTPER = 1250 for this application, which allows duty cycles between 0 and ; 2500. The sine table data is signed, so we will multiply the table data ; by 1250, then add a constant offset to scale the lookup data to positive ; values PWM frquency = 40 / (2 x 1250) MHz = 16 kHz *** For 10kHz PWM frequency, use PWM_Scaling = 2000 *** *** PWM frequency = 40 / (2 x 2000) MHz = 10 kHz *** *** The factor 2 appears because the carrier is triangular (up-down counter) instead of sa .equ PWM_Scaling, 1250

; The pointer to the sign wave table is 16 bits. Adding 0x5555 to the ; pointer will provide a 120 degree offset and 0xAAAA will give a 240 ; degree offset. These offsets are used to get the lookup values for ; phase 2 and phase 3 of the PWM outputs. .equ Offset_120, 0x5555 .equ Offset_60, 0x2AAA Lalit Patnaik

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;.............................................................................. ; Code Section in Program Memory ;.............................................................................. .text __reset: MOV MOV MOV NOP CALL

;Start of Code section #__SP_init, W15 #__SPLIM_init, W0 W0, SPLIM

;Initalize the Stack Pointer ;Initialize the Stack Pointer Limit Register ;Add NOP to follow SPLIM initialization

_wreg_init

;Call _wreg_init subroutine ;Optionally use RCALL instead of CALL

call Setup ; Call the routine to setup I/O and PWM ;-----------------------------------------------------------------------------; Variable initialization ;-----------------------------------------------------------------------------clr clr clr Phase

Frequency Amplitude

;-----------------------------------------------------------------------------; Main loop code ; The PWM interrupt flag and DMA interrupt flag are polled in the main loop ;-----------------------------------------------------------------------------Loop:

btss

IFS3,#PWMIF

; poll the PWM interrupt flag in the ; Interrupt Flag Status register3. ; PWM interrupt is generated once in

bra

CheckPOT

; if it is set, continue

call bclr

Modulation IFS3, #PWMIF

; call the sinewave modulation routine ; Clear the PWM interrupt flag

CheckPOT: btss bra

IFS0,#DMA0IF Loop

; if DMA transfer completed ; if not - go to Loop again

; 16 PWM cycles

call

ReadPOT

bra

Loop

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;-----------------------------------------------------------------------------; ADC processing subroutine ;-----------------------------------------------------------------------------; ADC interrupt => trigger DMA ; (transfer data from ADCBUF SFR to certain memory location) ; ; DMA interrupt => trigger ReadPOT sub-routine ; (transfer data from memory to computational register) ReadPOT: ; save all working registers (W0, W1, W4, W5) push.d W0 ; Push W0 and W1 to Top-Of-Stack push.d W4 ; Push W4 and W5 to Top-Of-Stack mov

dma_pot_read,W0

; Read the ADC results into W0 ; dma_pot_read is address where DMA transfered ; the value captured by ADC

bclr bclr

IFS0,#AD1IF IFS0,#DMA0IF

; clear ADC interrupt flag ; clear DMA interrupt flag

asr W0,#2,W4 ; Right shift by 2 bits to get the mov W4,Frequency ; frequency. ; ’Frequency’ denotes an 8-bit offset value ; (affects LSByte of the Sine Table Pointer i.e. ’Phase’) sl W0,#5,W4 ; Left shift W0 to get a Q15 value ; Note that this value is always +ve and less than 1 mov #ACIM_V_per_Hz_const,W5 mpy W4*W5,A ; multiply frequency by V/Hz gain to get sac A,W0 ; mod. amplitude. Store result in W0 ; NOTE: No need for any shifts as Multiplication is in ; fractional mode by default and the operands are in Q15 format mov #28000,W1 cp W1,W0 bra GE,NoLimit mov W1,W0 ; Flatten the ; NOTE: 28000/32767 = 85.45% NoLimit: mov W0,Amplitude pop.d pop.d

; Limit modulation amplitude to avoid ; dead-time induced distortion in PWM ; modulation. V/f profile

W4 W0

return Lalit Patnaik

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;-----------------------------------------------------------------------------; PWM sine wave modulation subroutine ;-----------------------------------------------------------------------------Modulation: push.d W0 ; Save off working registers push.d W2 push.d W4 push.d W6 push.d W8 push.d W10 push.d W12 ; The next three instructions initialize the TBLPAG and pointer register ; for access to the sinewave data in program memory using table reads. mov mov mov

#tblpage(SineTable),W0 W0,TBLPAG #tbloffset(SineTable),W0

; The next block of instructions loads various constants and variables ; used in the sinewave modulation routine.

mov

mov Phase,W1 ; Load the sinewave table pointer mov #Offset_120,W4 ; This is the value for a 120 degree offset #Offset_60,W12 ; This is the value for a 60 degree offset mov Amplitude,W6 ; Load the Amplitude scaling factor mov #PWM_Scaling,W7 ; Load the PWM scaling value mov Frequency,W8 ; Load the Frequency constant that will ; be added to the table pointer at each ; interrupt. ; ; ; ; ; ; ;

This is the pointer adjustment code. The Frequency value is added to the sine pointer to move through the sine table. Then, offsets are added to this pointer to get the phase 2 and phase 2 pointers. Note: If different phase offsets are desired, other constant values can be used here. Add 0x4000 to get a 90 degree offset, 0x8000 will provide a 180 degree offset. Here, 0x5555 has been loaded to W4 to provide 120 degrees.

add add add

W8,W1,W1 W1,W12,W2 W2,W4,W3

; Add the Frequency value to the sine pointer ; Add 60 degree offset value for phase 2 ; Add another 120 degree offset for phase 3

; The sine table has 64 entries, so the pointers are right shifted ; to get a 6-bit pointer value. lsr Lalit Patnaik

W1,#10,W9

; Shift the phase 1 pointer right to get the upper 6 bit 91/104

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15.2. Open Loop Control sl lsr sl lsr sl ; ; ; ; ;

W9,#1,W9 W2,#10,W10 W10,#1,W10 W3,#10,W11 W11,#1,W11

Chapter 15. Software ; ; ; ; ;

Left shift by one Shift the phase 2 Left shift by one Shift the phase 3 Left shift by one

to convert to pointer right to convert to pointer right to convert to

byte address to get the upper 6 bit byte address to get the upper 6 bit byte address

Now, the pointer for each phase is added to the base table pointer to get the absolute table address for the lookup value. The lookup value is then scaled for the correct amplitude and for the range of valid duty cycles. The next block of instructions calculates the duty cycle for phase 1. The phase 2 and phase 3 code is the same.

add tblrdl mpy sac mpy sac add mov

W0,W9,W9 [W9],W5 W5*W6,A A,W5 W5*W7,A A,W8 W7,W8,W8 W8,PDC1

; ; ; ; ; ; ; ;

Form the table address for phase 1 Read the lookup value for phase 1 Multiply by the amplitude scaling Store the scaled result Multiply by the PWM scaling factor Store the scaled result Add the PWM scaling factor to produce 50% offset Write the PWM duty cycle

; The next block of code calculates the duty cycle for phase 2. add tblrdl mpy sac mpy sac add mov


; ; ; ; ; ; ; ;


; The next block of code calculates the duty cycle for phase 3. add tblrdl mpy sac mpy sac add mov


; ; ; ; ; ; ; ;


; Now, save off the adjusted sinewave table pointer so it can be ; used during the next iteration of this code. mov

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W1,Phase

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Chapter 15. Software pop.d


W12 ; restore working registers pop.d W10 pop.d W8 pop.d W6 pop.d W4 pop.d W2 pop.d W0 return

; return from the subroutine

;-----------------------------------------------------------------------------; PWM and ADC setup code ;-----------------------------------------------------------------------------Setup: ; setup Fcy at 40MIPS i.e. ; external osc is 8MHz mov #0x3000,W0 mov W0,CLKDIV mov #0x0026,W0 mov W0,PLLFBD

Tcy = 25ns ; ; ; ;

setup of PLLPRE & PLLPOST N1=N2=2 setup of PLLDIV M=40

; wait for PLL lock Lock_loop: btss OSCCON,#LOCK ; wait for PLL lock status bit in Oscillator Control Register bra Lock_loop

; Setup the DMA ;************************************************************************** ; The DMA Channel 0 is configured to transfer data from ADCBUF0 to a ; certain set of RAM locations starting from 0x0000. A DMA interrupt is ; generated whenever one DMA tranfer occurs. mov #0x8000,W0 ; set configuration for DMA channel 0 mov W0,DMA0CON ; DMA channel control register ; ref. datasheet pg.129 mov #0x000D,W0 ; set interrupt request from ADC mov W0,DMA0REQ ; DMA channel IRQ select register ; ref. datasheet pg.130 ; *** SET DMA DESTINATION ADDRESS *** mov #0x0000,W0 ; set DMA RAM start address mov W0,DMA0STA ; DMA RAM Primary Start Address Offset register ; ref. datasheet pg.131

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; *** SET DMA SOURCE ADDRESS *** mov #0x0300,W0 ; set Peripheral address to ADC1BUF0 SFR mov W0,DMA0PAD ; DMA Peripheral Address register ; ref. datasheet pg.46,132 mov #0x0000,W0 ; set number of DMA transfers to one (CNT+1) mov W0,DMA0CNT ; DMA Transfer Count register ; ref. datasheet pg.132 bclr IFS0,#DMA0IF ; ref. datasheet pg.88

; clear DMA interrupt flag

; Setup the ADC ; ref. datasheet pg.249 ;************************************************************************** mov #0x0400,W0 ; scan input for CH0 during sample A bit mov W0,AD1CON2 ; 1 sample/convert per interrupt mov #0x0002,W0 ; Selecting the A/D conversion clock mov W0,AD1CON3 ; Tad = 3*Tcy = 75ns ; Choose Tad = 120ns for 12-bit mode clr clr

AD1CHS123 AD1CHS0

; scan mode - no need for them ;

mov mov

#0xFFDF,W0 W0,AD1PCFGL

; only AN5 pins analog mode, others are in digital mode

clr AD1CSSL ; clear CSSL bits. Input scan select register bset AD1CSSL,#5 ; set for scanning only AN5 ; No need to configure CSSH bits unless AN16-31 are used mov mov

#0x8066,W0 W0,AD1CON1

; enable A/D, PWM trigger, auto sample ; integer format

bclr

IFS0,#AD1IF

; clear A/D interrupt flag

; Now, setup the PWM registers ; ref. datasheet pg.163 ;************************************************************************** mov mov

#0x0077,W0 W0,PWMCON1

mov mov

#0x0068,W0 ; 2usec deadtime at 40 MIPS W0,DTCON1 ; Dead Time Control Register

mov mov

#PWM_Scaling, W0 ; set period for 16KHz PWM at 40 MIPS W0,PTPER ; PWM Time Base Period Register

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; complementary mode, #1, #2, and #3 ; pairs are enabled

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Chapter 15. Software mov mov


#0x0F00,W0 W0,PWMCON2

; set the special event postscaler to 1:16 ; Generate interrupt after every 16 PWM cycles

mov #0x8002,W0 ; PWM timebase enabled, center aligned mode mov W0,PTCON ; PWM time base control register ; double PWM updates may be used for increasing control Bandwidth return

; return from the Setup routine

;.............................................................................. ; Subroutine: Initialization of W registers to 0x0000 ;.............................................................................. _wreg_init: CLR W0 MOV W0, W14 REPEAT #12 MOV W0, [++W14] CLR W14 RETURN ;--------End of All Code Sections --------------------------------------------.end

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;End of program code in this file

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Chapter 16

System Wiring Figure 16.1 on the following page shows the complete system wiring diagram. For further clarifications on pin numbers and pin names, refer the sections on connector details for each board (section 13.3 for CiPoS board and section 14.3 for dsPIC board).

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Lalit Patnaik

97/104 Relimate (J15)

RJ-11 (J1)

Bergstrip (J2)

Combicon (J3)

Combicon (J9)

dsPIC Board

DAC Outputs for debugging

ICD2 Debugging / Programming Interface

PICkit2 Programming Interface

Auxiliary Supply for dsPIC

Single Phase AC Power Input

+15V and +3.3V DC Supplies

PWM & Fault Signals

DC Link

Combicon (J22)

Relimate (J24)

FASTON (P) FASTON (N)

FASTON (U)

FASTON (J14)

FASTON (J13) BLEEDER

FASTON (J8)

FASTON (J7)

FASTON (J6)

FASTON (J5)

Combicon (J10)

Relimate (J4)

FASTON (J11) FASTON (J12)

FASTON (W) MAIN AUX.

Chapter 16. System Wiring

CiPoS Board FASTON (V)

1-Phase motor used as 2-phase motor

LEGEND:

High Power Lines Low Power Lines Signal Lines

Figure 16.1: System Wiring Diagram

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Chapter 17

Experimental Results The CiPoS board has been tested with star-connected lamp load (up to 700W) and with 3-phase as well as single-phase motor load with suitable PWM inputs drawn from micro-controller. The dsPIC micro-controller part of the dsPIC board has been tested with a sample PWM code. MPLAB IDE correctly identifies the device and successfully programs it. The program runs as expected on power on. The unity power factor converter has been tested on a general purpose board for light loads. For higher load currents, instability sets in. Complete system integration was still in progress at the time of writing this report.

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Appendix A

UPFC Design M-code Following is the MATLAB code for the design of the circuit element values in a unity power factor converter circuit using UC3853 % Design of Boost PFC using UC3853. This is based on UNITRODE’s application % note U-159.

clc format short e; muo = 4 * pi * 1e-7; % SPECIFICATIONS Po = 460; % output power, watts eff = 0.9; % Efficiency Pin = Po/eff; Vinmin = 200; % minimum input rms voltage, volts Vinmax = 250; % maximum input rms voltage, volts fl = 50; % line frequency, hertz flmin = 47; Vo = 400; % Output voltage,volts fs = 75e3; % switching frequency, hertz % fs = 75 kHz for UC3853 Vomin = 380; % min. o/p voltage at which load can work, volts %INDUCTOR VALUE Ipk = sqrt(2)*Pin/Vinmin; % max. peak line current di = 0.2*Ipk; % ripple current D = (Vo - sqrt(2)*Vinmin)/Vo; % duty factor at Ipk when input peak % under low line conditions L = Vinmin*sqrt(2)*D/(fs*di); % Inductor value fprintf(1,’\n\n%s %e\n’,’Calculated value, L,H = ’,L); L=input(’Choose the practical inductor value, L, H = ’); %OUTPUT CAPACITOR VALUE [No hold time requirement] 99

Chapter A. UPFC Design M-code Co = 0.2e-6*Po; fprintf(1,’\n\n%s %e\n’,’Calculated value, Co,F = ’,Co); Co=input(’Choose the practical capacitor value, Co, F = ’); %MOSFET and DIODE ratings of BOOST converter Vds = Vo; % Vds rating > Vo Ids = Ipk+(di/2); % Ids rating > Ids calculated PIV = Vo; % PIV > Vo Id = Ids; % Id > Ids calculated % CONTROLLER CIRCUIT DESIGN BASED ON 3854 % SENSE RESISTOR VALUE Vrs=1; % CHOOSE - sense voltage across current sense resistor Ipkmax=Ipk+(di/2); Rs = Vrs/Ipkmax; % sense resistor value fprintf(1,’\n\n%s %e\n’,’Sense resistor calculated value, Rs,ohms = ’,Rs); Rs = input(’Choose the practical sense resistor value, Rs, ohms = ’); Vrs = Rs*Ipkmax; % recalculated sense voltage pRs = Ipkmax*Ipkmax*Rs; %power dissipation in Rs % Rac SELECTION Vpkmax=sqrt(2)*Vinmax; % divide by maximum multiplier input current = 500 micro amps. Rac=Vpkmax/500e-6; fprintf(1,’\n\n%s %e\n’,’Calculated value, Rac,ohms = ’,Rac); Rac=input(’Choose the practical resistor value, Rac, ohms = ’); % CURRENT ERROR AMPLIFIER (CEA) COMPENSATION % The amplifier gain at the switching frequency has to be slope compensated. % The voltage across the sense resistor due to maximum downslope of the inductor % current which occurs when Vin=0 has to be used for current loop stability. % At Vin=0, D=0 so the voltage across L is Vo for (1-D)/fs i.e. 1/fs period. dVrs = Vo*Rs/L/fs; Vosc = 5; Gca = Vosc/dVrs; %gain at the switching frequency Rmo = 3.9e3; Rcz = Gca*Rmo; fprintf(1,’\n\n%s %e\n’,’Calculated value, Rcz,ohms = ’,Rcz); Rcz = input(’Choose the practical resistor value, Rcz, ohms = ’); fci = (Vo*Rs*Rcz)/(Vosc*2*pi*L*Rmo); %current loop crossover frequency Cczmin = 1/(2*pi*fci*Rcz); %for 45deg. phase margin-choose zero at fci fprintf(1,’\n\n%s %e\n’,’Calculated value, Cczmin,F = ’,Cczmin); Ccz = input(’Choose the practical capacitor value, Ccz, F = ’); Ccpmax = 1/(2*pi*fs*Rcz); %choose pole above fs/2 fprintf(1,’\n\n%s %e\n’,’Calculated value, Ccpmax,F = ’,Ccpmax); Ccp=input(’Choose capacitor value less than calculated value, Ccp, F = ’);

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Chapter A. UPFC Design M-code % VOLTAGE ERROR AMPLIFIER (VEA) COMPENSATION % Rvi = Rvd((Vo/Vfb)-1) Rvi = input(’Choose Rvi value, Rvi, ohm = ’); Rvd = input(’Choose Rvd value, Rvd, ohm = ’); Gvd = 3/Vo; fr = 2*flmin; % second harmonic frequency at flmin Vopk = Pin/(2*pi*fr*Co*Vo); % output peak to peak ripple dVcomp = 4.5; ripple=2.5/100; %percent ripple allowed at the amplifier output Gv = dVcomp*ripple/Vopk; Gvea = Gv/Gvd; %gain at the second harmonic frequency? gm = 485e-6; Cvc = gm/(2*pi*fr*Gvea); fprintf(1,’\n\n%s %e\n’,’Calculated value, Cvc,F = ’,Cvc); Cvc=input(’Choose capacitor value less than calculated value, Cvc, F = ’); fvi=sqrt(Pin*gm*Gvd/(dVcomp*Vo*Co*Cvc*2*pi*2*pi));%unity gain freq. of voltage loop Rvc=1/(2*pi*fvi*Cvc); fprintf(1,’\n\n%s %e\n’,’Calculated value, Rvc,ohms = ’,Rvc); Rvc=input(’Choose the practical resistor value, Rvc, ohms = ’); Cvczmin = 4*Cvc; fprintf(1,’\n\n%s %e\n’,’Calculated value, Cvczmin,F = ’,Cvczmin); Cvcz=input(’Choose capacitor value more than calculated value, Cvcz, F = ’); %FEEDFORWARD VOLTAGE DIVIDER CAPACITORS Vff = 12; THD = 2/100; % percent Vr = pi*Vff*THD; Iff = 0.015; Cffmin = Iff/(2*Vr*flmin); fprintf(1,’\n\n%s %e\n’,’Calculated value, Cffmin,F = ’,Cffmin); Cff=input(’Choose the practical capacitor value, Cff, F = ’); tdelay = 0.75; % time taken to charge Cff to Vff Rb = tdelay*sqrt(2)*Vinmin/(Vff*Cff); fprintf(1,’\n\n%s %e\n’,’Calculated value, Rb,ohms = ’,Rb); Rb = input(’Choose the practical resistor value, Rb, ohms = ’); Ibias = Vinmax*sqrt(2)*2/(pi*Rb); % Ibias should be less than 15mA %DESIGN OUTPUTS clc;

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Chapter A. UPFC Design M-code id(1)=1;%for standard output i.e. the screen id(2)=fopen(’I:\LALIT_PROJECT\FEC\PFC\BoostPFC_UC3853_design_output.m’,’w’); for j = 1:2, fid=id(j); fprintf(fid,’%s\n\n\n’,’THE DESIGN OUTPUTS ARE AS FOLLOWS’); fprintf(fid,’%s\n\n’,’SPECIFICATIONS’); fprintf(fid,’%s %e\n’,’1. Po = ’,Po); fprintf(fid,’%s %e\n’,’2. Pin = ’,Pin); fprintf(fid,’%s %e\n’,’3. Vinmin = ’,Vinmin); fprintf(fid,’%s %e\n’,’4. Vinmax = ’,Vinmax); fprintf(fid,’%s %e\n’,’5. Vo = ’,Vo); fprintf(fid,’%s %e\n’,’6. Vomin = ’,Vomin); fprintf(fid,’%s %e\n’,’7. fl = ’,fl); fprintf(fid,’%s %e\n’,’8. fs = ’,fs); fprintf(fid,’%s %e\n\n\n’,’9. hold time,th = ’,th);

fprintf(fid,’%s\n\n’,’POWER COMPONENTS’); fprintf(fid,’%s %e\n’,’1. L = ’,L); fprintf(fid,’%s %e\n’,’2. Co = ’,Co); fprintf(fid,’%s %e\n’,’3. MOSFET, Vds = ’,Vds); fprintf(fid,’%s %e\n’,’4. MOSFET, Ids = ’,Ids); fprintf(fid,’%s %e\n’,’5. DIODE, PIV = ’,PIV); fprintf(fid,’%s %e\n\n\n’,’6. DIODE, Id = ’,Id);

fprintf(fid,’%s\n\n’,’SENSE SECTION COMPONENTS’); fprintf(fid,’%s %e %s %4.2d %s\n’,’1. Rs = ’,Rs,’

>’,pRs,’W’);

fprintf(fid,’%s\n\n’,’CURRENT fprintf(fid,’%s %e\n’,’1. Rcz fprintf(fid,’%s %e\n’,’2. Ccz fprintf(fid,’%s %e\n’,’3. Ccp

ERROR AMPLIFIER COMPENSATION’); = ’,Rcz); = ’,Ccz); = ’,Ccp);

fprintf(fid,’%s\n\n’,’VOLTAGE fprintf(fid,’%s %e\n’,’1. Rvi fprintf(fid,’%s %e\n’,’2. Rvd fprintf(fid,’%s %e\n’,’3. Rvc fprintf(fid,’%s %e\n’,’4. Cvc fprintf(fid,’%s %e\n\n\n’,’5.

ERROR AMPLIFIER COMPENSATION’); = ’,Rvi); = ’,Rvd); = ’,Rvc); = ’,Cvc); Cvcz = ’,Cvcz);

fprintf(fid,’%s\n\n’,’VOLTAGE FEEDFORWARD SECTION’); fprintf(fid,’%s %e\n’,’1. Cff = ’,Cff); fprintf(fid,’%s %e\n\n\n’,’2. Rb = ’,Rb); end fclose(id(2)); Lalit Patnaik

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Bibliography [1] Aengus Murray. Motor-control www.electronicproducts.com, 2007.

designs

maximize

appliance

efficiencies.

[2] Jonah Chen and Vijay Bolloju. Cut domestic energy with speed control. www.eetasia.com, 2007. [3] Padmaraja Yedamale. Three ways to control a single-phase induction motor. www.designnews.com, 2004. [4] Rakesh Parekh. AC Induction Motor Fundamentals. Microchip Application Note - AN887, 2003. [5] Theodore Wildi. Electrical Machines, Drives, and Power Systems. Prentice Hall International, UK, 1997. [6] Austin Hughes. Electric Motors and Drives. Elsevier Science and Technology Books, USA, 1993. [7] A E Fitzgerald, Charles Kingsley, and Stephen Umans. Electric Machinery. McGraw-Hill Education, USA, 2003. [8] Steve Bowling. How to turn an ac induction motor into a dc motor (a matter of perspective). Microchip Technology, Inc, 2007. [9] Dave Ross, John Theys, and Steve Bowling. Using the dsPIC30F for Vector Control of an ACIM. Microchip Application Note - AN908, 2007. [10] Gopal K Dubey and C Rao Kasarabada. Power Electronics and Drives. Tata McGraw Hill Publishing Company, India, 1993. [11] Unitrode. UC3853 - High Power Factor Preregulator. IC Datasheet, 2008. [12] Phillip C Todd. Boost power factor corrector design with the UC3853. Unitrode Corporation, Application Note U-159, 1999. [13] Texas Instruments. UA7800 series - positive voltage regulators. IC Datasheet, 2009. [14] Microchip. TC2117 - 800 mA fixed low dropout positive regulator. IC Datasheet, 2006. [15] Epcos AG. NTC thermistors for inrush current limiting. Application Note, 2005. [16] Padmaraja Yedamale. Bidirectional VF Control of Single and 3-Phase Induction Motors Using the PIC16F72. Microchip Application Note - AN967, 2005. 103

BIBLIOGRAPHY

BIBLIOGRAPHY

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