Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Clifford E. Cummings

SNUG-2002 Boston, MA Voted Best Paper 2nd Place

Sunburst Design, Inc. [email protected]

ABSTRACT There is a common misconception that coding sequential logic with nonblocking assignments does not simulate correctly unless a #1 delay is added to the right hand side of the nonblocking assignment operator. This is not true. This paper will explain how delays and nonblocking assignments impact the Verilog event queue. This paper will also detail both good and bad reasons for adding delays to nonblocking assignments and include guidelines for good RTL coding styles that permit mixed RTL and gate-level simulation.

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Introduction

In his book Writing Testbenches[7], Functional Verification of HDL Models, Janick Bergeron claims that VHDL and Verilog both have the same area under the learning curve[8]. Due to the misinformation that has been spread through numerous Verilog books and training courses, I am afraid Bergeron may be right. When Verilog is taught correctly, I believe the area under the Verilog learning curve is much smaller and Verilog simulations run much faster than comparable VHDL simulations. This paper details functionality and important guidelines related to nonblocking assignments and nonblocking assignments with delays. Before discussing nonblocking assignment functionality and recommendations, a quick review of the definition of nonblocking assignments is in order: A nonblocking assignment is a Verilog procedural assignment that uses the "