Versatile All-Optical Clock Recovery Circuit for OOK and DPSK Modulated Data Traffic G. Contestabile, M. Presi, N. Calabretta, A. D'Errico, E. Ciaramella Scuola Superiore Sant'Anna, via Moruzzi 1 - 56124, Pisa (Italy) Email:
[email protected] Abstract: We demonstrate the properties of an all-optical processing unit capable of clock-recovery from both OOK and DPSK modulated signals. The circuit is based on periodic sharp filtering and it is suitable for photonic integration. Independently on the modulation format, it is characterised by a tens of MHz locking range, few bits locking time and timing jitter generally below 2% of the bit time. Thanks to these features it can be employed in future optical packets switched networks.
Keywords: All-optical Clock Recovery, Fabry-Per6t Filter, Optical Packet Switching, Tuffi a Cufaniello, Photonic Integration, Burst-Receiver 1. Introduction
The synchronization issue is a serious challenge for the development of future Optical Networks, whatever it is addressed to point-to-point optical links or Optical Packet Switching (OPS) environment. As many other functions, synchronization should be performed in optical domain with the simplest possible circuit. Suitability for photonic integration and low power consumption are also important key design points. Among the various known schemes the latter features are matched by CR circuits based on selfpulsating lasers [1] and Fabry-Per6t filters (FPF) [2,3]. Self-pulsating lasers based CR circuits are suitable forBP point-to-point optical links: polarization and wavelength independent realizations have been demonstrated to this aim. Those circuits are also characterized by very long clock release times, hence being resistant to long constant-symbol sequences. However this limits their use in OPS environment where it is required a packet-bypacket burst-mode processing and it is important to minimize the inter-packets guard-time [4]. FPF-based circuits can be optimized to work in asynchronous optical packet networks (as it will be discussed in section 3). Here we experimentally demonstrate an all-optical circuit in which a FPF (assisted by a single SOA) acts as the true clock extractor: this is an important advance in respect to other circuits in which a FPF had the role of pre-processor [5]; based mainly on these components, it is suitable for photonic integration and (due to the passive nature of FPFs) for low power consumption operations. As it will be discussed in this paper (section 3), this circuit is able to recover the synchronization signal from a variety of modulation formats. Moreover, when properly designed it is suitable to be employed in OPS environments: we report here a preliminary measurement of packet-by-packet CR from pure 10Gb/s DPSK packets without preamble fields. The effectiveness of the proposed CR circuit in all-optical regenerative applications has been also recently demonstrated for RZ signals in an over-million km transmission in a re-circulating loop experiment with 3R
regeneration [6], and in a field trial transmission for NRZ signals [7]. 2. Working Principle and Results
The Fall-ptca 6C uit isPbasicllymde by fiesse F Inabsaturated ed Fitr (fig I). Theby regime(fow operated
an hih an seA proposed g tested forp RZ p and architecture for the CR (fig.g 1 ) has been NRZ data stream at 40Gb/s and for NRZ-DPSK streams
and burst data at 10Gb/s 2.1 RZ Data The working principle can be understood first considering an OOK-RZ signal. In this case, thanks to the interplay of the memory properties of an high-finesse FPF with the Free Spectral Range (FSR) matching the clock frequency and the power-limiting capability of a saturated SOA, it is possible to fill the zero slots of the incoming RZ data stream with optical pulses (fig. 1). _OOK RZ a) -----------------------
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Fig. 1 All-Optical CR architecture for different modulation formats: in the case of NRZ modulation a pre-processor is required. RZ andan NRZ-DPSK (with a proper filter direct detection se be dietly prcsed.
In case of a long zero sequence, the FPF introduces pulses with decaying intensity and thus amplitude oscillations arise; the saturated SOA that follows the FPF equalizes the pulse amplitudes [3] in order to obtain a good quality clock signal. In the frequency domain, this circuit can be understood considering the frequency response of the FPF: when the FSR matches the signal bit-rate, the FPF selects only discrete components in the spectrum of the incoming signal generating a beat at the clock frequency. The FPF Finesse (F) determines the filter selectivity, i.e., the amount of modulation removed from the incoming signal. When operated in saturated regime, the SOA acts like a pulse amplitude equalizer, or equivalently as an high-pass filter with around I GHz cutoff frequency [8]. Typical amplitude noise removal is
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All-Optical Clock Recovery Unit
shown in the insets of fig.1. Other equalizers could be employed to this end, for example a UNI switch or an SOA-Mach-Zender Integrated circuit [9,10]; however, using a single SOA the circuit implementation is simplified and is possible to operate it at lower optical power levels.
temperature controller in order to match the incoming signal wavelength. Depending on the FPF a polarization controller at circuit input may be required. We used a FPF with F=270 (150 MHz line-width) for 40Gb/s experiments and F=100 (100 MHz line-width) for the 10Gb/s experiment. Both FPFs had about 4 dB Insertion Loss. The SOA had 28 at dB200 smallmAsignal gaincurrent. and 6 Two dBm Optical output saturation power driving Isolators (01) installed at the FPF ends (see fig. 1) block spurious back-reflections from the SOA toward the FPF and from the FPF toward the incoming data. An amplifier at the circuit input compensates for the losses introduced by the FPF in order to keep the equalizing SOA in the saturated regime. A narrow optical filter at the circuit output is used to remove the ASE noise introduced by the SOA.
2.2 NRZ Data NRZ data streams cannot be directly processed by the CR unit because of the very weak clock components in the spectrum. A pre-processing stage is needed to enhance them. The pre-processing can be achieved by means of a simple circuit (fig lb) realized with an SOA and a BPF. As the NRZ signal enters this first SOA, an overshoot, with a corresponding wavelength red-shift, appears at the leading edge of data. The main non-linear effects responsible for this are Self Phase Modulation (SPM) and pattern dependent gain saturation [3]. A pseudo-return-to-zero (PRZ) signal is then obtained by the BPF, filtering every leading edge of the NRZ signal. This PRZ signal contains a sequence of pulses that can be injected into the CR unit (see fig 2). Fig 2c, shows the the clock line enhancement of about 15 dB due to the SPM experienced by the signal in the SOA. a)lp6 div
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Fig.2 a) NRZ data input streams; b) converted Pseudo-RZ signal c) Clock enhancement (about 15 dB) observed in the Electrical Spectrum
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NRZ-DPSK. In the insets, demodulated DPSK eye diagram obtained when the oscilloscope is triggered with the optical clock, and a visual comparison between CR signal and
electrical system clock. 2.3 DPSK Data In principle a NRZ-DPSK stream could be demodulated to The recovered clock showed very similar properties for all an intensity modulated signal and then sent to the prethe tested modulation formats. The timing jitter (estimated by integrating the Single Side Band spectra obtained by processing stage in order to achieve the CR. However if the DPSK signal is demodulated with a Gaussian shaped Electrical Spectrum Analyzer) was found always lower than 2% of bit time for every modulation format. The good filter (with bandwidth around 2/3 of the signal bit-rate) quality and stability of the recovered signal was confirmed realized with a reflective Fibre Bragg Grating (FBG) [11] it is possible to obtain simultaneously (and without any for the various modulation formats by using it to trigger a other processing stage) a PRZ for the CR unit (fig. lc). sampling oscilloscope and also as clock signal to error This is simply done by using the signal transmitted through detectors in Bit Error Rate (BER) measurements. This the FBG. From a physical point of view, same consecutive never showed penalties in respect to electrical CR units. As an example we report in fig. 3 results obtained in the symbols (data persistence), which correspond to spectral DPSK case. components close to the carrier, are reflected by the filter, while data transitions, which correspond to frequencies aside in the spectrum, pass almost unaffected through the grating. We highlight that the part of the signal transmitted through the FBG is composed by all the NRZ-DPSK transitions. Hence it results into a pulse at every phase transition of the incoming data and consequently the 20 ps/div )j 50 ps/div aOps/div sequence contains significant clock components. Once obtained this RZ-like signal at one FBG end it can be used to realize clock recovery, while at the other end the Fig. 4 Clock recovered signal for 40Gb/s a) RZ input stream, incoming signal is demodulated.b) NRZ input stream and c) 10Gb/s DPSK input stream.
3. General Results and Issues
In all cases the traffic was PRBS (with variable pattern lengths). The variety of experimental conditions confirms the versatility of the circuit. In the CR unit, we used commercially available fibre-based FPF: these filters are unaffected by mechanical fluctuations thus allowing very stable CR operation; moreover the FPF transfer function can be wavelength shifted by means of a stabilized
After one hour accumulation time, the eye diagram of the FBG-demodulated NRZ-DPSK signal was still completely fixed and open when using the recovered clock to trigger signal to the oscilloscope. In Fig. 3 it is also possible to observe a visual comparison between the recovered clock signal and the clock signal from a pattern generator. Fig.3 also reports a comparison of the BER curves obtained using the electrical clock from the pattern generator, an electrical clock obtained with an electrical CR unit and the
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shown in fig. 5 where it is shown a packet-by-packet CR from l0Gb/s, 128 bits-long packets without preamble field. This result was obtained by using the scheme reported in fig. lc. and a FPF with F=100. In this case, a raise time of 40 bits (400 ps) decay time of 100 bits (10 ns) is observed: this time can be shortened by choosing a FPF filter with lower Finesse at expenses of the tolerance to long '0' bits sequences. From the figure it is also possible to note that in the recovered packet it is always possible to find a region in which the clock amplitude is flat: this can be useful for successive all-optical processing operations.
optical clock signal recovered by our scheme as clock signals. No appreciable power penalty was observed among the various synchronization signals. Finally, a detail of the CR signals for each modulation format is reported in fig. 4. While the FPF FSR is fixed by the signal bit-rate the FPF Finesse determines the CR behaviour. It affects the timing jitter, the locking and the persistence times, as well as the locking-range and the CR tolerance to lasers line-widths. The locking-range (and the tolerance to the laser line-width) is proportional to the FPF line-width (given by the ratio FSR/F); lowering the Finesse increases the CR unit tolerance to signals bit-rate and carriers wavelength instabilities. The same beneficial effect can be observed at higher bit-rates (at same F values). The relationship between lock-in and persistence times and the Finesse can be understood approximating the traffic with averaged amplitude: in this case the FPF acts exactly like a first-order low-pass filter. It responds to a square wave with a time constant t given by: [1] F 2I FSR Thus the lock-in time can be shortened lowering the Finesse. Eq [1] also gives information about the CR unit tolerance to long sequences of constant symbols in the input signal: it increase with the Finesse. The Finesse should be kept to reasonable high values, in order to remove the more modulation is possible from the incoming signal. The best Finesse value is obtained with a trade-off and depends on the application: higher values are suitable for continuous traffic streams, while smaller values should be chosen for burst data. Due to the presence of the amplitude-equalizing SOA the time constant X introduced in eq. 1 is effectively "shortened"; the shortening ratio depends on the SOA operating conditions. This circuit can be operated at higher bit-rates, by simply varying accordingly the FSR (while maintaining unaltered the Finesse).
5 Conclusion
We discussed the capability of a FPF-based circuit to recover clock signals from a variety of modulation formats and for optical packets. The circuit was demonstrated at 40 Gb/s for 00K signals and 10 Gb/s for DSPK signals. It can be upgraded to higher bit-rates with increased tolerance to signals bit-rate and wavelength stability. 6. Acknowledgment
This work was partially supported by the European Commission FP6 program through the project IST NOBEL II 6. References
J. Slovak et al:"Bit rate and wavelength transparent alloptical clock recovery scheme for NRZ-coded PRBS signals", IEEE Photon. Technol. Lett.,18, 7, 2006 [2] G. Contestabile, et al.: "40-GHz all-optical clock extraction using a semiconductor-assisted Fabry-Per6t filtee', IEEE Photonics Technology Letters,16, 11,.2004 [3] G. Contestabile, et al: "All-optical clock recovery from 40 Gbit/s NRZ signal based on clock line enhancement and sharp periodic filtering", Electronics Letters, 40, 21, 2004 [4] M. Funabashi et al: "Packet-by-Packet all-optical burst-mode 3R regeneration in an optical-label switching router",
[1]
Proceedings of OFC 2006 [5] T. Wang et al.: "Combination of Comb-Like Filter and SOA for Preprocessing to Reduce the Patten Effect in the Clock Recovery", Photon. Technol. Lett., vol. 16, pp. 614 - 616,
4 Applications to Burst Traffic The CR circuit was tested In optical packets architectures. Several groups shown the effectiveness of the proposed CR circuits in case of burst traffic with RZ modulation [4].
February 2004
Zhuary "0 0[6] Z. Zhu, et al: a10 all-optical 3R 000-hop cascaded 000-km 10-Gbls regeneration to achieve 1 250 in-line transmission", IEEE Photonics Technology Letters, 18,
. Recovered Packet Clock
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Incoming DPSK Packets .
........[9] G. T. Kanellos et al:
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M. Funabashi et al: "First Field Demonstrations of 1000-hop Cascaded All-Optical 3R Regeneration in 10 Gb/s NRZ
Beach, California, USA) ,2006
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0oGbls Asynchronous Optical Packets' IEEE Photonics ............Technology....Letters,.. T15noog11ettpp. 11666-1668,66 166 20030 [10] P. Bakopoulos: "Compact all-optical packet clock and data
- - -'- - -nne/divl recovery circuit using generic integrated MZI switches,'
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Fig. 5 CR circuit behavior with 10Gb/s DPSK otical packets.
Traces are recorded with a Sampling Oscilloscope and 10 GHz bandwidth photodiode. Insets show detailed eyediagrams both for recovered clock and demodulated packets.
~~~[11]
13, 17, pp 6401-6406, 2005 A. D'Errico, et al: "WDM-DPSK Detection by means of Frequency-Periodic Gaussian Filtering" Electronics Letters, 42, pp.112-113, 2006
As explained before, the versatility of this circuit, easily allows the extension of these results to DPSK packets, as PS'2006 - Photonics in Switching Conference
