Very Low-Noise ENG Amplifier System Using CMOS ... - IEEE Xplore

IEEE TRANSACTIONS ON NEURAL SYSTEMS AND REHABILITATION ENGINEERING, VOL. 14, NO. 4, DECEMBER 2006

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Very Low-Noise ENG Amplifier System Using CMOS Technology Robert Rieger, Martin Schuettler, Dipankar Pal, Chris Clarke, Peter Langlois, John Taylor, and Nick Donaldson

Abstract—In this paper, we describe the design and testing of a system for recording electroneurographic signals (ENG) from a multielectrode nerve cuff (MEC). This device, which is an extension of the conventional nerve signal recording cuff, enables ENG to be classified by action potential velocity. In addition to electrical measurements, we provide preliminary in vitro data obtained from frogs that demonstrate the validity of the technique for the first time. Since typical ENG signals are extremely small, , very low-noise, high-gain amplifiers are on the order of 1 1 required. The ten-channel system we describe was realized in a CMOS technology and detailed measured results are pre0.8 sented. The overall gain is 10 000 and the total input-referred root mean square (rms) noise in a bandwidth 1 Hz–5 kHZ is 291 nV. 2 and the power consumption is 24 mW The active area is 12 from 2.5 V power supplies.

m

V

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Index Terms—Multielectrode recording.

cuff,

nerve

cuff,

tripolar

I. INTRODUCTION MAJOR current challenge in neuroprosthetics research concerns the use of naturally occuring neural signals (ENG) to provide sensory feedback to artificial devices. Neural afferent signals generated by natural sensors within the body can be used to obtain information such as skin contact, force, and position [1]–[4], so they may be used in closed-loop neuroprostheses. These applications require stable responses from chronically implanted electrodes. Nerve cuff electrodes are currently the most well-established nerve interfaces with safe implantation being reported for as long as 15 years [5]. Consequently, nerve cuff electrodes have been used at sites in the limbs [6] and on the nerves that innervate the bladder [7]. A further advantage of these electrodes is that implantation is relatively easy, the cuff is either slit and reclosed, or is self-curling, to allow surgical placement without damage to the nerve. Fig. 1(a) shows the general form of a typical nerve cuff

A

Manuscript received November 4, 2004; revised July 4, 2006; accepted July 7, 2006. This work was supported by CEC project Smart Electrode for Nerve Sensing (SENS) Ref QLG5-CT-2000-01372. R. Rieger is with the Department of Electrical Engineering, National Sun Yat-sen University, Taiwan. M. Schuettler is with the Department of Microsystems Engineering, University of Freiburg, Freiburg D-79110 Germany. D. Pal is with the Department of Electronics and Communication Engineering, B.I.T. Mesra, Ranchi 835215 India. C. Clarke and J. Taylor are with the Department of Electronic and Electrical Engineering, University of Bath, Bath BA2 7AY, U.K. (e-mail: [email protected]. uk). P. Langlois is with the Department of Electronic and Electrical Engineering, University College, London WCIE 7JE, U.K. N. Donaldson is with the Department of Medical Physics and Bioengineering, University College, London WCIE 6BT, U.K.. Digital Object Identifier 10.1109/TNSRE.2006.886731

fitted with three electrodes, while Fig. 1(b) shows its equivalent circuit and a typical tripolar amplifier system (see Section II). In the tripolar nerve cuff shown in Fig. 1(a), only one signal output is available and hence the information that can be obtained is limited. Because the large number of fibres in each peripheral nerve carry a great many neural signals with, generally, both afferent and efferent traffic, this reduction to only one output signal represents a huge loss of information. However, where fibres of different diameter carry various types of neural signal, it should be possible to extract more information from one cuff if fibre diameter-selective recording were possible. This is equivalent to measuring the level of activity in the velocity domain, because of the approximately linear relationship between axon diameter and action potential (AP) velocity [8]. A method for velocity-selective recording has been described recently [9]: it relies on the use of a multielectrode cuff (MEC). An MEC tripoles of the single tripole arrangement is an extension to shown in Fig. 1, where is typically about 10. As a result, more than one ENG signal is available, which, as outlined in Section II, is the key to the proposed velocity selective recording (VSR) technique. In spite of the many advantages of the nerve cuff approach to ENG recording, the amplitude of the ENG recorded using this method is very small, on the order of a few microvolts, with most of the signal power in a bandwidth between about 300 Hz–5 kHZ. This problem is exacerbated in an MEC, since in this type of cuff the electrodes are spaced more closely than in a single-tripole cuff of the same length, resulting in even smaller signal amplitudes. In addition, the ENG signal recorded from nerve cuff electrodes is contaminated by significant amounts of noise. In the bandwidth of interest, for a single tripole, the most significant noise source is the axial (ohmic) resistance appearing and in Fig. 1(b)]. With the between the electrodes [ MEC and increasing , the spreading resistances [ , and ] become dominant. These sources contribute thermal (additive white Gaussian) noise that, together with noise generated by the amplifiers, degrades the signal-to-noise ratio available at the tripole outputs. Therefore, ENG recording systems rely critically on the availability of very low-noise, high-gain amplifiers [10]–[13]. In this paper, we describe the design, fabrication and testing of the analogue signal-capture sections of a ten-channel amplifier system suitable for connection to an MEC. This is intended to be an implantable system to be mounted, ideally, directly on the MEC to take maximum advantage of the very low noise capabilities of the preamplifier stage of the system. We also describe preliminary in vitro experiments in frogs which provide the first practical validation of the VSR process. The system has an overall gain of 10 000 and a total input-referred root mean

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Fig. 1. (a) Insulating cuff and tripolar electrode assembly fitted to a nerve. (b) True-tripole recording system and amplifier arrangement.

Fig. 2. Two action potentials with different velocities and their electro neurogram as recorded by an eleven contact cuff (MEC) connected to a bank of tripolar amplifiers.

square (rms) noise per channel of less than 300 nV in a bandwidth of 1 Hz–5 kHZ. In addition, a general description of the digital signal processing required to perform velocity selective recording is given. The system block diagram is shown in Figs. 2 and 3. Fig. 2 indicates the principle of VSR while Fig. 3 outlines the architecture of the signal processing required by the system. In outline, the system consists of the interface to the MEC followed by two stages of amplification and a signal-processing unit (SPU). The first rank amplifiers are specially designed low noise, low power units (preamplifiers) each with a nominal voltage gain of 100. This design is described in Section III and its superiority to other designs is quantified by the benchmarking exercise described in Section VI. Each preamplifier is followed by an alternating current (ac) coupling stage that, in addition to removing direct current (dc) offsets, shapes the frequency response of the system, setting the lower cutoff frequency of the passband at 300 Hz.

This is described in Section IV. This stage is followed by a second rank of much less tightly specified amplifiers, each also having a gain of 100 and an upper (i.e., lowpass) cutoff frequency of 3.5 kHZ. The outputs of these second rank amplifiers are bandpass filtered difference voltages taken between pairs of adjacent electrodes. They are called dipole signals [see also Fig. 1(b)]. The dipole signals form the inputs to the SPU, which is shown in the box on the right of Fig. 4. The SPU contains elements that are common to each chosen velocity band (multiplexing, analogue to digital conversion) and some which are duplicated for each band (delay, summation, filtering). The digitized dipole signals are subtracted in pairs to form tripole signals, as shown in Fig. 3, before processing by the SPU as explained in Section II. In order to demonstrate the VSR process, the system was used to measure electrically evoked ENG (i.e., compound action potentials) in the sciatic nerve from a Xenopus Laevis frog using

RIEGER et al.: VERY LOW-NOISE ENG AMPLIFIER SYSTEM USING CMOS TECHNOLOGY

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Fig. 3. System of Fig. 2 showing the signal processing unit for selecting one velocity.

Fig. 4. Preamplifier architecture.

an in vitro preparation. For these initial experiments, the dipole output signals were coupled directly to a PC fitted with a data acquisition card (DAC) and running MATLAB. This combination implemented the SPU, providing all the required signal processing. A description of the experimental arrangement and details of the cuff construction are given in Section V. Section VI reports measured results and is divided into two parts. The first part details the electrical measurements on the fabricated chips (including the benchmarking exercise already referred to) and compares them with CADENCE simulations while the second part describes the results of the in vitro frog experiments. Finally, Section VII contains discussion and conclusions. II. ELEMENTS OF MULTIELECTRODE NERVE CUFF RECORDING The problem of the small amplitude of the ENG signal recorded using electrode cuffs and consequent noise contamination has already been mentioned. Additionally, interfering signals, especially electromyographic (EMG) potentials generated by excited muscles near the cuff, can have much greater amplitudes than ENG, typically larger by a factor of two or three orders of magnitude. However, it is well known that the influence of common mode potentials such as EMG can

be reduced significantly by the use of one of the forms of tripolar electrode system [15]. The MEC and amplifier array connected as shown in Figs. 2 and 3 is an extension of the true tripole system first described by Pflaum et al. [15] and displays significant immunity to contamination by common mode interference signals. By contrast, the ENG signal, resulting from propagation along the nerve does not cancel in this way and can be recovered. As already noted, an MEC is an extension of tripoles. Long cuffs are bound to the single tripole case to jeopardize the nerve so we assume that the MEC will be limited to 20–30 mm, depending on the site. The result of this is that the interelectrode spacing must be decreased in proportion to the number of electrodes in the MEC, which also reduces the amplitudes of the individual tripole outputs. As the ENG signal propagates along the nerve, voltages appear at the electrodes and hence at the tripole outputs. There is a delay between the appearance of the signals at successive tripole outputs which is a function both of the conduction velocity, and the intertripole spacing, , so that:

(1) This process is illustrated in Fig. 2 where the electrical tripolar signals resulting from an AP propagating along the nerve from top to bottom are shown. If equal and opposite delays are introduced subsequently by the signal processing, and the tripole signals are added, the resulting output power is a maximum for that conduction velocity [9], [16]. Using several signal processing units, with delays chosen to correspond to a set of velocity bands across the spectrum, the power at each output will be proportional to the level of activity in the band.

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If the bands are well-chosen, they may correspond to distinct physiological functions. As described in [9], we define velocity selectivity in terms of a “matched” velocity, i.e., the propagation velocity at which the inserted delay exactly cancels the naturally-occurring delay and the transfer function of the system is a maximum and a further pair of velocities, one greater than and one less than the matched velocity, at which the output power has fallen to one half its peak value. By analogy with the frequency domain, we refer to the difference between these two velocities as the 3 dB velocity bandwidth. The arrangement to implement the signal processing required for velocity selectivity is shown in Fig. 3. Each output is followed by a bandpass filter which has the effect of equalizing the velocity selectivity of each signal processing unit, since these selectivities tend to be quite velocity-dependent [9]. Analysis and simulation (not repeated in this paper, see [9]) suggest that about six equally-spaced bands can be resolved across the typical range of 120 m/s. In addition, a key result of the analysis indicates that the method is particularly suited to recording ENG at the lower end of this velocity range, which is not generally possible using a single tripole.

III. PREAMPLIFIER STAGE The noise in the recording channel is dominated by the preamplifiers making very low-noise design essential. After preamplification the signal level is high enough that noise is not a major concern in subsequent stages. Absolute amplifier gain and linearity are not critical in biopotential recording [17], so that the feedforward architecture shown in Fig. 4 was chosen to eliminate the added complexity and noise of feedback networks. Although the overall system bandwidth (3.5 kHZ) is set by the second rank amplifiers, it was felt necessary to protect the highly sensitive preamplifiers from high frequency and the capacitor implement this interference. Resistor by defining the local high-frequency cutoff at about 35 kHZ. The preamplifier is followed by the ac coupling stage described in Section IV that, in addition to eliminating the dc offset at the preamplifier output, removes the low frequency noise tail. It has been shown that since bipolar transistors (BJTs) achieve very low noise on reasonable silicon area with low power consumption they are well suited to use in the input stages of ENG preamplifiers [14]. In addition, the differential ac input impedance of the BJT-based front-end described ) compared to the below is still sufficiently high (about 15 at ENG frequencies) electrode source impedance (about 1 to avoid loading the source, resulting in loss of signal. The main reason for the advantageous noise performance is as follows. The white noise current spectral density in the channel of metal-oxide-semiconductor (MOS) and BJTs can be approximated by [10]

(2) where the symbols have their usual meaning and is around 0.8 for MOS and unity for BJT. For a differential amplifier, the

noise current in the channels of the input transistors feeds into the load resistor and produces an output voltage noise density of

(3) where is the signal gain of the amplifier. Since transconducis larger in a BJT compared to a MOS with the same tance bias current (typically by a factor around 3), the noise performance of the bipolar design is always superior. This is particularly important in applications such as this where low noise and low power are required (this theme is taken up again in the benchmarking exercise described in Section VI). Unfortunately, the ideal choice of an optimized BiCMOS process is significantly more expensive than a pure CMOS realization. Although a more cost effective CMOS process does not provide dedicated (vertical) BJTs, it has been suggested that lateral bipolar transistors can be used in low frequency applications with no significant loss in circuit performance [18]. Nevertheless, in a typical lateral device up to 50% (but more typically about 25%) of the emitter current is diverted into the substrate and does not contribute to transconductance, so that this approach comes at the expense of some increased power consumption. Assuming is rea worst-case efficiency of 50%, a tail current of 280 output spot noise acquired to achieve less than 350 cording to (2). A current of this order is still within the given power budget, so that lateral devices can be used in this application to minimise noise and chip cost. transistor employed is an optimized standard The lateral CMOS/BICMOS process by Austricell available in the 0.8amicrosystems. In this design, the emitter area and lateral base width (i.e., the channel length of the corresponding MOS transistor) are minimized and the emitter is surrounded by the collector so as to favour the lateral device as far as possible [18]. Lateral current gains of more than 100 are possible using these structures, which is adequate for the application described in this paper. However, due to the onset of strong injection (i.e., when the density of minority carriers at the emitter end of the base approaches the net impurity density) it is impossible to maintain this level of lateral current gain with collector currents of more than a few microamperes. For this reason, a parallel combination of 24 standard cells was employed in each half of the long tailed pair differential amplifier to sustain a current gain of about . In spite of this requirement, the 100 at a tail current of 280 area of the amplifier is comparable to an implementation using vertical bipolar transistors [14]. A complete circuit schematic is and shown in Fig. 5, including additional transistors to cancel the input bias currents. IV. AC COUPLING AND SECOND RANK AMPLIFIER STAGES A. AC Coupling Stage To remove the offset voltage at the amplifier output, ac coupling is required. This has a high-pass filtering action and, ideally, eliminates low frequencies below the ENG passband


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Fig. 5. Preamplifier schematic (Q1–Q3 are lateral pnp transistors).

Fig. 6. (a) Equivalent circuit of the preamplifier and ac coupling stages. (b) Reduced form of (a) for calculating the noise contribution from the ac coupling stage.

without increasing the noise in the recording channel. In practice, although eliminating the low-frequency noise tail of the noise) increases the dynamic preamplifier (i.e., the residual range of the system, the filter components will introduce some noise in the passband. In the design of this system, we chose to match the filter to the preamplifier in the sense that the noise power added by the filter in-band was equal to that eliminated in the low frequency tail. The reason for this choice is discussed at the end of this section. Note that the 1/f noise contribution of the ac coupling stage itself is not considered in this calculation. Both simulation and measurement show that this is negligible compared to the white noise contribution. This is due firstly to the absence of dc current in the two MOS transistors used and secondly to the fact that they are both very long in comparison to their widths. As shown in the following analysis, a first-order resistance–capacitance (RC) filter provides the required performance and can be realized with minimum component count and no static power dissipation. This stage is added in cascade with the low-pass filter at the output of the preamplifier as shown in the equivalent circuit in Fig. 6(a). Since the cutoff frequencies of the two sections (i.e., lowpass and highpass) are very different (300 Hz, 35 kHZ), there is negligible interaction between them. As a result, to a good level of approximation, the reduced form given in Fig. 6(b) can replace the circuit of Fig. 6(a).

The resulting filter noise power density can, therefore, be approximated as follows:

at frequency

(4) where

is the filter cutoff frequency given by

(5) Integration of (3) and substituting (4) yields the total filter noise power below frequency

(6) Simulation of the preamplifier predicts that the total rms noise power below the cutoff frequency is around 50 . Choosing a matching filter noise contribution and solving (6) for allows calculation of the required follows directly from (5), recapacitance. The magnitude of sulting in component values and . The noise performance of the preamplifier alone and in combination with the RC-filter has been simulated using circuit parameters provided by the foundry. The preamplifier output noise

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Fig. 7. High value active resistor for ac coupling stage.

Fig. 9. Percentage variation of the value of the active resistance from its nominal value (8.2 M ) as a function of applied voltage compared to a single PMOS transistor of aspect ratio 2/387.

resistance can be realized. Although this method is attractively simple and small compared to many other designs that have been published (see, e.g., [19]), given the signal levels at this point in the circuit, the very high nonlinearity that results is unacceptable in this application. Fig. 7 shows a second possibility, consisting of two complementary devices in series connection. In addition to providing the required high resistance, this arrangement, given an appropriate choice of relative channel lengths, shows considerably improved linearity compared to a single MOS. The design is based on the SPICE Level 1 model. Although approximate, it is adequate for this purpose

(7)

Fig. 8. Output noise PSD before and after the RC filter (total rms noise in the bandwidth 1 Hz–10 kHZ remains the same).

and is the transconductance parawhere meter. From this expression, it is possible to show that the resistances of the individual devices are given approximately by

(8) power spectral densities (PSDs) before and after filtering are -noise compared in Fig. 8. As predicted, the preamplifier tail (as well as the dc offset) is removed by the filter. Between 50 Hz and 1 kHZ the noise increases slightly, due to the thermal noise contribution from the active resistor, so that the total rms input referred voltage noise in the bandwidth 1 Hz–5 kHZ remains unchanged at 290 nV as expected. Note that it is possible to design a coupling stage which removes more low-frequency noise than is added in the pass band. However, this requires a larger capacitor than that chosen above, which was felt to be undesirable, as discussed below. of the required magnitude would conA physical resistor sume excessive chip area and so the use of an MOS transistor biased in the ohmic region was considered. Using this approach, much less than unity, high values of with an aspect ratio

(9) and hence the total resistance of the combination is the sum of the two where “ ” and “ ” relate to the PMOS and NMOS deis the common source voltage. The vices, respectively, and right-hand side of both equations consists of two terms: the first , is a linear term with no dependence on the signal voltage the second term represents the nonlinear behavior of the devices. The linearization strategy employed is therefore to make these terms equal, so that when the devices are connected in series, they cancel from the expression for the total resistance. After some manipulation (a complete analysis of the device is beyond the scope of this paper and is the subject of a forthcoming publication), it can be shown that cancellation of the nonlinear terms


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Fig. 10. Second rank amplifier schematic.

in (8) and (9) occurs when the device aspect ratios are chosen so that (modulus signs ignored)

(10) For

, , and , the transistor aspect ratios were calculated as shown in Fig. 7. Fig. 9 shows a plot, based on simulation, of the error resulting from the NMOS-PMOS combination compared to a single PMOS transistor realizing the same value of resistance. Although simulations of the active resistor agreed closely with measured results, there is no guarantee that this would be the case for all process runs, due to the presence of process parameters in (8)–(10). Worst case simulation indicated total harmonic distortion of about 1% with 100 mV peak signal and a shift in nominal value of about 15%. Given that the actual signal level will be much less than 100 mV in practice, neither of these nonidealities seems likely to be significant in a system of this type. active resistor is about 1000 , The total area of the 8.2 whereas the 65 pF capacitor occupies about 43 000 . The area penalty of a further increase in the value of the capacitance is not, therefore, compensated by a corresponding decrease in the area of the resistor. Further noise reduction by this means is not, therefore, an attractive option. Conversely, trading the area of the capacitor against a larger resistor results in the generation of more noise in the passband, which is also undesirable. These considerations led to the choice of the compromise solution mentioned above. B. Second Rank Amplifiers The circuit schematic of the second-rank amplifier is shown in Fig. 10. It consists of a fully symmetrical operational transconductance amplifier (OTA), where the output current feeds into and to achieve the impedance provided by transistors a high voltage gain. The gain stage is followed by a Class AB of the type discussed in, e.g., [20], output stage . The overall to drive the resistive feedback network open loop gain is about 72 dB and the feedback network sets the closed-loop voltage gain to 100 (40 dB). The value of capacitor (35 pF) is chosen to set the high-frequency cutoff of the recording channel to the specified value of 3.5 kHZ.

Fig. 11. Setup for recording electrically evoked compound action potentials from frog nerve in Ringer’s solution using an eleven contact recording cuff and a hook electrode (for validation purposes).

V. EXPERIMENTAL ARRANGEMENT The general layout of the experiment is shown in Fig. 11. The core of the setup is the MEC and the amplifier bank connected to it. In addition, a stimulation cuff was used to electronically excite the nerve with a bipolar hook electrode (manufactured using 0.1 mm diameter platinum wire). ENG was recorded in the manner of Erlanger and Gasser [21] to provide a useful measure of control of the MEC recorded data, although this aspect is not discussed in this paper. The following paragraphs describe the MEC and the in vitro preparation in more detail A. Neural Electrodes Polyimide thin-film technology was employed to manufacture the MECs. The electrodes consist of a 300-nm film of sputtered platinum sandwiched between two 5sheets of spin-coated polyimide (Pyralin 2611). The area of the contact pads and recording sites was exposed by dry-etching the top polyimide sheet using oxygen plasma. A detailed description of the manufacturing process can be found in [22]. The planar polyimide substrate was transferred to the three-dimensional cuff shape by keeping it curled in a metal tube while annealing ). Now the mechanical stress by heat treatment (2 h at 300 self-curling, the cuffs were connected to screen printed alumina ceramic adapters by a gold-bond technique which rivets the thin-film contacts through a hole to the screen printed gold tracks of the ceramic substrate [22]. Enameled copper wires

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Fig. 12. Polyimide thin-film cuff electrode with eleven contacts, visible on this photograph as dark vertical lines.

Fig. 13. ASIC chip microphotograph.

were then soldered to the screen printed tracks. All the contacts and tracks of this adapter were insulated with medical grade silicone adhesive. The final electrode was 1.5 mm in diameter, 40 mm long, and carried eleven 0.5 mm wide, ring-shaped platinum. This is shown in Fig. 12. The stimulation electrodes were fabricated in the same way as the recording electrodes. They had a diameter of 1.0 mm and three ring-shaped platinum contacts (0.2 mm wide) at a longitudinal pitch of 5.0 mm. B. Nerves for Experimentation Four sciatic nerves were obtained from two decapitated adult Xenopus Laevis frogs. After dissection, the nerves were transferred to the basin of the setup and immersed in amphibian Ringer’s solution. The nerves had a total length of typically 8–9 cm and varied in diameter from 0.5 mm (distal) to 2 mm (proximal). VI. MEASURED RESULTS A. Analogue Signal Acquisition System A microphotograph of the complete 10 channel ASIC is shown in Fig. 13. The packaged chip was mounted on a speand powered from voltage regulators also cially designed mounted on the . All bias currents are derived from a single source. The following sets of measurements external 50 were carried out. 1) Frequency Response: Five chips were selected at random for test from the fabricated batch of 15. The frequency response of the ten channels on each chip was measured in response to an and the results averaged (i.e., 50 input signal of amplitude 10 measurements in all). This response is shown in Fig. 14 together with the simulation of the nominal system. The measured values show close agreement with the simulation. 2) Input-Referred Noise and Benchmarking: The input referred voltage and current noise of the system were measured as output voltages with the input shorted to ground (for the voltage

Fig. 14. Averaged frequency response of all 10 dipole channels from five randomly chosen chips (50 channels in all) compared to the nominal simulation.

noise) or connected to ground by a 100 resistor (for the current noise). For these measurements, two channels were chosen at random from each of the five chips used in the frequency response measurement (total 10 measurements each for voltage and current noise). Fig. 15 shows the input referred voltage noise density as a function of frequency, together with the simulated curves, for comparison. The agreement between the two is exact at the band edges and very good elsewhere. The input referred current noise spectrum (not shown) is in similarly close agreement with the simulated result. In order to calculate the input referred rms voltage noise, the rms voltage (square root of power) noise in a bandwidth 1 Hz–5 kHZ was calculated by integrating the voltage and current noise power spectral densities over the , sumappropriate range, assuming a source resistance of 1 ming and taking the square root. The resulting value was 291 nV, which falls within the specification (see Table I). The noise efficiency factor (NEF) is commonly used as a benchmark for the comparison of noise performance of amplifier front-ends [10]. The NEF relates the input referred voltage noise of an amplifier to the shot noise generated by a single bipolar transistor


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TABLE I SYSTEM SPECIFICATION

Fig. 15. Average measured input-referred voltage noise taken from two channels chosen at random from the same five chips used for Fig. 14 (10 channels in all).

with a collector current equal to the total current consumed by the amplifier. However, this factor does not consider the effect of current noise, which may not be negligible in a very low-noise design such as this. We therefore extend the definition of the NEF to a comparison between the noise of a single bipolar transistor connected to a matched and noiseless input resistance and the noise of a single recording given by channel connected to the input resistance typical for the application. The NEF is then defined as TABLE II BENCHMARK COMPARISON OF ENG AMPLIFIERS

(11) where is the total current consumed in each recording and are the input-referred rms voltage and channel, is the bandwidth of the current noise, respectively, and channel. A single bipolar transistor has a NEF of one and a differential input stage containing two bipolar devices has a ; all practical circuits have higher values. The meaNEF of sured performance of the MEC recording system connected to leads to a NEF of 3.1. a typical input resistance (cuff) of 1 NEFs calculated for previously reported multichannel designs are considerably higher. Some examples are tabulated below, indicating clearly the advantages of this front-end design for interfacing with nerve electrode systems, including MECs (see Table II). 3), 4) CMRR and PSRR: These were measured in the conventional manner and the results are presented in Table I. The measured results compare well with the simulation. 5) Residual Input Current: Five chips were selected at random and the inputs of each channel were connected to resistors. The residual input currents ground through 10 were measured in terms of the voltages appearing across these resistors. The average currents were 15.5 nA for the noninverting inputs (S.D.1.7 nA) and 20.25 nA for the inverting

inputs (S.D.2.2 nA). These are highly satisfactory results, well within the specified limit of 100 nA. 6) Adjacent Channel Breakthrough (Crosstalk): For one chip chosen at random from the batch, the central channel was driven (channel 5 output by a 1-kHZ sinewave of amplitude 55 565 mV), the other inputs being grounded and the outputs on the other channels were measured. The resulting crosstalk was small, less than 1% in all cases and is tabulated below. Note that the amplitude of the crosstalk decreases away from the centre since channel 5 was placed in the center of the layout (see Table III). B. In Vitro Measurements Figs. 16 and 17 show the amplified bipolar cuff electrode signals after being converted to tripolar signals (signals based on a recordings from three electrode contacts) using MATLAB. The

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TABLE III MEASURED ADJUSTMENT CHANNEL BREAKTHROUGH

of 35 m/s and smaller one which relates to a speed of 14 m/s. These measurements fall within the velocity range for frog nerves at room temperature which is up to 42 m/s [21]. VII. DISCUSSION AND CONCLUSION

Fig. 16. Tripolar recordings of electrically evoked potentials, recorded with the eleven-contact cuff. The stimulation intensity was 0.13 C. Black bar to the right shows the amplitude scale: 50 V .

Fig. 17. Tripolar recordings of electrically evoked potentials, recorded with the eleven-contact cuff. Stimulation intensity was 1.01 C. Black bar to the right shows the amplitude scale: 50 V .

-axis shows the position of the tripole along the cuff. The further the tripole is placed along the cuff, the longer the time the signal needs to appear. Fig. 17 shows the effect of higher level of stimulation intensity than in Fig. 16. In this case the dispersion of two different CAPs, corresponding to populations with different propagation velocities can be seen. Given the electrode contact pitch of 3.5 mm, it is easy to calculate the AP propagation velocity from the measured data presented in Figs. 16 and 17. At low levels of stimulation (Fig. 16), one species is seen, corresponding to a propagation velocity is 28 m/s. At high stimulation charges (Fig. 17), we find two species, one corresponding to a velocity

A system for the recording of nerve signals from a multielectrode cuff (MEC) has been described. Previously reported designs focus on recording from conventional tripoles, which provide a single output, whereas the system described in this paper comprises 10 parallel recording channels to enable velocity selective recording (VSR). In addition, some preliminary in vitro experiments in frogs are described. As well as demonstrating the capabilities of the amplifier array, they provide the first practical validation of the VSR method. The challenge of recording the very small ENG signal in the presence of noise is met by a specially designed very low noise preamplifier front-end. The proposed preamplifier uses lateral bipolar input transistors as the optimum choice considering noise, power consumption and manufacturing cost. The benefit of this approach is illustrated by a benchmarking comparison with other designs. The device is intended to be mounted directly on the nerve cuff to take maximum advantage of its low noise properties. A stage to ac couple the preamplifier to the subsequent stages is described which removes any preamplifier output offset voltages. This stage also defines the lower cutoff frequency of the recording channel at about 300 Hz. The coupling stage comprises a very large resistance, realized by a series connection of complementary MOS transistors. The proposed structure is analyzed and is shown to yield a very large impedance whilst introducing less distortion than a single MOS transistor operated in the linear region. The noise shaping properties of the coupling stage are discussed in detail to arrive at optimum component values for the desired noise performance. A second-rank amplifier is described which provides the gain necessary for subsequent digital processing of the signal and also sets the upper cutoff frequency of the channel to the specified value of about 3.5 kHZ. Although this value of upper cutoff frequency is somewhat lower than that generally used in ENG recordings, it did not adversely affect the primary aim of this work, which was to demonstrate the VSR process. In addition to the detailed account of the analogue sections of the system, an outline description of the digital signal processing required to provide velocity selective ENG spectral analysis is provided. Measured results obtained from five test chips, selected randomly from a fabricated batch of 15, containing the complete recording system are presented. Special attention is given to the frequency response, noise, CMRR, PSRR, input offset currents, linearity, and crosstalk. The measured results are in good agreement with the CADENCE simulations and design targets for velocity-selective recording. The performance is achieved at low cost using a standard CMOS process. Finally, the results of the in vitro CAP experiments are described. For these an MEC of length 40 mm was employed, fitted with eleven ring-shaped platinum electrodes. In practice, in an in vivo situation, surgical considerations would probably limit the maximum length of the MEC to about 30 mm, which is similar to that of cuffs that have been implanted successfully and


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