VLSI Design and Application of a High-Voltage ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 5, OCTOBER 2007

VLSI Design and Application of a High-Voltage-Compatible SoC–ASIC in Bipolar CMOS/DMOS Technology for AC–DC Rectifiers Winston Langeslag, Rosario Pagano, Member, IEEE, Kees Schetters, Arjan Strijker, and Arjan van Zoest

Abstract—This paper presents an application-specific integrated circuit (ASIC) controller that is suitable for double-stage ac–dc power converters, which employ power-factor correction (PFC) and flyback topologies. The PFC cell is used as a preregulator to comply with line-current harmonic standards, while the flyback converter operates in quasi-resonant (QR)/discontinuous conduction mode to deliver to the load a maximum output power of 120 W. The control functions of the PFC and flyback converters are combined in a unique system-on-chip–ASIC solution to reduce system complexity. The ASIC implements valley-switching control of both the PFC and flyback cells to achieve QR operation. The concept of “valley skipping” is also recalled by the proposed ASIC to determine the operating point in the power-frequency characteristic of the power converter. Depending on the output-power requirement, the ASIC drives the flyback stage into three different states, which result from the combination of the QR and valleyskipping modes. This allows the flyback converter to operate at a fixed on-time, while its off-time is changed according to the output power. The PFC stage is also driven in the QR mode with valley skipping to provide the dc–dc stage with a fixed input voltage of 400 V. To evaluate the performances of the presented ASIC device, a demoboard of a 120-W PFC–flyback system has been realized and tested. Several experimental results have been carried out to confer the validity of the approach that is discussed throughout this paper and to evaluate the performances of the ac–dc rectifier. Index Terms—Application-specific integrated circuit (ASIC), flyback, power-factor correction (PFC), system integration, valleyswitching control.

N OMENCLATURE C CDS,1 CDS,2 Ceq,1

Input capacitance of the valley-detection circuit. Parasitic drain-to-source capacitance of M1 . Parasitic drain-to-source capacitance of M2 . Equivalent output capacitance of M1 .

Ceq,2 CGD,1 CGD,2 COUT Cramp D Frel (n) fring,2 fs,2 fs_ max,1 fs_ max,2 fs_ min,2 I1 I2 IC ICOM P ID,1 ID,2 Idis IIN IL IP Ipk,1 Ipk,2 Ipk,crit Ipk_ max,2 IREF IS LIN Llk

Manuscript received July 27, 2006; revised November 9, 2006. This paper was presented in part at the 32nd Annual Conference of the IEEE Industrial Electronics Society, Paris, France, November 7–10, 2006. W. Langeslag, K. Schetters, A. Strijker, and A. van Zoest are with NXP Semiconductors (formerly Philips Semiconductors), 6534 AE Nijmegen, The Netherlands (e-mail: [email protected]; kees.schetters@nxp. com; [email protected]; [email protected]). R. Pagano was with the Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, University of Catania, 95125 Catania, Italy. He is now with NXP Semiconductors (formerly Philips Semiconductors), 6534 AE Nijmegen, The Netherlands (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2007.894735

Lm m M1 M2 MHRnorm (n) N

0278-0046/$25.00 © 2007 IEEE

Equivalent output capacitance of M2 . Parasitic gate-to-drain capacitance of M1 . Parasitic gate-to-drain capacitance of M2 . Output capacitor of the PFC. Capacitor in the PFC controller used for ramp voltage generation. Output diode of the PFC. Amplitude of the nth harmonic of the mains current normalized to the fundamental one. Ringing frequency of the flyback converter. Flyback switching frequency. Maximum operative frequency of the PFC. Maximum operative frequency of the flyback. Minimum operative frequency of the flyback. Output current of the voltage-to-current transducer that is internal to the PFC controller. Output current of the transconductance amplifier that is internal to the PFC controller. Current flowing into the capacitor of the valley-detection circuit. Compensation pin of the PFC controller. Drain current of the PFC switch. Drain current of the flyback switch. Discharge current of Cramp . Input current of the ac–dc rectifier. Input current of the PFC. Primary current of the flyback converter. Peak current of the PFC switch. Peak current of the flyback switch. Critical peak value of the PFC input current. Maximum peak current of the flyback switch. Reference current of the valley-detection circuit. Secondary current of the flyback converter. Input inductor of the PFC. Leakage inductance of the flyback transformer. Magnetizing inductance of the flyback transformer. Number of valleys of M1 drain voltage. PFC switch. Flyback switch. Limit that is imposed by class-D standards to the nth harmonic of the mains current. Flyback-transformer turns ratio.

LANGESLAG et al.: VLSI DESIGN AND APPLICATION OF HIGH-VOLTAGE-COMPATIBLE SoC–ASIC

Pon,ZVS S T1 T2 Tf,1 TL Toff,1 Toff,2 Ton,1 Ton,2 Tr,1 Tring,1 Tring,2 Ts,1 Ts,2 VDS,1 VDS,2 VFB,CTRL VFB,DEM VFB,DRV VFB,ENABLE VFB,GATE VFB,OSC VFB,POL VFB,SENSE VFB,VALLEY VGS,1 VGS,2 VIN VIN,SENSE VM Vmin VO,PFC VOCP,SENSE VPFC,AUX VPFC,DRV VPFC,GATE VPFC,OSC VPFC,SENSE VPFC,VALLEY VREF ωL

Turn-on power loss of the flyback under zerovoltage-switching conditions. Switch that is internal to the PFC controller. PFC magnetic core. Flyback transformer. Fall time of the voltage across M1 . Time period of the mains voltage. Off-time of the PFC. Off-time of the flyback. On-time of the PFC. On-time of the flyback. Rise time of the voltage across M1 . Total ringing time of the drain voltage across M1 . Ringing time of the drain voltage across M2 . PFC switching period. Flyback switching period. Drain-to-source voltage across M1 . Drain-to-source voltage across M2 . Output voltage of the feedback circuit. Voltage that is derived from the flyback auxiliary winding. Driving voltage of M2 . Enabling signal of the flyback controller. Driving voltage of M2 . Output voltage of the flyback oscillator. Voltage signal that is used for polarity check. Voltage that is derived from the flyback transformer. Output voltage of the valley-detection circuit. Gate-to-source voltage across M1 . Gate-to-source voltage across M2 . Input voltage of the ac–dc rectifier. Scaled and filtered input voltage of the PFC. Maximum amplitude of the ramp voltage in the PFC controller. Minimum value of the voltage across M1 during valley occurrence. Output voltage of the PFC. Sensing voltage for overcurrent protection. Voltage that is derived from the PFC auxiliary winding. Driving voltage of M1 . Input voltage of the PFC driver. Output voltage of the PFC oscillator. Scaled output voltage of the PFC. Output voltage of the valley-detection circuit. Reference voltage of the PFC controller. Angular frequency of the mains voltage. I. I NTRODUCTION

S

UBSEQUENT to the introduction of line-current harmonic standards such as the IEC 61000-3-2, power-factor correction (PFC) converters have been widely used as preregulator stages to obtain fine regulation of the input current harmonic content [1], [2]. Although such a strategy allows obtaining higher power factor and lower current harmonic distortion, the

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power system suffers from complexity and cost due to the need for suitable control techniques [3], [4]. This issue is particularly taken into account when high-performance, low-cost, and lowsize applications need to be designed [5]. For instance, digitalvideo-disk recorders, monitor and television power supplies, and notebook adapters represent large-volume applications that demand low component count and cheap control circuitries. Based on this consideration, it is desirable to integrate the control functions necessary for the PFC stage and for the dc–dc converter in a system-on-chip–application-specific-integratedcircuit (SoC–ASIC) solution, providing for a reliable design of the power system. Moreover, in the aforementioned applications, flyback converters are strongly recommended over other topologies due to their lower component count and simple circuit topology. As the efficiency of the ac–dc power converter is of concern, a new switching technique has been proposed in recent years, which permits reducing the turn-on switching losses of the power devices. Such a technique, namely, valley switching, is suitable for a large variety of power converters due to its high versatility [6], [7]. In [8], a biflyback single-stage PFC converter based on the valley-switching technique has been implemented. It has been shown that valley-switching technique that is applied to two integrated flyback circuits allows reaching a higher power factor, along with high efficiency and low total harmonic distortion (THD). By adopting the choice of a double-stage power converter, valley-switching technique that is applied to both the power cells allows obtaining even higher efficiency levels. In fact, different from single-stage power converters, the rms current through the cells’ transformers is lower, with significant benefit on the cores’ sizes. The valleyswitching technique is suitable for discontinuous conduction mode (DCM) operation, where the power switches of the power cells are driven into quasi-resonant (QR) mode. This permits obtaining a significant decrease of the switching losses that are experienced at turn-on with considerable advantages in terms of efficiency. A drawback that is related to this technique is a higher harmonic distortion level due to the shaping of the input line current that is operated by the valley-switching control. However, it can be shown that an ac–dc converter that is based on this control still meets class-D standards with harmonic content within the limits. Based on the considerations drawn previously, the valley-switching technique is suitable for lowpower low-cost applications complying with THD standards, and, on this respect, the realization of an on-chip solution implementing this concept deserves careful attention. Design of ASIC controllers represents a key point for the realization of highly efficient power-conversion applications and optimal motor control [9]–[20]. Since the large signals of the power-conversion stage induce disturbances onto the small signals of the control system, several challenges are posed to device and application engineers. This is particularly true when the power converter comprises two asynchronous stages, such as PFC and dc–dc converters, causing interference problems among their respective controllers. A solution to this trouble envisages adoption of a high-voltage-compatible Bipolar Complementary metal–oxide–semiconductor/Diffused metal–oxide–semiconductor (BCD) technology to design and

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integrate on-chip the controllers of the PFC and dc–dc converters [21]. This is the approach that has been followed in this paper. This paper deals with a new ASIC controller that is suitable for a double-stage ac–dc power converter that is composed of a PFC cell and a flyback converter, and devoted to switch-modepower-supply applications. The proposed controller is based on a high-voltage-compatible BCD process and implements the concept of valley switching to reduce the turn-on switching losses that are charged onto both the power devices of the PFC and flyback converters. The PFC cell is controlled with constant on-time over one mains cycle and by limiting the switching frequency at current zero crossing by valley skipping. With reference to the flyback converter, current peak control is performed by the proposed ASIC device. In addition, QR mode is combined with valley skipping to limit the switching frequency of the flyback cell. A large number of functions are performed by the proposed SoC–ASIC controller, such as output-voltage regulation of the PFC and flyback stages, inputvoltage compensation, soft start to prevent audible noise of the transformer, burst mode of the PFC converter, overcurrent and overvoltage protection. As to the state of the art, existing solutions of on-chip controllers for two-stage power converters can be found in [22] and [23]. In [22], an IC controller that is devoted to PFC-forward combo systems has been proposed. However, [23] has been considered as a reference in this paper since dealing with an ASIC controller that is suitable for PFC–flyback-based power converters. Accordingly, such a solution has been compared with the one presented in this paper in the same application. This paper is organized in the following way. In Section II, the SoC–ASIC controller is presented and discussed, giving emphasis to its constituent parts and on the layout design. Both the PFC and flyback controllers that are internal to the ASIC are analyzed, in detail, in correlation with the power-frequency characteristics of the ac–dc converter. Accordingly, the mechanism of valley-switching skipping that is implemented by the ASIC is explained. In Section III, experimental results concerning the switching waveforms of the converter are presented, discussing the efficiency and output transient response, which was carried out for the application under consideration. Section IV deals with mains harmonic reduction (MHR) in correlation with current shaping due to the valley-switching technique. On this respect, the power factor and THD features of the power system are discussed by means of simulation runs and experimental analysis. In Section V, an experimental analysis has also been performed with regard to the conducted electromagnetic interference (EMI) noise that is generated by the ac–dc rectifier under valley-switching conditions. Finally, a summary is given in Section VI. II. T ECHNOLOGY AND F UNCTIONALITIES OF THE S O C–ASIC C ONTROLLER The integrated structure of the ASIC device combines a controller for the boost PFC cell of the ac–dc power converter and additional circuitry that is devoted to the control of the flyback converter. Both the PFC and flyback controllers

implement valley switching, looking for a reduction of the turn-on losses. This involves the two power cells operating in QR/DCM, and according to a policy of limiting on-time, variable switching-frequency control has been implemented. Valley-switching technique is performed with variable switching frequency by applying valley skipping, which means that the controller waits for some oscillations of the MOSFETs’ drain voltages before turning on the two switches. This is the strategy by which the output power of the ac–dc converter is regulated. In Fig. 1, the block diagram that is relative to the IC controller is shown, as well as the power stage. As observable in Fig. 1, the driving signals of the PFC and flyback switches, i.e., M1 and M2 , are generated by the PFC and flyback controllers, respectively, using an auxiliary control section that is placed as an interface between the two former ones. To implement valley-switching control, the voltage across the input inductor of the PFC converter is sensed through an auxiliary winding, obtaining the signal VPFC,AUX . As long as the flyback controller is concerned, the demagnetization of transformer T2 is detected through the signal VFB,DEM that is generated by an auxiliary winding. The drain voltage of the flyback switch is also sensed by the high-voltage signal VFB,SENSE to detect the valley of the voltage oscillation that is subsequent to the demagnetization of T2 . Mains compensation is realized by sensing input voltage VIN,PFC , which is properly attenuated, giving rise to the signal VIN,SENSE . Output-voltage regulation of the PFC is achieved by sensing VO,PFC after conversion into the signal VPFC,SENSE . A compensation network that is tied to the ICOM P pin of the IC device is employed. The output voltage of the flyback converter is regulated by a feedback circuit that is suitable for offline applications. The feedback circuit is interfaced with the proposed IC device and provides the control signal VFB,CTRL . The overcurrent protection of M1 and M2 is realized by detecting the voltages, which are both referred to as VOCP,SENSE , across the sensing resistors in the MOSFETs’ sources. A. Overview of the ASIC Technology As previously mentioned, the proposed SoC–ASIC is based on BCD technology, which allows sensing, by a high-voltagecompatible process, the high-voltage signals of the power stage. The chip is assembled in an SO16 package, where a lowvoltage and a high-voltage die are interconnected, as shown in Fig. 2. The two dies have a size of 4.8 and 0.9 mm2 , respectively, and are interconnected by using a Cu/NiPdAu lead frame. An external voltage of up to 650 V can be applied to the high-voltage die, enabling the generation of an internal current source that is used to supply the ASIC. A distance that is higher than 500 µm has been enforced between the low- and high-voltage dies for safety reasons and to avoid interactions between the two sections. The ball-bonding technique has been employed to contact the chip pads. The use of ball bonding is due to the large number of functionalities and the small size of the ASIC, where smaller bond pads and closer bondpad spacing have to be concerned. Moreover, the wire-bonding technique has been considered due to its economic advantage and strong resistance to sweeping.


Fig. 1.

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Block diagram of the proposed ASIC along with the ac–dc power converter stage.

Fig. 2. Chip photograph of the SoC–ASIC. (left) Low-voltage die of the ASIC. (right) High-voltage die that is used to sense the high-voltage signals of the power converter.

B. Valley-Switching Technique and Varied Switching-Frequency Control With reference to Fig. 3, the valley-switching technique is based on the demagnetization of the flyback transformer and the voltage oscillation in the drain node due to the magnetizing inductor Lm and the parasitic capacitances of MOSFET M2 , i.e., CDS,2 and CGD,2 . According to Fig. 4(a), when the secondary current of the flyback converter, which is referred to as IS , decreases to zero during the secondary stroke, the magnetic core is completely demagnetized. This enables voltage ringing in the drain node of the MOSFET with frequency fring,2 =

Fig. 3. Flyback-converter circuit with evidence of MOSFET parasitic capacitances and transformer inductances.

(1/(2π Lm (CGD,2 + CDS,2 ))), as well as oscillation of drain current IP (Fig. 3). The MOSFET is turned on when the drain voltage experiences a valley, and accordingly, it starts conducting in zero-voltage conditions with a switching loss that is given by 2 fring,2 , where Ceq,2 is the sum of Pon,ZVS = (1/2)Ceq,2 VDS,2 the MOSFET capacitances. Fig. 4(b) shows the power-frequency characteristics of the flyback converter, which are determined by the proposed ASIC controller. Since the switching frequency is limited, valley locking is implemented to avoid audible noise of the transformer. For instance, when the output power increases and the flyback

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converter is moved to QR mode with valley skipping. To avoid instability problems, valleys are locked by using a hysteresis characteristic, as evident in Fig. 5. This prevents the transformer from ringing due to the low-frequency harmonic that is added into the spectrum of VDS,2 . When the output power decreases further and the MOSFET’s peak current Ipk,2 reaches the minimum value Ipk_ max,2 /4, the switching frequency is decreased linearly and is allowed to decrease from below fs_ min,2 down to zero. Fig. 6 is considered to determine the frequency window where the ASIC operates by performing valley skipping. Such a frequency window is determined in such a way that, when the maximum frequency fs_ max,2 is reached along the nth valley characteristic, the corresponding power Pn is lower than Pn+1 , i.e., the power at the minimum frequency fs_ min,2 along the (n + 1)th valley curve. By supposing that the flyback operates along the nth valley characteristic, it is possible to express the switching period time as Ts,2 = Ton,2 + Toff,2 + Tring,2 =

Lm Ipk,2 Lm Ipk,2 + + (2n − 1)π Lm Ceq,2 VO,PFC N VOUT

(1)

where Lm , Ceq,2 , VOUT , and VO,PFC have been referred in Fig. 3 and N is the transformer turns ratio. In (1), Ton,2 , Toff,2 , and Tring,2 are the on-time, off-time, and ringing time of the flyback converter, respectively. Accordingly, the peak-current value Ipk,2 can be calculated as

Ipk,2

Fig. 4. Valley-switching technique with varied switching frequency control: (a) waveforms, in principle, of the flyback converter and (b) power-frequency characteristic of the flyback converter.

converter is initially in the third valley, the ASIC controller will force the converter to skip to the second valley if the switching frequency reaches the minimum operative frequency fs_ min,2 . A further skip will be performed from the second to the first valley if the output power continues to increase. To decrease the output power, the controller will cause the flyback converter to skip from the first to the second valley and, successively, from the second to the third valley when the maximum operative frequency fs_ max,2 is reached. In Fig. 4(b), the maximum limit of the output power that is associated with the maximum peak current of the MOSFET, i.e., Ipk_ max,2 , is also reported. Such a limit is provided to prevent transformer saturation. In Fig. 5, the full power-frequency characteristic of the flyback converter with implementation of the valley-switching technique is depicted, showing the operative waveforms in three different modes. At high power level, the ASIC controller drives the flyback into QR mode, while for lower power, the

Ts,2 − (2n − 1)π = 1 Lm VO,PFC +

Lm Ceq,2 .

(2)

1 N VOUT

By using (2), the output power of the system is given by the following equation: 

Ts,2 − (2n − 1)π 1 Pn = Lm  1 2 Lm VO,PFC +

2 Lm Ceq,2  fs,2 .

1 N VOUT

(3)

In a similar way, the power correspondingly to the (n + 1)th valley characteristic can be calculated as

Pn+1

 2 Ts,2 + [4π − (2n − 1)π] Lm Ceq,2 1  = Lm  1 2 L + 1 m

VO,PFC

·

N VOUT

Ts,2 + 4π

1

Lm Ceq,2

.

(4)

By imposing Pn+1 ≥ Pn , it can be found in case Ts,2 > 2Tring,2 = 4π

Lm Ceq,2

(5)


Fig. 5.

Fig. 6.

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Full-power frequency characteristic of the flyback converter.

Reference picture that is used to calculate the frequency window.

that the following condition has to be satisfied: fs,2
1, and Ipk,1 < Ipk,crit . No secondary stroke occurs, and accordingly, no power is converted from the input to the output of the PFC. • Case 3: (VO,PFC /2VIN ) > 1, and Ipk,1 ≥ Ipk,crit . A secondary stroke occurs, and power conversion is possible. Now, the expression of the input current is derived relatively to Case 1. It is worth observing that Ton,1 is a control parameter that is set by the PFC controller that is shown in Fig. 10.

Tring,1 = 2mπ

LIN Ceq,1 .

(13)

Accordingly, the switching period of the PFC converter is Ts,1 = Ton,1 + Toff,1 + Tring,1

(14)

where rise time Tr,1 and fall time Tf,1 have been neglected. Finally, the input current of the ac–dc converter during the PFC switching period is obtained by averaging IL over Ts,1 , as illustrated in Fig. 17 and in the following: (Ton,1 , m, VO,PFC , VIN (t)) IIN

=

Ipk,1 Ton,1 + Toff,1 , 0 ≤ t ≤ Ts,1 . 2 Ts,1

(15)

In (15), it can be observed that the input current is a function of the PFC on-time, number of valleys, input voltage, and output voltage. As previously discussed, the input current that is represented by (15) refers to Case 1, and in


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accordance with this, the expressions of current IIN (Ton,1 , fs_max,1 , VO,PFC , VIN (t)) in Case 2 and Case 3 (not reported in this paper) have been derived. The total input current that is extended to the complete mains cycle has been thus obtained. Here, fs_ max,1 represents the maximum switching frequency of the PFC, as will be discussed in the next section. Aiming to calculate the harmonics content of the input current, a Fourier analysis of the mains current over one complete period has been performed. Given the Fourier series expansion IIN (Ton,1 , fs_ max,1 , VO,PFC , VIN (t)) =

∞

cn ejnωt

(16)

n=−∞

cn represents the nth-order coefficient of such a series expansion and depends on Ton,1 , fs_ max,1 , and VO,PFC (since IIN does). By applying the Fourier transform to the mains current F (jω, Ton,1 , fs_ max,1 , VO,PFC ) TL = IIN (Ton,1 , fs_ max,1 , VO,PFC , VIN (t))e−jωt dt

(17)

0

cn can be derived by the following equation: cn =

1 F (jnωL , Ton,1 , fs_ max,1 , VO,PFC ), TL

n = 1, 3, 5, . . . . (18)

Equation (18) is now used to simulate the harmonics content of the mains current.

Fig. 18. (a) Mains input voltage and (b) input current shaping by the valleyswitching control.

B. Simulation Result Derivation by the Proposed Model In Fig. 18(a) and (b), calculations referring to the mains voltage and the input current based on the previously discussed model are shown, respectively. For this simulation, it has been assumed that the power of the converter is 120 W. As it can be possibly observed in Fig. 18(b), the current starts increasing from zero with a sinusoidal shape and then exhibits a jump due to the skip from the third to the second valley. The current continues, hence increasing with a sinusoidal shape until a further valley skip is performed. When the input current decreases, valley skips are performed in the reverse order than in the rising edge. By looking at Fig. 18(b), it can be argued that the harmonics content of the input current will contain high-frequency components, which contribute to the THD in a nonnegligible way. In Fig. 19, it can be noticed how the switching frequency changes during half mains cycle under valley-skipping conditions. It is shown that to maintain the switching frequency below 140 kHz, which is the value of fs_ max,1 , the converter needs to start switching in correspondence to the third valley, from 0 up to 2.5 ms. Then, a valley skip is performed [Fig. 19 (point a)], and the converter moves along the second valley characteristic to skip again after 3.3 ms to the first valley curve [Fig. 19 (point b)]. The opposite behavior is exhibited by the control [Fig. 19 (points c and d)], at the completion of the first half mains cycle. From this analysis, it can be concluded that at least three valleys are required to

Fig. 19. Switching frequency as a function of the drain-voltage valleys and mains voltage: (a) skip from the third to the second valley, (b) skip from the second to the first valley, (c) skip from the first to the second valley, and (d) skip from the second to the third valley.

limit the switching frequency below 140 kHz, although this will affect the THD level. An analysis of the harmonics content that is associated with the mains current has been carried out by resorting to (18), which gives the amplitude of the nth-order harmonic component. Simulation result derivation by such an analysis is

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Fig. 20. Harmonics content of the mains current under valley-switching conditions.

Fig. 21. Mains voltage and input current in full-load conditions at (a) VIN = 110 Vac and (b) VIN = 230 Vac.

shown in Fig. 20, where Frel (n) and MHRnorm (n) are the amplitudes of the nth harmonic component that is normalized to the fundamental one and its relative limit according to class-D standards (VIN = 230 Vac), respectively. By visual inspection, it emerges that, for all the considered harmonics, Frel (n) is lower than MHRnorm (n) with a satisfactory margin, hence conferring validity on the approach proposed in this paper. C. Experimental Analysis of the THD and Power Factor Some experimental results of concern with the input current shaping due to the valley-switching technique are reported in Fig. 21(a) and (b). Fig. 21(a) refers to an input voltage of 110 Vac, where, apart from discontinuities that are close to the zero-current crossing, a pure sinusoidal shape can be recog-

Fig. 22.

THD of the ac–dc converter for three steps of the mains voltage.

Fig. 23.

Percentage of the class-D limit at VIN = 110 and 230 Vac.

nized. In Fig. 21(b), the input current is shown with reference to an input voltage of 230 Vac. As clearly emerging, the shape of the input current is very similar to the simulated one that is reported in Fig. 19(b). To quantify the THD level that is associated with this current shaping, some measurements at three steps of the mains voltage are proposed in Fig. 22. The minimum THD is reached at VIN = 90 Vac in all the power range. When the input voltage increases up to 110 Vac, a 5% THD increase is observed. At 230 Vac, the THD, which refers to the current shape of Fig. 21(b), is nearly 34% at full load. In Fig. 23, the harmonic content of the input current is expressed as the percentage of the class-D limits that are reported in the IEC 61000-3-2 standards. Such percentages are lower than the maximum allowed one, reaching peak values of 62% at the highest harmonic. As a consequence, ac–dc power converters using the valley-switching technique are in conformity to the aforementioned standards. Finally, the power factor that is relative to the three steps of the mains voltage is reported in Fig. 24. It is shown that, at 230 Vac, the power factor at full load is close to 91%, giving a good result. At higher mains voltages, the power factor is also higher than 97%, thus achieving excellent results. D. Comparison of Performances of Fixed-Frequency and Valley-Switching Control Compared with the PFC/flyback ASIC that is referred to in [22], where the PFC and flyback controllers are assembled


Fig. 24. Power factor of the ac–dc converter for three steps of the mains voltage.

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Fig. 25. Experimental setup that is adopted to carry out quasi-peak and average EMI-noise measurements in the proposed ac–dc rectifier.

TABLE II PERFORMANCE COMPARISON OF THE TWO CONTROL TECHNIQUES

on the same chip but in distinct dies, the solution proposed in this paper integrates the two controllers in the same die. This means that there is no need for external hardware to communicate between the two controllers and for high immunity to switching noise because of the shorter signal paths. Moreover, more functions have been implemented in the ASIC presented in this paper, such as soft start for both the PFC and flyback to reduce the current stress that is charged onto the switches. Additional functions include protection against open-controlloop situation in both converters and relative overvoltage protection. Regarding the comparison of the performances that are relative to the two solutions under study, it is worth observing that such performances rely more on the implemented control technique rather than on the ASIC device. As a matter of fact, the ASIC proposed in this paper implements valley-switching control for both the PFC and flyback, while the counterpart that is used in this comparison operates the two converters at a fixed switching frequency under hard-switching conditions. Accordingly, improved efficiency, and lower THD and power factor are inherent to the valley-switching technique, as reported in Table II. V. EMI P ERFORMANCE OF THE AC–DC R ECTIFIER Owing to the QR commutation characteristic that is exhibited by the valley-switching control, dV /dt at turn-on of the PFC and flyback switches is considerably reduced [24], [25]. As a matter of fact, the MOSFETs will turn on with lower voltage, hence allowing a decrease of the noise that is generated by their switching activities. Based on these considerations, an experimental analysis that is focused on the conducted EMI noise that is produced in the ac–dc rectifier has been performed. In Fig. 25, the measurement setup that is adopted to detect the conducted quasi-peak and average common-mode EMI noise

Fig. 26. Conducted common-mode EMI noise generated by the ac–dc rectifier. The dashed line represents the upper-bound limit for quasi-peak EMI noise according to international standards. The dotted–dashed line represents the upper-bound limit for average EMI noise.

of the power converter is illustrated. A line impedance stabilization network is inserted between the ac mains and the input line of the ac–dc rectifier. This allows decoupling the highfrequency low-voltage switching noise from the low-frequency high-voltage signal at the input of the converter. The conducted common-mode EMI noise is thus measured by averaging voltages VX and VY across the 50-Ω resistors. This is implemented by the EMI analyzer in Fig. 25, which scans step by step in the considered frequency range the quasipeak and average noise in the converter under test. The experimental results that are obtained by the measurement setup described previously are plotted in Fig. 26. The first trace from the top of the figure represents the upper-bound limit for quasipeak EMI noise according to international standards [26]. Then, the upper-bound limit for average EMI noise follows. Finally, the third and fourth curves from the top are the quasi-peak and average common-mode EMI voltages that are generated in the ac–dc rectifier, respectively. As shown in the figure, the two measurements are within their respective upper-bound limits,

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with a satisfactory margin in all the frequency range. To obtain these results, a transformer structure that is made of shielded primary- and secondary-winding layers has been realized. By this way, the coupling capacitances between the primary and secondary sides of the magnetic have been reduced. In this experiment, a 470-pF Y-cap capacitor that is placed between the ground references of the flyback input and output circuits has been used. VI. C ONCLUSION In this paper, a SoC–ASIC controller that is suitable for a double-stage ac–dc power converter that is based on PFC and flyback cells has been presented. Both the PFC and flyback stages are controlled by two distinct sections of the ASIC, aiming to integrate in a unique solution the control, driving, and protection functions of the two converters. The proposed IC implements the valley-switching technique to attain lower turn-on power losses than that in conventional PWM control. The SoC–ASIC has been described by discussing some integration issues. The PFC and flyback controllers have been analyzed in detail, along with their switching waveforms. An experimental analysis of the ac–dc converter comprising efficiency, THD, and power-factor measurements has been carried out to confer validity on the approach followed in this paper. It has been shown that, in comparison with conventional PWM control, the power converter features an efficiency of 97% at 230 Vac, with a power factor of 91% and a THD of 34%. It has also been observed that the class-D limits that are contained in the IEC 61000-3-2 standards are met by the proposed ASIC solution. Finally, the EMI performances of the presented ac–dc rectifier have been analyzed, carrying on some measurements of the conducted common-mode EMI noise in the converter.

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ACKNOWLEDGMENT The authors would like thank H. Halbestardt of NXP Semiconductors, Nijmegen, The Netherlands, for his valuable contribution to the design of the SoC–ASIC, and Dr. H. Regtop of the Electromagnetics Cooling Competence Center, Philips Applied Technologies, Eindhoven, The Netherlands, for performing the EMI experimental tests. R EFERENCES [1] C. M. Wang, “A novel ZCS–PWM power-factor preregulator with reduced conduction losses,” IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 689–700, Jun. 2005. [2] R. M. F. Neto, F. L. Tofoli, and L. C. de Freitas, “A high-power-factor half-bridge doubler boost converter without commutation losses,” IEEE Trans. Ind. Electron., vol. 52, no. 5, pp. 1278–1285, Oct. 2005. [3] R. Zane and D. Maksimović, “A mixed-signal ASIC power-factorcorrection (PFC) controller for high frequency switching rectifiers,” in Proc. 30th Annu. IEEE Power Electron. Spec. Conf., Charleston, SC, Jun. 27–Jul. 1, 1999, pp. 117–122. [4] A. K. S. Bhat and R. Venkatraman, “A soft-switched full-bridge singlestage AC-to-DC converter with low-line-current harmonic distortion,” IEEE Trans. Ind. Electron., vol. 52, no. 4, pp. 1109–1116, Aug. 2005. [5] S. Buso, G. Spiazzi, and D. Tagliavia, “Simplified control technique for high-power-factor flyback cuk and sepic rectifiers operating in CCM,” IEEE Trans. Ind. Appl., vol. 36, no. 5, pp. 1413–1418, Sep./Oct. 2000. [6] L. Huber and M. M. Jovanovic, “Single-stage, single-switch inputcurrent-shaping technique with reduced switching loss,” in Proc. 14th

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Annu. IEEE Appl. Power Electron. Conf. and Expo., Dallas, TX, Mar. 14–18, 1999, pp. 112–118. Y. Panov and M. M. Jovanovic, “Adaptive off-time control for variablefrequency, soft-switched flyback converter at light loads,” in Proc. 30th Annu. IEEE Power Electron. Spec. Conf., Charleston, SC, Jun. 27–Jul. 1, 1999, pp. 457–462. W. Qiu, W. Wu, K. Rustom, H. Mao, and I. Batarseh, “Bi-flyback singlestage PFC converter with valley switching technique,” in Proc. 34th Annu. IEEE Power Electron. Spec. Conf., Acapulco, Mexico, Jun. 15–19, 2003, pp. 803–807. G. Marent and S. Zudrell-Koch, “Novel electronic ballast with integrated digital power factor controller,” in Proc. 38th IEEE Ind. Appl. Soc. Annu. Meeting, Salt Lake City, UT, Oct. 12–16, 2003, pp. 791–798. J. A. Pozas, L. Perez, J. Gonzalez, and J. L. Conesa, “Highly integrated dual programmable DC/DC converter for control applications,” in Proc. 21st IEEE Int. Conf. Ind. Electron., Control, Instrum., Orlando, FL, Nov. 6–10, 1995, pp. 296–299. D. Killat, J. Schmidt, A. Baumgaertner, R. Baraniecki, and O. Salzmann, “On-chip solution in 0.35 µm standard CMOS for electronic ballasts for fluorescent lamps,” in Proc. IEEE Int. Symp. Syst.-on-Chip, Tampere, Finland, Nov. 19–21, 2003, pp. 23–26. M. N. Cirstea, M. Giamusi, and M. McCormick, “A modern ASIC controller for a 6-pulse rectifier,” in Proc. 10th Annu. IEEE Int. ASIC Conf. and Exhib., Rochester, NY, Sep. 7–10, 1997, pp. 335–338. C. K. Yao, W. C. Yu, and T. Y. Yu, “ASIC implementation of a programmable servo control IC with digital phase-locked loop,” in Proc. 33rd Annu. Power Electron. Spec. Conf., Charleston, SC, Jun. 23–27, 2002, pp. 558–563. F. F. Linera, J. Diaz, M. A. P. Garcia, and A. G. Soriano, “Design of an ASIC with CMOS 1.5 µ ES2 technology for emergency lighting systems with fluorescent lamp,” in Proc. 3rd Tech. Int. Power Electron. Congr., Cuernavaca, Mexico, Aug. 21–25, 1994, pp. 56–61. C. Kuratli, H. Qiuting, and A. Biber, “Implementation of high peakcurrent IGBT gate drive circuits in VLSI compatible BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 924–932, Jul. 1996. T. Riesgo, J. Sanchez, W. Schogler, W. Moshammer, V. Guerreiro, and J. L. Ramos, “ENERCHIP: An integrated circuit for power control,” in Proc. 21st IEEE Int. Conf. Ind. Electron., Control, Instrum., Orlando, FL, Nov. 6–10, 1995, pp. 662–667. J. M. Retif, B. Allard, X. Jorda, and A. Perez, “Use of ASICs in PWM techniques for power converters,” in Proc. 19th IEEE Int. Conf. Ind. Electron., Control, Instrum., Maui, HI, Nov. 15–19, 1993, pp. 683–688. A. M. Omar, N. A. Rahim, and S. Mekhilef, “Three-phase synchronous PWM for flyback converter with power-factor correction using FPGA ASIC design,” IEEE Trans. Ind. Electron., vol. 51, no. 1, pp. 96–106, Feb. 2004. G. K. Andersen and F. Blaabjerg, “Current programmed control of a single-phase two-switch buck-boost power factor correction circuit,” IEEE Trans. Ind. Electron., vol. 53, no. 1, pp. 263–271, Feb. 2006. J. X. Shen and S. Iwasaki, “Sensorless control of ultrahigh-speed PM brushless motor using PLL and third harmonic back EMF,” IEEE Trans. Ind. Electron., vol. 53, no. 2, pp. 421–428, Apr. 2006. W. Langeslag, R. Pagano, K. Schetters, A. Strijker, and A. van Zoest, “A high-voltage compatible BCD SoC–ASIC performing valleyswitching control of AC–DC power converters based on PFC and flyback cells,” in Proc. 32nd IEEE Int. Conf. Ind. Electron., Control, Instrum., Paris, France, Nov. 7–10, 2006, pp. 2996–3001. M. Herfurth and L. Lorenz, “Power factor and PWM controller TDA 16888,” in Proc. Power Convers. Conf., Nagaoka, Japan, Aug. 3–6, 1997, pp. 901–906. “PFC/PWM controller simplifies ac/dc power supply design,” On Semiconductors, Archive Press Release. [Online]. Available: http://news. thomasnet.com/fullstory/466770 N. Mutoh, J. Nakashima, and M. Kanesaki, “Multilayer power printed structures suitable for controlling EMI noises generated in power converters,” IEEE Trans. Ind. Electron., vol. 50, no. 6, pp. 1085–1094, Dec. 2006. L. H. S. C. Barreto, E. A. A. Coelho, V. J. Farias, J. C. de Oliveira, L. C. de Freitas, and J. B. Vieira, Jr., “A quasi-resonant quadratic boost converter using a single resonant network,” IEEE Trans. Ind. Electron., vol. 52, no. 2, pp. 552–557, Apr. 2005. International Electrotechnical Commission, “CISPR 16-1/(1999-10): Specification of radio disturbance and immunity measuring apparatus and methods, Part 1: Radio Disturbance and Immunity Measuring Apparatus,” pp. 1–13. [Online]. Available: www.iec.ch/news_centre/ onlinepubs/pdf/emc2002.pdf


Winston Langeslag was born in Nijmegen, The Netherlands, in 1970. He received the M.Sc. degree in electrical engineering from the University of Eindhoven, Eindhoven, The Netherlands, in 1994. In 1996, he joined Philips Lighting, where he was involved in the design of high-frequency lamp drivers. In 2001, he moved to Philips Semiconductors (now NXP Semiconductors), Nijmegen, where he was involved in the design of integrated circuits for offline switch-mode power supplies and has been a Project Manager since 2005. He is the holder of several patents on switch-mode power supplies and lamp drivers. His research interests include the development of IC controllers for different power applications.

Rosario Pagano (S’02–M’04) was born in Catania, Italy, on August 10, 1976. He received the Laurea degree and the Ph.D. degree in electronic engineering from the University of Catania, Catania, in 2001 and 2005, respectively. In 2004, he concluded his Ph.D. studies at the University of California, Irvine. In 2002, he was a Visiting Scholar at the University of Illinois at Chicago. Since the summer of 2005, he has been with Philips Semiconductors (now NXP Semiconductors), Nijmegen, The Netherlands, first as an Application Engineer and then as a VLSI Designer for power-management applications. He is the holder of one U.S. patent. His research interests include power-device modeling and characterization, power converters, mixed-signal ICs, and digitally based control of power converters. Dr. Pagano is a member of the IEEE Power Electronics Society and the IEEE Circuits and Systems Society. In 2003, he was a Fellow of the Italian National Council of Research (CNR).

Kees Schetters was born in Halsteren, The Netherlands, on March 20, 1972. He received the M.Sc. degree in electrical engineering from Eindhoven University of Technology, Eindhoven, The Netherlands, in 1998. He has been with NXP Semiconductors, Nijmegen, The Netherlands, as a Development Manager since 2005. Before joining NXP Semiconductors, he held various functions in the field of power electronics. He is the holder of five patents. His research interests include power electronics in general and business development.

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Arjan Strijker was born in Dedemsvaart, The Netherlands, in 1966. He received the M.Sc. degree in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1991. In 1995, he joined Philips Semiconductors (now NXP Semiconductors), Nijmegen, The Netherlands, where he was involved in the design of integrated circuits for offline switch-mode power supplies and has been a Project Manager since 2001. He is the holder of several patents on switch-mode power supplies. His research interests include the development of IC controllers for highly energy-efficient switch-mode power supplies with low standby power for consumer applications.

Arjan van Zoest was born in Utrecht, The Netherlands, in 1964. He finished his technical education in electronics in 1984 and received the Bachelor degree in commerce from the University of Applied Sciences of Utrecht, Utrecht, in 1995. From 1985 to 2001, he was with Siemens, where he held various functions. In 2001, he joined Philips Semiconductors (now NXP Semiconductors), Nijmegen, The Netherlands, where he is currently an Application Engineer and is involved in the development of several ICs for offline flyback controllers. His research interests include smart power products.