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MUFFAKHAM JAH COLLEGE OF ENGINEERING AND TECHNOLOGY ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT Course Code : EC 402 Course Title : VLSI DESIGN Year and Semester : IV Year I Semester Contact Hours per week : 4+1(Tutorial) Course Coordinator : MD.ZAKIR HUSSAIN, Asst.Prof. Course Coordinator Phone : 9949-426-362 Course Coordinator Email :
[email protected] Course Coordinator URL : http://tinyurl.com/zakirhussain-eced Course Coordinator Location : Room No. 5405 Course Coordinator Availability:
Day Wednesday Friday Saturday
Pre-lunch 9:10-12:40 10:30-12:40
Post-lunch 12:40-4:00 -
I. PRE-REQUISITE COURSES AND ASSUMED KNOWLEDGE AND CAPABILITIES: 1. BE I YEAR SUBJECTS CS 101- PROGRAMMING IN C & C++ CS 131- PROGRAMMING LAB 2. ECE III YEAR,I SEMESTER ECE 302-DIGITAL INTEGRATED CICUITS AND APPLICATIONS II.
COURSE DESCRIPTION:
This course covers the use of Verilog HDL in high-level synthesis of digital system designs. The language Verilog HDL as well as how it is used for describing, modeling, simulating and synthesizing various digital modules will be addressed. Verilog HDL coding and synthesis issues on combinational and sequential modules including Finite State Machine will be discussed. The course will also cover the basic theory and techniques of digital VLSI design in CMOS technology. III. COURSE OUTCOMES: On completion of this module the student will be able to: 1.
Describe various Verilog HDL data types, explain system tasks and compiler directives and be able to write gate level and data flow level modeling
2.
Describe behavioural modeling, switch level modeling. Explain Timing control, Conditional statements, Sequential and Parallel Blocks, Generate Blocks. Differentiate between Tasks, Functions. Model Mealy and Moore state models using Verilog.
3.
Describe Basic MOS Transistor action: and Basic electrical properties of MOS. Infer MOS inverters with different loads, Basic Logic Gates with CMOS
4.
Explain the MOS and CMOS circuit Design Process.
5.
Infer Combinational Logic, Sequential Logic
IV.
OVERVIEW OF LEARNING ACTIVITIES: 1. Lectures and class discussions 2. Quizzes 3. Seminars 4. Assignments
V.
OVERVIEW OF LEARNING RESOURCES:
A. Suggested Reading: 1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, 2/e , Pearson Education, 2008. 2. Michael D. Ciletti, “ Advanced Digital Design with Verilog HDL”, PHI, 2005. 3. Kamran Eshraghian, Douglas A. Pucknell, and Sholeh Eshraghian, “Essentials of VLSI circuits and systems”, PHI, 2011. 4. John P. Uyemura, “Introduction to VLSI Circuits and systems”, Wiley India Pvt.Ltd., 2011. B. Supplementary Reading: 1. “Design Through Verilog Hdl” , T.R. Padmanabhan, B.Bala Tripura Sundari 2. “Introduction to VLSI Circuits and Systems” , John P. Uyemura 3. “Fundamentals of Digital Logic with Verilog Design” , Zvonko G Vranesic VI.
FREELY ACCESSIBLE INTERNET SITES : SL.NO. 1. 2. 3.
VII.
TITLE VLSI Circuits -- Prof. S. Srinivasan VLSI Technology -- Dr. Nandita Dasgupta Electronic Design and Automation
OVERVIEW OF ASSESSMENT
I. Internal assessment for this course comprises of
II.
1. Class tests 2. Quizzes 3. Assignments External assessment for this course comprises of 1.
University Exam
RESOURCE LINK http://nptel.ac.in/courses/117106092/ http://nptel.ac.in/courses/117106093/ http://goo.gl/Uak4iY
