Wafer Level Embedding Technology for 3D Wafer Level Embedded ...

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Wafer Level Embedding Technology for 3D Wafer Level Embedded Package Aditya Kumar1*, Xia Dingwei2, Vasarla Nagendra Sekhar1, Sharon Lim1, Chin Keng1, Gaurav Sharma1, Vempati Srinivas Rao1, Vaidyanathan Kripesh1, John H. Lau1,3, Dim-Lee Kwong1 1 Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685 [email protected], Tel: (65) 67705438; Fax: (65) 67745747 2 Kinergy Ltd, TECHplace II, Ang Mo Kio Ave. 5, Singapore 569871 3 Now with Hong Kong University of Science & Technology Abstract This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve reliable 3D EMWLP. Several molding process issues, such as warpage, die-sweep, EMC penetration, and die-shift, were faced during embedding process development. A large warpage of more than 1 mm and die-shift of more than 600 m were found to occur in reconstructed molded wafer. Wafer level embedding process was optimized to reduce warpage and die-shift problems. A significant reduction in warpage (~ 30 %) and die-shift (~ 88 %) were achieved after embedding process optimization. The detail of process optimization is presented in the paper. Reconstructed molded wafers were subjected to various reliability tests, such as thermal cycle (TC), moisture sensitivity test-level 3 (MST-L3), and highly accelerated stress test (HAST). Scanning acoustic microscopy (SAM) analysis of molded wafers was carried out to analyze the void formation and delamination in molded wafers. No major void or delamination was observed in reconstructed wafer after molding as well as after reliability tests. 1. Introduction The demand of high functional electronic devices is driving the packaging industry to develop advance packages such as multi chip modules (MCM), system in package (SiP), system on package (SoP), and package on package (PoP). These advance packages not only enhance the functionality of system, but also provide other advantages, such as the integration of different device technologies, high performance, low cost, and small package size. The 2-D size of semiconductor package is decreasing continuously with the trend of miniaturization in very large-scale integrated (VLSI) device. Concurrently, the thickness of package is also decreasing to reduce the profile and weight of package. The package thickness is usually reduced by using thin semiconductor device die and/or thin substrate, however recently, a new type of package that is known as embedded wafer level package has been developed to reduce the size and cost and to increase the functionality and performance of package [1-4]. In this type of packages, semiconductor die is embedded inside the polymer and the interconnection between semiconductor die and BGA solder balls are realized

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with the help of redistributed metallization lines, thus eliminating the usage of wire-bonds, flip-chip bumps, and package substrate [3]. One of the limitations of EMWLP technology is an easy realization of 3D system in an EMWLP. In our previous work [5], we have presented the design and development of 3D EMWLP. In this paper, we are presenting the development of wafer level embedding process, which is used for 3D EMWLP. Several processes and materials issues and their solutions are discussed in this paper in depth. 2. 3D EMWLP Technology In EMWLP technology, the cost and size of package is reduced by eliminating wire-bonds, flip-chip bumps, and package substrate [3]. This is mainly realized by forming reconstructed molded wafer, which has multiple Si chips embedded in EMC. The functionality and performance of EMWLP package can be increased further by realizing 3D structure in EMWLP. A 3D EMWLP can be realized by integrating different conventional semiconductor fabrication and assembly processes [5]. Fig. 1 shows the process flow of 3D EMWLP. First, a molding tape is laminated on dicing ring. Then, multiple semiconductor dies having Cu posts at front or device side are placed on the molding tape. The dies are then embedded in EMC by using molding method. After molding, molding tape is removed from reconstructed molded wafer. Then, reconstructed molded wafer is grinded to expose Cu posts. Finally, depending upon requirements, redistributed metallization lines and/or solder bumps are fabricated on reconstructed molded wafer. Though EMWLP technology in general has a number of advantages over conventional packaging technology, there are several process challenges in making this technology suitable for mass-production. One of the most challenging processes in EMWLP technology is wafer level embedding and this is the process, whose requirements and limitations must be kept in mind by design and integration engineers while developing EMWLP. For a successful EMWLP technology, embedding process must be able to produce a reconstructed molded wafer, on which subsequent wafer level processes can be carried out easily. In this paper, we are mainly discussing the development of wafer level embedding process, the critical issues in embedding process and embedding material, and their possible solutions. An effort has been made to understand the process issues of wafer level embedding, which are critical for EMWLP technology.

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(f) Fig. 1. Process flow for fabricating 3D EMWLP: (a) laminating molding tape on a dicing ring, (b) placing multiple dies on the molding tape, (c) embedding dies in EMC, (d) removing molding tape from molded wafer, (e) grinding molded wafer to expose Cu posts, and (f) forming redistribution lines and/or bumps on molded wafer. 3. Embedding Process Development In semiconductor packaging, a number of embedding methods, such as transfer [5, 8], compression [2, 6], lamination [4, 9-10], printing [7, 8], coating [9], and potting [1], have been used to embed the semiconductor dies or wafer in polymer. These embedding methods are broadly characterized into two categories. The first is molding and the other is liquid encapsulation. Both of these embedding categories have their advantages and disadvantages. Normally molding processes, such as transfer, injections, and compression, offer a precise control on dimensions and high throughput, but they are expensive. On the other hand, liquid encapsulation methods, such as printing, potting, and casting, are of low cost, but they do not offer precise control on dimensions. Other than the embedding methods, the physical properties of embedding materials also play an important role in achieving reliable embedding of die or wafer. Since embedding materials are epoxy compounds, which usually have very high coefficient of thermal expansion (CTE) as compared to single crystal Si, a large amount of thermomechanical stress is developed in composite epoxy-Si structure after embedding process. To minimize thermomechanical stresses, normally two approaches are used for the selection of epoxy compound. The first approach is low CTE approach and the other is high CTE approach. In low CTE approach, the CTE of epoxy compound is decreased to match with the CTE of Si and this is done by adding a high amount

of filler particles in epoxy compound. The high filler content of epoxy compound reduces its CTE mismatch with Si and thus reduces thermo-mechanical stress. In high CTE approach, epoxy compound does not have high filler content and thus the Young’s modulus of epoxy compound is low. Due to low Young’s modulus, high CTE epoxy compound does not induce high thermo-mechanical stress in composite epoxy-Si structure. In present embedding process development, compressive molding method was selected due to its ability to mold a large area (8” diameter) with a precise control of mold thickness (< 20 µm). Fig. 2 is a schematic illustration of wafer level embedding process that was used to fabricate reconstructed molded wafer having multiple Si dies in EMC. In embedding process, first a granular EMC was spread evenly on the Si dies placed on a molding tape, which was mounted on a dicing ring. Then, EMC was covered with a mold release tape, which was mounted on another dicing ring. After that, both the dicing rings along with dies and EMC were placed on molding tool and then claming force was applied along with heat for a certain duration of time to melt and cure EMC. Finally, clamps were opened and the molding and mold release tapes were removed from the molded wafer. EMC

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(d) Fig. 2. Schematic illustration of wafer level embedding process. Three types of granular EMCs having different CTEs ranging from 5 ppm/C to 20 ppm/C were investigated with different molding conditions to select an appropriate molding condition and compound. Three EMCs, which are categorized into low CTE, medium CTE, and high CTE, and different molding conditions, which are tabulated in table 1, were analyzed in the present work. For embedding process development, Si dies of 7mm  7 mm  0.4 mm size were used and the thickness of reconstructed molded wafer was around 0.5 mm. Moldablity, wafer warpage, and void formation were evaluated after embedding process.

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Table 1. Molding compounds and conditions used for embedding process development. Molding Low CTE Medium CTE High CTE compounds Molding 175C2mins 175C2mins 175C2mins conditions 150C5mins 150C5mins 150C5mins 125C10mins 125C10mins 125C10mins A. Moldability Blanket molded wafers (without Si dies) were fabricated by using different molding compounds and molding conditions to investigate moldability. Moldability was investigated by analyzing the surface imperfections, such as voids and cracks, in molded wafers. It was found that all the three molding compounds, low CTE, medium CTE and high CTE, results in void-free smooth molded surface at 175C2mins and 150C5mins molding conditions. Fig. 3 shows the void-free smooth molded surface achieved at 150C5mins molding condition using low CTE material. However, at 125C10mins molding condition all three EMCs resulted in rough molded surface as shown in Fig. 4. Other than rough molded surface, the wafers molded at 125C10mins were weak and thus prone to crack during handling. From moldability study, it became clear that condition 125C10mins is not suitable for molding reconstructed wafer.

wafers having Si dies of 7mm  7 mm  0.4 mm size were molded using different molding materials and conditions shown in Table 1. The thickness of molded wafer was around 0.5 mm. Wafer warpage was measured using wafer mapping system (FSM). FSM uses non-contact infrared (IR) interferometric technique to generate a 2D map of wafer profile as shown in Fig. 5. The warpage measurement of reconstructed molded wafers revealed that the warpage varies in the range of 1100 µm to 1250 µm, irrespective of molding compound and condition. Further process optimization was carried out to reduce wafer warpage and their results will be discussed later.

Fig. 5. Warpage data of reconstructed wafer molded at 175C2mins using high CTE EMC. All data in µm.

Fig. 3. Optical image of wafer molded at 150C5mins using low CTE EMC, showing smooth molded surface.

Fig. 4. Optical image of wafer molded at 125C10mins using low CTE EMC, showing rough molded surface. B. Reconstructed Molded Wafer Warpage Warpage is a critical issue for EMWLP as it consists of a composite epoxy-Si structure, in which CTE mismatch is very large (5 – 15 ppm). For warpage measurement, reconstructed

C. Void Formation SAM analysis of reconstructed molded wafer was carried to investigate void formation during embedding process. Fig. 6 shows SAM images of reconstructed wafer molded at 150C5mins using medium CTE EMC. It can be observed that no major void formed in reconstructed molded wafer during embedding process. SAM analysis of reconstructed wafers, which were molded using other EMCs and molding conditions, revealed the same result. D. Reliability Analysis Reliability analysis of reconstructed molded wafers was carried out to confirm the integrity of composite epoxy-Si structure. Table 2 shows the reliability tests that were carried out on reconstructed molded wafer. After reliability test, SAM analysis was carried out to find any void or delamination in reconstructed molded wafer. Fig. 7 shows SAM images of the reconstructed wafer molded at 150C5mins using medium CTE material, after HAST reliability test. From the figure it is clear that no major void or delamination occurred in the reconstructed molded wafer during HAST. Similar results were observed in the

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reconstructed wafers molded using other molding materials and conditions, after reliability tests.

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(a) C-SAM (b) Thro-SAM Fig. 6. SAM images of multiple Si dies embedded in medium CTE EMC at 150C5mins. Table 2. Reliability tests that were carried out on reconstructed molded wafer. Reliability tests (Standard) Condition Thermal Cycle (JESD22-A104-G) -40 to 125C for 1000 cycles MST Level 3 (J-STD-20) 30C/60%RH for 192 h & 3Reflow HAST (JESD22-A118) 130C/85%RH for 96 h

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(b) Fig. 8 Optical and SAM images showing crack formation in the reconstructed wafers molded using (a) medium CTE and (b) high CTE EMCs.

(a) C-SAM (b) Thro-SAM Fig. 7. SAM images of multiple Si dies embedded in medium CTE EMC at 150C5mins, after HAST reliability test. E. Wafer Handling Handling problem like wafer creaking was observed in the case of reconstructed wafer molded using medium CTE and high CTE EMCs. Fig. 8 shows the cracks that occurred in the reconstructed wafers molded using medium CTE and high CTE EMCs. The formation of crack in medium CTE and high CTE EMCs can be understood due to their low mechanical strength as these EMCs have much smaller Young’s modulus than that of low CTE EMC. The CTE of an EMC depends upon their filler content. High filler content results in low CTE and high mechanical strength (Young’s modulus). Thus, the low filler content of medium CTE and high CTE EMCs results in low mechanical strength and thereby makes them more prone to crack during handling. Based on the results of embedding process development, two molding conditions, 175C2mins and 150C5mins, and low CTE EMC were selected for further embedding process optimization.

4. Embedding Process Issues and Optimization Several process issues, such as die-sweep, EMC penetration, die-shift, and high wafer warpage, were faced during wafer level embedding process development. Further embedding process optimization was carried out to solve these issues. The details of process issues and optimization are given in this section. A. Die-Sweep and EMC Penetration Wire-sweep is a common problem that occurs during molding of wire bonded package. In wire-sweep, wires move from their original position and if their movement is very large then they touch adjacent wires. A similar die-sweep phenomenon was observed in wafer level embedding, in which dies left their original positions and got embedded at different locations in molded wafer. Fig. 9a is an optical image showing die-sweep problem in a reconstructed molded wafer. It can be seen that several dies completely moved away from their original positions during embedding process. Another problem observed in the embedding of Si dies in EMC was EMC penetration. In this problem, as shown in Fig. 9b, EMC penetrated the interface between die and molding tape and thus covered a part of Si die.

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flowing EMC exerts a large displacement force on dies. Even if displacement force is not sufficiently large to move the die completely, it can help EMC to penetrate through the interface between die and molding tape. After understanding die-sweep and EMC penetration problems, it became clear that these problems can be solved by (1) increasing adhesion between die and molding tape by using high adhesion strength molding tape, (2) reducing claming speed, (3) reducing molding temperature, and (4) spreading molding compound on dies uniformly to slow down the flow of molten EMC. Since the first two solutions were limited to molding tape property and equipment, the last two solutions were tried to solve die-sweep and EMC penetration problems. It was found that, the die-sweep and EMC penetration problems can be solved by spreading EMC on dies uniformly and using low 150 C molding temperature (Fig. 9c).

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(c) Fig. 9. Optical images showing (a) die-sweep and (b) EMC penetration problems in reconstructed wafer molded at 175C2mins after placing EMC at the centre of molding tape and (c) reconstructed wafer molded at 150C5mins after spreading EMC on Si dies uniformly. Though die-sweep and EMC penetration problems seem different, but they both are related to the adhesion between die and molding tape. The molding tape used in embedding process development was a thermal release tape that losses its adhesive strength after heating at certain temperature for particular duration. Thus, the molding tape having releasing temperature much higher than molding temperature was used. However, there are a number of factors that can influence the adhesion between die and molding tape during molding process. The first is molding temperature. Though, the molding temperature is much less than the releasing temperature of molding tape, but low molding temperature also reduces the adhesion strength of molding tape due to long molding time. The second is claming speed. High claming speed results in the fast flow of EMC and then fast

B. Die-shift One of the biggest processing issues in EMWLP packaging technology is die-shift. In die-shift problem, die does not sweep completely from their original position, but it shifts slightly. This slight shift in dies creates problem for subsequent wafer processes, such as the formation of redistribution lines. To understand die-shift problem, dies of 5mm  5 mm size having aluminum pattern as shown in Fig. 10 were molded to form reconstructed molded wafer. After reconstructed wafer molding, the distance of each die located into two perpendicular directions of reconstructed molded wafer was measured from the centre of molded wafer. Fig. 11 shows the location and shift of each die from the centre of molded wafer. From the figure, it is clear that dies shift away from the centre of wafer and the die-shift could be up to a few hundred microns, making reconstructed molded wafer defective for subsequent processes. After analyzing molding process and molding material properties, it was found that such a large die-shift in outward direction could be a result of two phenomena. The first phenomenon is thermal expansion of polymeric molding tape due to its high CTE value (> 35 ppm/C) and high molding temperature. The second phenomenon is flow of molding compound from the centre to the edge of wafer during molding. These two phenomena together cause the dies to shift outward.

Fig. 10. Optical image of patterned Si die used for die-shift measurements. As molding is done at a certain temperature, the molding temperature cannot be lowered down than a certain temperature and it is also impossible to restrict the flow of

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molding compound during molding. Thus, to reduce die-shift problem, molding tape was stick to a carrier wafer to restrict the thermal expansion of molding tape during molding process. For this purpose, a molding tape having adhesive both the sides of tape was used. The one side of molding tape had thermal release adhesive and the other side had pressure sensitive adhesive. The pressure sensitive adhesive side of molding tape was mounted on a carrier and then Si dies were mounted on thermal sensitive side of tape. Fig. 11 shows the Si dies on the molding tape that is mounted on a carrier wafer. After molding with carrier wafer, as shown in Fig. 13, maximum die-shift was found to reduce significantly to 79 µm or by around 88 %. Another difference observed in this case was that die shifted towards the center of molded wafer. The reasons of die-shift towards the centre of wafer were found to be the cure and thermal shrinkages of EMC. The dies shifted towards the centre of wafer during molding due to the cure shrinkage in EMC and during mold cooling due to the thermal shrinkage in EMC. Although a huge reduction in die-shift can be achieved by using carrier wafer, further process and material optimization is need and being carried out to reduce die-shift to 25 µm.

Fig. 13. Die-shift data of reconstructed wafer molded at 150C5mins using low CTE EMC and carrier wafer. All data in µm. C. Reconstructed Molded Wafer Warpage Molding with carrier wafer not only reduced die-shift problem, but also significantly reduced molded wafer warpage. Figs. 14 and 15, respectively, shows the warpage data of reconstructed wafers molded without and with carrier wafer. From the figures, it is clear that with carrier wafer, warpage was reduced by around 30 %. In the case of carrier wafer, warpage is reduced because carrier wafer limits the cure and thermal shrinkages of EMC.

Fig. 11. Die-shift data of reconstructed wafer molded at 150C5mins using low CTE EMC. All data in µm.

Fig. 14. Warpage data of reconstructed wafer molded without carrier. All data in µm. Fig. 12. Optical image showing Si dies on the molding tape mounted on a carrier wafer.

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reconstructed molded wafer was grinded to exposed Cu pillar as shown in Fig. 16b. Some of dies located at the edge of wafer were over grinded due to wafer warpage. The SAM analysis of molded stacked Si dies was carried out to find out any major void or delamination. Fig. 17 is the SAM image of stacked Si dies showing void free embedding of Si dies in EMC. The cross-section of stacked Si dies having Cu pillars is shown in Fig. 18. From these figures, it is clear that using developed embedding process, a 3D integration of multiple dies can be easily realized.

Fig. 15. Warpage data of reconstructed wafer molded with carrier. All data in µm.

Fig. 17. SAM images of stacked Si chips with Cu pillars embedded in EMC.

Fig. 18. Cross-sectional optical image showing stacked Si dies having Cu pillars in a 3D EMWLP.

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(b) Fig. 16. Optical images showing (a) backside of 8” reconstructed molded wafer and (b) front-side of reconstructed molded wafer after grinding. 5. Realization of 3D Embedding Process From embedding process development and optimization, it was found that low molding temperature and low CTE EMC are the best for wafer level embedding process. Thus, 3D embedding of multiple Si dies having Cu pillars was carried out according to process flow shown in Figs. 1 and 2 using low CTE EMC and 150C5mins molding condition. Fig. 16 shows an 8” reconstructed molded wafer having stacked Si dies embedded in EMC. The front-side of

6. Conclusions A new wafer level 3D embedding technology has been developed in this study, which can provide a low cost solution for realizing a 3D system in an EMWLP. Some important results based on this work are as follows 1. 8” wafer level embedding process for semiconductor die in EMC has been developed successfully by using the compression molding method and granular EMC. The developed embedding process resulted in a void free and low warpage (< 1 mm) reconstructed molded wafer. 2. The warpage and die-shift problems of reconstructed molded wafer have been reduced significantly by optimizing the embedding process. 30% reduction in warpage and 88 % reduction in die-shift have been achieved after embedding process optimization. 3. Reconstructed molded wafers have passed reliability tests, such as TCT, MST-L3, and HAST, with no major void or delamination in EMC or at the interface between EMC and Si dies. 4. Developed wafer level embedding process has been used successfully to embed 3D stacks of Si dies in EMC. The SAM and optical inspection results showed void-free 3D embedding of multiple Si dies in EMC. Acknowledgments This work was supported by the Electronic Packaging Research Consortium of Institute of Microelectronics of A*STAR (Agency for Science, Technology and Research),

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Singapore. The authors would like to gratefully acknowledge funding for this work by industry consortium members, which are Asahi Glass Co. Ltd, ASM Technology Singapore Pte Ltd, Hynix Semiconductor Inc., Infineon Technologies Asia Pacific Pte Ltd, Ibiden Singapore Pte Ltd, Kinergy Limited, Nitto Denko (Singapore) Pte Ltd, NXP Semiconductors, Samsung Electro-Mechanics Co Ltd, Sumitomo Bakelite Singapore Pte Ltd, Victrex PLC and the Institute of Materials Research & Engineering. We are also grateful to Sumitomo Bakelite, Ashai Glass Company, Nitto Denko for materials support to our technology development efforts. References 1. J. C. Souriau, O. Lignier, M. Charrier, G Poupon, “Wafer Level Processing Of 3D System In Package For RF And Data Applications”, in proc. IEEE Electron. Comp. Techno. Conf., US, 2005, pp. 356-361. 2. M. Brunnbauer, E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, K. Kobayashi, “An Embedded Device Technology Based on a Molded Reconfigured Wafer” in Proc. IEEE Electron. Comp. Technol. Conf., US, 2006, pp. 547-551. 3. B. Keser, C. Amrine, T. Duong, Owen Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, R. Wenzel “The Redistributed Chip Package: A Breakthrough for Advanced Packaging”, in Proc. IEEE Electron. Comp. Technol. Conf., US, 2007, pp. 286-290. 4. R. Fillion, Charles Woychik, T. Zhang, D. Bitting, “Embedded Chip Build-Up Using Fine Line Interconnect”, in Proc. IEEE Electron. Comp. Technol. Conf., US, 2007, pp. 49-53. 5. V. Kripesh, V. S. Rao, A. Kumar, G. Sharma, K. C. Houe, Z. Xiaowu, K. Y. Mong, N. Khan, and J. Lau, “Design and Develeopment of a Multi-Die Embedded Micro Wafer Level Package”, in Proc. IEEE Electron. Comp. Technol. Conf., US, 2008, pp. 1544-1549. 6. T. Hamano, T. Kawahara, J-I Kasai, “Super CSPTM : WLCSP Solution for Memory and System LSI”, in proc. of International Symposium on Advanced Packaging Materials, 1999, pp. 221-225. 7. A. Okuno, “Wafer Level CSP Process by VPES (Vacuum Printing Encapsulation Systems)”, in proc. of International Symposium on Electron. Materials & Packaging, 2000, pp. 143-151. 8. T. Braun, K.-F. Becker, M. Koch, V. Bader, U. Oestermann, D. Manessis, R. Aschenbrenner, H. Reichl, “Wafer Level Encapsulation – A transfer Molding Approach to System in Package Generation”, in proc. Electron. Package Technol. Conf., 2002, pp. 235-244. 9. A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Bottcher and H. Reichl,“Realization of a Stackable Package Using Chip in Polymer Technology” , in proc. IEEE Polytronic 2002 Conf., 2002, pp. 160-164. 10. C.-T. Ko, S. Chen, C.-W. Chiang, T.-Y. Kuo, Y.-C. Shih and Y.-H. Chen, “Embedded Active Device Packaging Technoloogy for Next-Generation Chip-in-Substrate Packages, CiSP”, in proc. of ECTC 2006, US, pp. 322329.

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