Wafer Level Vacuum Packaging of MEMS Sensors - IEEE Xplore

Wafer Level Vacuum Packaging of MEMS Sensors Thomas F. Marinis, Joseph W. Soucy, James G. Lawrence & Megan M. Owens Draper Laboratory 555 Technology Square Cambridge, MA 02139-3563 Email: [email protected] Tel: 617-258-2953 Abstract A process has been developed for wafer level vacuum packaging MEMS sensors, which are fabricated from etched, single crystal silicon structures, anodically bonded to metallized glass wafers. Key objectives of the process design were to minimize the number of changes to sensor fabrication, insure a high level of vacuum integrity, and flexible enough to accommodate a wide range of sensor designs. Only a single change to the standard sensor fabrication is required to implement the vacuum sealing process. A seal ring of gold, 250 microns wide by 1 micron thick is applied around the perimeter of the sensor and its electrical contact pads. The key features of this vacuum sealing technology are incorporated in the silicon cap wafer. It is 200 microns thick and contains an array of cavities, 50 microns deep, which align with the MEMS devices on the glass wafer. The opposite side of the wafer is coated with 2000 angstroms of silicon dioxide and is arrayed with aluminum bond pads, which align with those on the sensor wafer. These pads are connected to the sensor by through wafer vias, which are coated with a layer of parylene, one micron thick. The parylene is applied in a vapor deposition process, and then an excimer laser is used to ablate it from the bottom of the vias to allow electrical connections to be made to the aluminum bond pads. The vias are metallized with an adhesion layer of 500 angstroms of titanium and a conduction layer of 2000 angstroms of gold. This metal is photo-patterned, to produce pads that align with those of the sensor, and then all exposed parylene is removed by reactive ion etching. This cap wafer is bonded to the sensor wafer in an ultrahigh vacuum system with a base pressure of 10-8 Torr. The two wafers are held on electrostatic chucks, one of which is hinged, so that in the degas phase, both wafers can be cleaned in-situ with an ion gun. For bonding, the hinge is actuated to position the cap wafer above the sensor wafer. A pair of prisms is positioned between the wafers to allow them to be precisely aligned prior to sealing. The wafers are bonded together by heating them to 300 °C and actuating a pair of ball screws, which clamps them together under a load of 500 Newtons. The load and temperature is maintained for one hour to allow the gold of the sensor seal ring to react with the silicon of the cap wafer. The bonded pair is slowly cooled under load to complete the sealing process. The ultimate goal of this sealing approach is to use the control ASIC chip that is paired with the sensor, as the cap structure. This would minimize the length of signal paths between the ASIC and sensor, while realizing a very compact vacuum package. 0-7803-8906-9/05/$20.00 ©2005 IEEE

Introduction MEMS sensors, which are fabricated from single crystal silicon wafers that are anodically bonded to glass substrates, are preferred for high performance inertial instruments because they can be made 20 microns or more thick, while holding out of plane bow to a few nanometers. These instruments achieve their highest level of performance when they are operated at pressures below a few millitorr. [1] They must be placed in close proximity to their control and readout electronics, but their fabrication processes are generally not compatible with CMOS structure. The process described in this paper addresses these issues in a wafer level packaging solution. In contrast to other wafer level packaging schemes, this approach tightly integrates the control ASIC chip with the sensor, by using it as the sensor cap. [2],[3] Assembly Description A schematic cross section of the package assembly is shown in Figure 1. The MEMS inertial sensor is a tuning fork gyroscope that is fabricated on a Pyrex chip, which is shown on top of the assembly. The bottom of the package is formed by the gyroscope’s ASIC control chip. Top views of these two components appear in Figure 2. The ASIC chip is mechanically thinned to 200 microns thick and has a cavity etched in it to accommodate the gyroscope. It also has nine vias that are etched down to its internal metal one level, which are used to make electrical connections to the gyroscope. These vias are insulated with parylene dielectric, which supports sputtered titanium-gold signal conductors. A gold seal ring around the perimeter of the Pyrex chip is used to

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Gold Seal Ring Gold Pad Pyrex Substrate Gyro

Chip Glassivation Metallized Via

ASIC

Sprayed on Glass

Aluminum Bond Pad Gold Bump

Figure 1. A vacuum packaged MEMS gyroscope is shown in schematic cross section. Its cap is fabricated from the ASIC control chip. 2005 Electronic Components and Technology Conference

make a vacuum-tight, gold-silicon diffusion bond between the two chips.

Fabrication of the silicon portion of the sensor begins with a silicon-on-insulator wafer, which is comprised of a 20 micron thick high boron doped layer that is bonded to an undoped carrier. The device structure is photodefined on the doped layer and cut through it using reactive ion etching. The patterned silicon wafer is then anodically bonded to the Pyrex wafer. The undoped silicon and oxide layers are etched off in KOH and HF respectively, to complete the sensor. A completed device is shown in Figure 4.

Figure 2. Top views of a tuning fork gyroscope (left) and its ASIC control chip (right). Sensor Fabrication The process steps for fabricating the MEMS sensor with a seal ring, for vacuum sealing, are as follows. First, positive photoresist (Shipley 1822) is applied to the Pyrex wafer, imaged with a negative mask of all metalized areas, including the seal ring, and developed. The exposed glass areas are etched to a depth of 1500 angstroms, then a film comprised of 500 A of titanium, 500 angstroms of platinum, and 1000 angstroms of gold is sputtered on. A second layer of photoresist (AZ4620) is applied and photo patterned to expose only the metal that is aligned with the seal ring around the perimeter of the chip. The gold seal ring is then electroplated on this exposed metal in a two-step process. First, the wafer is immersed in a strike bath (Orthostrike C, Technic Inc.) at 50°C, pH 4.5 and current density of 5 ASF for 20 seconds to initiate the plated layer. The one micron ring thick seal ring is plated in a high purity bath (434HS, Technic Inc.) at 50°C, pH 6.0 and current density of 10 ASF for ~10minutes. Both layers of photoresist are then stripped from the wafer in an acetone bath with ultrasonic agitation. An SEM image of a metallized Pyrex chip at this point is shown in Figure 3.

Figure 3. Completed Pyrex wafer with sputtered metallization and electroplated gold seal ring.

Figure 4. Completed gyroscope sensor ready for vacuum packaging. Silicon Cap Preparation The first step in processing the ASIC chip wafer is to prepare it for attachment to a silicon handle wafer, by applying gold ball bonds to all of the I/O pads. Next, it is sprayed with a suspension of Pb-B-Zn glass frit in isopropyl alcohol, and then fired in a conveyor oven. The oven profile attains a peak temperature of 400°C for three minutes. Two additional layers of the same glass are applied, and fired at a lower peak temperature of 370°C. These layers of fired glass are then mechanically lapped to a total thickness of 30 microns. At this stage, the ASIC wafer is ready for bonding to a silicon handle wafer. A stainless steel ring fixture is used to press the two wafers together. Bonding is achieved by placing the assembly in a box oven that is ramped up 420°C over one hour. The oven temperature is then lowered to 325°C to allow the glass to anneal for one hour and then slowly cooled to ambient. Once bonded to the handle wafer, the ASIC wafer is mechanically thinned to 200 microns thick. A Logitec lapping machine is used with successively finer diamond emery papers to perform this operation. The thinned wafer is then polished with an alumina-water slurry to achieve a near optical quality finish. Preparation for photolithography is completed by growing an 8000 angstrom thick layer of low temperature oxide on the polished surface of the wafer. Two photolithography steps are needed; one defines the sensor cavity and an isolation trench around the seal ring area. The other defines the vias down to the internal I/O pads on the ASIC chip. The sensor cavity and seal ring trench are made first. Positive resist (AZ4620 ) is spun on and exposed

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2005 Electronic Components and Technology Conference

with a negative mask. The exposed oxide is etched with HF, the photoresist is stripped in acetone and then the exposed silicon is etched in tetramethylammonium hydroxide (TMAH). The sensor cavity is etched to a depth of 50 microns, the LTO mask is stripped away in HF, and a new layer of LTO, 8000 angstroms thick, is applied. This layer is photo patterned and etched in HF to define the vias. Via etch follows the procedures used to form the sensor cavity, but care has to be taken to properly orient the vias, since they extend through the full thickness of the ASIC wafer and etching proceeds anisotropically. The TMAH etch reaction occurs most rapidly along the normal to (111) crystallographic planes of silicon. [4] The plane of the ASIC wafer is (100) and the edges of the square vias are oriented to lie in its (110) planes. This results in a 54.74° angle between the plane of the wafer and each of the four via sidewalls as shown in Figure 5. A 250 micron square via is patterned on the top of the wafer to achieve a 38 micron square opening at the interface to the metal one layer of the ASIC chip.

laser. A close up view of an ablated hole is shown in Figure 8.

Figure 6. Holes drilled through one micron of Parylene using a frequency tripled YAG laser operating at 354 [nm]. (100) (110) 250

A

o

54.74 150

A

38

125 um

Figure 5. Orientation of etched via relative to crystallographic planes of silicon wafer. The via profile is shown in cross section A. Linear dimensions are in microns. Following via etch, the LTO mask layer is stripped from the wafer in HF. A vapor deposition process is then used to apply a coating of Parylene D dielectric, which is between 1 and 1.5 microns thick. Several reasons prompted the selection of this dielectric material. It can be applied as a vapor at ambient temperature, it has a low dielectric constant, and it provides a compliant support of the metal pads that press against those on the sensor. Unfortunately, Parylene conformally coats the ASIC metal at the bottom of the vias, so it has to be removed to make electrical contacts. This is done, by using an excimer laser to ablate a hole through the Parylene without damaging the underlying metal. The use of an excimer laser, which operates at 248 [nm], is critical in this respect because Parylene is transparent at wavelengths above 300 [nm]. [5] When a frequency tripled YAG laser, operating at 354 [nm], was used to drill through the Parylene, the result shown in Figure 6 was obtained. It is believed that most of this longer wavelength radiation passed through the Parylene and heated the underlying metal, which caused absorbed gases and moisture to expand and burst the Parylene. Figure 7 shows vias after drilling holes through the Parylene with an excimer

Figure 7. Vias after ablation of Parylene from the bottom metal.

15 µ Figure 8. Hole drilled through the same material as in Figure 6 using an excimer laser operating at 248 [nm]. After the Parylene is ablated from the bottom of the vias, they are dry etched to remove any metal oxide. Then 8000 angstroms of aluminum is sputtered over the wafer and photo

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patterned to define capture pads for the vias. The final step in cap fabrication is to etch off the exposed Parylene, which is done using a 50/50 gas mix of argon and oxygen, in a reactive ion etcher. A photograph of a completed cap appears in Figure 9.

mechanism is then swung into position between the two wafers. A long working distance camera system, which is mounted outside one of the view ports of the metal bell jar, is used to view both wafers simultaneously. Wafer alignment is accomplished by actuating motors connected to the x-y stage of the bottom wafer chuck to bring alignment features on both wafers into coincidence. The split prism is retracted from between the wafers immediately after alignment.

Figure 9. Completed silicon cap with metallized vias and a cavity for the gyroscope. Seal Process Sealing of the cap and sensor wafers is carried out in an ultra-high vacuum system, which achieves a base pressure of 10-8 Torr, by using a combination of a dry mechanical pump, a turbo pump and an ion pump. A picture of this vacuum system appears in Figure 10. It incorporates several special features, which include a custom designed bonding mechanism, an ion gun for in situ cleaning of both wafers, and view ports, optics and manipulators that allow the wafers to be optically aligned prior to bonding. The bonding mechanism is comprised of two electrostatic chucks, which are mounted on stainless steel plates with embedded heaters. They are powered through independent temperature controllers. The bottom chuck is mounted on an x-y stage, by means of four springs, which provide compliance when the wafers are pressed together. The top chuck is hinged on one end and is attached to a motor, which flips it from a wafer up to a wafer down position. The wafer is loaded and ion cleaned with the chuck in the up position. Prior to bonding, the chuck is flipped to the wafer down position and locked in place by a spring latch. These two chucks are shown in Figure 11; the top chuck is moving between its face up and down positions. The electrostatic chucks were fabricated by printing an inter-digitated comb pattern of gold thick film ink on low temperature co-fired ceramic (LTCC). Another layer of ceramic tape, with punched holes for access to the conductor combs, was laminated on top and fired. The bottom sheet of the fired ceramic was then lapped to a thickness of 150 microns. The wafers are vacuum degassed at 200°C for eight hours, and ion cleaned for 30 minutes in preparation for bonding. The motor is energized to flip the top wafer chuck and latch it into bonding position, as shown in Figure 12. A split prism

Figure 10. bonding.

Vacuum sealing system for wafer level

Figure 11. Close up view of bonder, which shows the electrostatic chucks that are used to hold the wafers. Bonding of the wafers is initiated by energizing a gear motor that drives two ball screws, which are connected to the

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top wafer chuck. They pull it down onto the bottom wafer chuck, while four precision slides maintain alignment of the wafers. A strain gage load cell, mounted below the lower wafer chuck is used to monitor and control the bond force.

the same process as used to thin the ASIC chip wafer. Solder bumps or wire bonds can then be used to make electrical connections to the ASIC I/O pads.

50 um Figure 14. Magnified view of seal ring area of the bonded chip pair shown in Figure 13. The dark dendrites are the silicon rich phase in the gold-silicon alloy of the interface.

Figure 12. Bonder mechanism with top wafer chuck flipped down and latched for bonding. Arrow points to the prism mechanism that swings between wafers for optical alignment. The wafers are bonded together at a temperature of 375°C, while a pressure of 5 MPa is applied on the seal ring interface. Both the temperature and pressure are gradually ramped to these values and then held constant for one hour to affect bonding. Then, the pressure is released slowly, the bell jar is isolated from the vacuum pumps, and the temperature is lowered to ambient by bleeding nitrogen into the bell jar. Micrographs of the bond interface, as viewed through the glass chip of the sensor are shown in Figures 13 and 14. A cross section of the bond interface appears in Figure 15.

870 nm Figure 15. Cross section of the interface shown in Figure 14. Discussion A full characterization of this package with operating sensors has not yet been completed. The via technology was characterized by using a test structure of three vias that were drilled down and connected to a common buss. The tops of the vias were connected to isolated probe pads. A top view of several of these test structures is shown in Figure 16. The capacitance of a single via is estimated to be

CVia

Figure 13. Bonded sensor and silicon cap pair, as viewed through the glass chip of the sensor. The last major process step is removal of the handle wafer from the bonded pair, to provide access to the gold ball bonds on the I/O pads. This is done by mechanical lapping, using

= εP ε0

4 AWall + ABott + APad , dP

[1]

where εP and dP are the relative permittivity and nominal thickness, respectively, of Parylene D, and ε0 is the permittivity of vacuum. Their values are: εP = 2.84, dP = 1 [µm], and ε0 = 8.84 × 10-12 [F/m]. The areas of the via wall, AWall, via bottom, ABott, and probe pad, APad, are calculated from the dimensions given in Figure 17. Their values are: AWall = 2.65 × 10-8 [m2], ABott = 1.13 × 10-9 [m2], and APad = 9.99 × 10-8 [m2]. Thus, the total area of a test via is AT = 4 AWall + ABott + APad = 2.07 × 10-7 [m2], and from equation [1], its corresponding capacitance is 5.2 [pF]. Capacitance measurements were made, by probing between adjacent test structures, which was equivalent measuring the total

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capacitance of two test structures connected in series. The expected capacitance of this configuration is

CM

1 (3 CVia + C Buss ) . 2

=

[2]

The term CBuss is the capacitance of the metal buss that connects the three vias in each test structure. It is 750 [µm] long by 250 [µm] wide and is deposited on 6000 angstroms of thermal oxide, which has a dielectric constant of ε = 3.8. Its estimated capacitance value is 10.5 [pF]. Substitution for CVia and CBuss in equation [2] yields a capacitance value of 13.1 [pF], which compares favorably with the measured value of 11.0 ± 1.6 [pF]. Thus, we conclude that the actual capacitance of a via is close to the calculated value of 5.2 [pF].

RWall

=

ρ

  2mL ln + 1 , 2mt  w 

[3]

where ρ and t are the resistivity and thickness, respectively, of the aluminum film, with values of ρ = 2.65 × 10-8 [Ω m] and t = 8.0 × 10-7 [m]. The geometry of the sidewall is defined by, a length, L, a bottom width, w, and a taper, m. The values of these quantities, as specified in Figure 17, are: L = 1.84 × 10-4 [m], w = 3.8 × 10-5 [m], and m = 106/184 = 0.576. The sidewall resistance obtained by substituting these values into equation [3] is RWall = 0.048 [Ω]. The total resistance of the via is RVia = (RWall + RBott)/4, where RBott is the contribution from the bottom of the metal. For a value of RBott = 0.009 [Ω],RVia = 0.014 [Ω]. Four point resistance measurements were made on the test structure vias by applying a pair of current and voltage probes on the center pad and a current and voltage probe on each of the adjacent pads. Resistance values on the order of 1000 ohms were measured on the first test wafer. This value was reduced to 100 ohms by extending the time of cleaning after laser drilling. We are investigating the source of the high resistance. Nevertheless, the high resistance appears to be stable and it is not detrimental to the intended sensor application. The vacuum level within a sealed package was estimated by measuring the deflection of the silicon cap, after it was mechanically thinned. This measurement was made with the interferometer arrangement that is depicted in Figure 18. An optical flat was placed on the silicon surface and illuminated with a helium-neon laser. Reflections from the two surfaces formed a fringe pattern, in which one black and white fringe pair corresponded to a displacement of 0.316 microns. The fringe pattern obtained from a tablet of four sealed chips appears in Figure 19.

Figure 16. Arrays of test structures comprised of three vias connected to a common buss, which were used to characterize the resistance and capacitance of the via structure. 250 106 38 38

250

Figure 18. Schematic representation of interferometer used to measure deflection of silicon cap after mechanical thinning.

290

20 106 560

The deflection of a uniformly loaded plate of length a and width b, with all four sides built in is given by [6]

184 Via Side Wall

Top Probe Pad

Figure 17. Features used in calculation of via capacitance and resistance. All dimensions are in microns. The resistance of the via side wall, RWall, is estimated from

RWall

=

ρ t

L

−1 ∫ (2mx + w) dx

w =

4q a 4 π 5D

∞

∑

m =1, 3, 5

m −1

(− 1) 2 m

5

 mπx  cos ×  a 

[4]

 α tanh α m + 2 mπ y mπ y mπ y  . 1 1 − m  + cosh sinh a a a  2 cosh 2 cosh α α m m 

The plate stiffness, D, is defined in terms of the elastic modulus, E, thickness, h, and Poison’s ratio, ν,

0

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E h3 , and the term αm represents 12 1 − ν 2 m π b . From the fringe patterns in Figure 19, the αm = 2a displacement, w, of the plate center is estimated to be 1.9 microns. Substitution of the values E = 179 [GPa], ν = 0.3, a = b = 4 [mm], and h = 150 [µm] into equation [4] yields a value of 2.06 [Torr] for the internal pressure q. However, a value of w = 1.90515, yields an internal pressure of 4 [mTorr], so we are reasonably confident that the internal pressure is within the goal of less than 10 milli-Torr. D =

(

)

Figure 19. Fringe pattern obtained from a tablet of four sealed devices, after the silicon cap was mechanically thinned. Each fringe corresponds to a normal displacement of 0.316 microns.

The vacuum in the sensor cavity can be degraded by several different sources of gas molecules. During sealing, the wafers are raised to an elevated temperature, after the cavities are closed off. The product of time and temperature in this sealing process is comparable to that of degassing prior to sealing. Consequently, molecules of water or volatile carbon compounds adsorbed in surface pits, scratches, etc. can be released and not readily re-adsorbed. The magnitude of this potential source can be estimated by considering a cavity, 4.2 [mm] square, by 50 [µm] deep. Its volume and surface area are VCavity = 8.82 × 10-10 [m3] and ACavity = 3.61 × 10-5 [m2]. The sensor is estimated to have a surface area of approximately ASensor = 1.00 × 10-5 [m2], so the total surface area within the cavity is 4.61 × 10-5 [m2]. If 0.1% of this area is covered by a monolayer of water, then 8.46 × 10-13 moles of water are trapped within the cavity. By the perfect gas law, PV = nRT, these molecules could generate a pressure of 18 milli-Torr, if completely volatilized. Another source, from which gas can be introduced into the cavity during sealing, is the electroplated gold seal ring. A

seal ring, 0.25 mm wide by 1 micron thick, which surrounds a cavity 4.2 [mm] square, contains 8.597 × 10-5 [gm] or 4.365 × 10-7 moles of gold. If this metal contains 1 ppm of dissolved hydrogen, it could release 4.365 × 10-13 moles of gas into the cavity. If the cavity is 50 [µm] deep, it has a volume of 8.82 × 10-10 [m3], so the gas could raise its pressure by 9.26 milliTorr. The gas sources discussed previously degrade the vacuum level achieved during sealing. Gas that enters the cavity via seal leaks or diffusion out of its walls limits sensor life to the time required to leak up to maximum operating pressure. In the case of guidance grade, inertial instruments, this pressure is approximately 20 milli-Torr. The sensor operational lifetime, tLife, can be estimated for a given leakage rate, LR, at standard pressure and temperature as follows PMax VCavity , [5] t Life = PStd LR where PStd is standard atmospheric pressure of 760 Torr. For a leakage rate of LR = 1.0 × 10-14 [std cc / sec] and a cavity volume of VCavity = 8.82 × 10-4 [cc], equation [5] yields tLife = 2.32 × 106 [sec], or a little more than 26 days. Even though the postulated leakage rate is below the sensitivity of any commercial instrument, the sensor operational lifetime is unacceptably low. This situation can be dramatically improved, by incorporating a getter element in the cavity. With an included getter element, equation [5] becomes PMax VCavity + AGetter CGetter , [6] t Life = PStd LR where AGetter is the area of the getter element. If it covers half the area on the silicon side of the cavity, AGetter = 8.82 × 10-2 [cm2]. The getter capacity, CGetter, is assumed to be equal to that of SAES, patterned thin film product, which is 0.5 [cc Torr / cm2] when activated for 45 minutes at 350°C. [7] For a leakage rate of LR = 1.0 × 10-14 [std cc / sec], tLife = 5.384 × 109 [sec], or 170 years! By electing to use vias to make electrical connections to the sensor within the vacuum cavity, we avoid the loss of real estate on the ASIC wafer required for perimeter feed throughs. Our experience with conventional vacuum packages also leads us to believe that the via structure has better vacuum seal integrity than peripheral feed throughs. The reason is that the vias terminate at metal 1 within the ASIC, so there is no direct path to the outside atmosphere as in the case of perimeter feed throughs. Vias also allow for the shortest signal path from the sensor to the ASIC chip. The principal disadvantage of our process is that it is implemented with the use of a handle wafer, which has to be removed after sealing. The decision to use a handle wafer was driven by the high incidence of breakage that we experienced in trying to process wafers in a laboratory environment with manual handling. It may be possible to eliminate the handle wafer in a more automated production environment. Alternatively, we believe that the handle wafer could be replaced by a LTCC substrate, with I/O pads that are aligned to those on the ASIC wafer. A thin coating of AuSn braze alloy on the pads of the ceramic substrate could be used

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to make electrical connections to the gold bumps on the ASIC wafer when it is bonded to the substrate with glass frit. Conclusions We have developed and demonstrated a wafer level vacuum sealing process for MEMS sensors. Highly miniaturized instruments can be realized in this process because a wafer of ASIC chips is used to cap the wafer of MEMS sensors. Electrical connections between each sensor and its ASIC circuitry are made by vias through the backside of the ASIC wafer. The via interconnect scheme allows ASIC wafer real estate to be utilized more efficiently than with peripheral feed throughs. The capping process is fully compatible with the use of thin film getter elements. The use of getter in the vacuum cavity is considered essential to realizing acceptable sensor operating life times. Acknowledgments This work was sponsored by DARPA under contract DAAH01-99-C-R299, “High-G IMU on Chip”. Case #2501 approved by DARPA on 6/18/2004 by Charade Estes, Mgr. DARPA TIO. Approved for Public Release: Distribution is unlimited. The authors would like to acknowledge the contributions of Mark Mescher and Mark Singleton in developing the processes to fabricate the silicon sensor cap and Tom Worth with the glass frit and handle wafer processes. References 1. Marinis, T. F. and Soucy, J. W., “Vacuum Packaging of MEMS Inertial Sensors,” Proc. International Microelectronics and Packaging Society Conf, Boston, MA, Nov. 2003, pp. 386-391. 2. Gooch, Roland and Schimert, Thomas, “Low-Cost Wafer-Level Vacuum Packaging for MEMS,” Materials Research Society Bulletin, January, 2003, pp. 55-59 3. Sparks, Douglas, et. al., “Chip-Scale Packaging of a Gyroscope Using Wafer Bonding,”, Sensors and Materials, Vol. 11, No. 4, 1999, pp. 197-207 4. Peterse, Kurt E., “Silicon as a Mechanical Material,” Proceedings of the IEEE, Vol. 70, No. 5, pp. 58-95. 5. Specialty Coating Systems Inc., Inianapolis, Indiana, Parylene Pellicles for Space Applications 6. Timoshenko, S. and Woinowsky-Krieger, S., Theory of Plates and Shells, McGraw-Hill (New York, 1959), p. 197. 7. SNEG sorption curve, Patterned Getter Wafer, SAES Getters S. p. A., Viale, Italia, www.saesgetters.com

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