WCDMA Direct-Conversion Receiver Front-End ... - Semantic Scholar

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 4, APRIL 2005

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WCDMA Direct-Conversion Receiver Front-End Comparison in RF-CMOS and SiGe BiCMOS Brian A. Floyd, Member, IEEE, Scott K. Reynolds, Thomas Zwick, Member, IEEE, Lunal Khuon, Troy Beukema, and Ullrich R. Pfeiffer

Abstract—Wide-band code-division multiple-access direct-conversion receiver front-ends have been implemented in both 0.25- m RF-CMOS and SiGe BiCMOS technologies. These circuits have been designed for the same application, radio architecture, and system specifications, allowing relevant comparisons to be made. The front-ends include a bypassable low-noise amplifier, a quadrature downconverter, baseband variable-gain amplifiers, and a local-oscillator frequency divider with output buffers. At 24.5 mA of total current consumption from a 2.7–3.3-V supply, the CMOS front-end has a noise figure of 5.3 dB, in-band third-order intercept point (IIP3) and second-order intercept point (IIP2) of 14 and 20.7 dBm, respectively, and out-of-band IIP3 and IIP2 of 1.2 and 69 dBm, respectively. Compared to an SiGe front-end consuming 22 mA, the CMOS circuit has a 2-dB higher noise figure, comparable out-of-band linearity, 3-dB higher in-band IIP3, 12-dB lower in-band IIP2, and 7-dB higher LO-to-RF leakage.

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Index Terms—BiCMOS, direct-conversion receiver, low-noise amplifier (LNA), local oscillator (LO) buffer, mixer, RF CMOS, SiGe, technology assessment, wide-band code-division multiple access (WCDMA).

I. INTRODUCTION

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OR WIRELESS integrated circuits, a key step in arriving at a suitable, cost-effective, and timely solution is choosing the optimal technology for the RF portion of the radio. There are many factors which weigh into this decision, including cost, the amount of digital content to be integrated, the application’s performance requirements, the capabilities of the technologies, and design-kit/library maturity. Currently, CMOS and SiGe BiCMOS are both widely used technologies for many wireless applications; however, questions remain over which technology and generation is most appropriate and the performance tradeoffs seen in migrating amongst technologies. While literature surveys [1] help to illustrate trends, uncertainty remains due to differences between architectures, system specifications, and even circuit designers themselves. This paper provides a performance comparison between direct-conversion CMOS and SiGe BiCMOS receiver front-ends which have been designed for the same application using the same radio architecture to meet the same system specifications.

Manuscript received April 19, 2004; revised August 4, 2004. B. A. Floyd, S. K. Reynolds, T. Zwick, T. Beukema, and U. R. Pfeiffer are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). L. Khuon is with the Department of Electrical and Computer Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. Digital Object Identifier 10.1109/TMTT.2005.845742

A 0.25- m RF-CMOS front-end is presented and then compared to the front-end of a 0.25- m SiGe BiC-MOS receiver [2]. Each front-end includes a low-noise amplifier (LNA), an off-chip surface acoustic wave (SAW) filter, a mixer preamplifier, downconversion mixers, and baseband variable-gain amplifiers. A frequency divider with local-oscillator (LO) buffers is also included to provide quadrature LOs. Our circuits are designed for the frequency-division duplex (FDD) wideband code-division multiple-access (WCDMA) standard [3]. The FDD system transmits in the 1920–1980-MHz range and receives in the 2110–2170-MHz range. WCDMA receivers require both very high sensitivity and very high linearity, with stringent out-of-band linearity requirements due to the presence of strong transmitter leakage signal at the receiver input [4]. Finally, these receivers need low power consumption and high integration levels to be cost-effective and competitive. The paper is organized as follows. Section II discusses the specific 0.25- m CMOS and BiCMOS technologies and then provides an overview of the differences between these technologies which impact the design and performance of the RF circuits. Section III presents the receiver front-end topology and then provides circuit-level comparisons between the LNA, downconverter, frequency divider, and LO buffers. Section IV presents the measured results for the WCDMA front-ends, while Section V presents our conclusions. II. CMOS TECHNOLOGY VERSUS BIPOLAR TECHNOLOGY A. Technology Overview The 0.25- m SiGe BiCMOS technology used features both and high-breakdown bipolar devices with 47- and high27-GHz , and 3- and 5.2-V , respectively. The minimum emitter length is 0.32 m. Note that the bipolar transistors in this 0.25- m BiCMOS technology are essentially the same as the bipolars in an earlier and less expensive 0.35- m SiGe BiCMOS technology (i.e., they have the same emitter lengths ); thus, the performance comparison in this paper and is applicable to both BiCMOS technology generations. Both thin- and thick-oxide field-effect transistor (FETs) with 0.24and 0.4- m minimum channel lengths, respectively, are also included. Passive components include metal–insulator–metal (MIM) capacitors, polysilicon and diffused resistors, and on-chip spiral inductors implemented in a 4- m-thick top-level metal. The substrate resistivity is 11–16 cm. The 0.25- m RF-CMOS technology is virtually identical to the BiCMOS technology except that there are no bipolar deis 35 GHz. The RF-CMOS vices. The 0.25- m device

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Fig. 1. Block diagram of the SiGe (minus the analog baseband) and CMOS WCDMA direct-conversion receiver front-ends.

technology features the same back-end-of-the-line and passive devices as the BiCMOS technology; thus, performance differences between these technologies can be attributed to the different active components rather than the passives. Finally, the cm. substrate resistivity is 11–16

B. Review of CMOS Versus Bipolar There are multiple differences between CMOS and bipolar devices which impact RF circuits (see [5] for a more in-depth discussion). The first difference of note is the transconducof the devices. Whereas bipolar tance-to-current ratio , equal to one over the devices have roughly a constant , which can be thermal voltage, MOS devices have a lower shown to be inversely proportional to the gate-overdrive voltage in saturation. This is valid at both long-channel taking a value of in and short-channel limits, with in extreme short-channel. As a result, long-channel and the FET’s declines as current increases. To increase the output signal current, one can then either increase the FET’s input voltage swing (shifting the burden to previous stages), the device size (moving to weaker inversion, i.e., lower gate-overdrive), or the bias current. In our CMOS designs, the reduced noticeably affected the divider, LO buffers, and mixer switches. noise Second, MOS devices exhibit significantly higher than their bipolar counterparts. Often technologies are comcorner frequencies; however, size and bias pared using dependencies cloud such comparisons. Therefore, the noise performance of the mixer commutating switch was simulated in both technologies, providing a functional comparison. At 100 Hz, 3 mA, and 2.5 V, a 100 0.24 m -channel MOSFET output spot noise than a 6 0.32 m shows 35 dB more bipolar. Third, MOS devices are more sensitive to substrate resistance than bipolar devices, due to bulk transconductance and parasitic capacitance at the source and drain. Bipolar devices only interact with the substrate through their collector. To illustrate this, simulations were run on LNAs when sweeping the substrate resistance in the transistor model. In this simulation, the SiGe LNA’s noise figure (NF) is virtually independent of substrate resistance, whereas the CMOS LNA’s NF varies up to 0.5 dB. To get good model-to-hardware correlation in CMOS, the substrate

has to be accurately modeled. Toward this end, the RF-CMOS technology includes “RF-FET” layout cells in which the substrate and gate hook-ups are fixed and included in the model. The comparisons discussed so far have all favored bipolar devices; however, FETs are superior in terms of raw third-order linearity performance [5]. The reason is that the output-current to input-voltage dependence is exponential for bipolar devices and less than quadratic for FETs. Therefore, more third-order distortion is generated in a bipolar device than in an FET; thus, we would expect the input-referred third-order intercept point (IIP3) to be better for CMOS. Note that harmonic cancellation techniques have been used successfully to greatly enhance IIP3 for bipolar circuits [6] and, more recently, for CMOS circuits [7]; thus, this comparison applies to “raw” performance.

III. CIRCUIT-LEVEL COMPARISONS A. Receiver Description A block diagram of the WCDMA front-end used for both CMOS and SiGe is shown in Fig. 1. The WCDMA signal from the antenna passes through a duplexer (not shown) and into the 50- input of the switched-gain LNA. The LNA provides either 14 dB of gain or 4 dB of loss, depending on the mode of operation. The LNA drives an off-chip SAW filter which attenuates signals outside the WCDMA receive band. This filter is necessary to meet stringent out-of-band receiver linearity requirements implied by the 3GPP specification [2]–[4] (e.g., 1.3-dBm out-of-band IIP3 and 72-dBm out-of-band second-order intercept point (IIP2), derived assuming LNA-referred signals of 21 dBm for TX leakage and blocking signals in the 1679–1840- and 2015–2075-MHz range between 59 and 40 dBm). The signal then comes back on chip to the downconverter, composed of a mixer preamplifier with 12 dB double-balanced mixers with 6 dB of of gain and a pair of gain. Quadrature LO signals are generated using a frequency divider and LO buffers. The outputs of the mixers drive baseband variable-gain amplifiers (BBVGAs), which provide five selectable gain settings from 16 to 8 dB in 6-dB steps. In addition to the front-end, the SiGe receiver also includes the analog baseband [2], consisting of automatically tuned channel-select filters, final VGAs, and a serial interface. Note that the SiGe front-end is a redesigned version of that presented in [4] and [8].

FLOYD et al.: WCDMA DIRECT-CONVERSION RECEIVER FRONT-END COMPARISON IN RF-CMOS AND SiGe BiCMOS

Fig. 2.

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Simplified schematics of switched-gain LNAs with inductive degeneration and external input match for (a) SiGe and (b) CMOS.

B. Low-Noise Amplifier Fig. 2(a) and (b) shows simplified schematics of the switchedgain LNAs. These LNAs have three gain modes and one bypass mode, all of which are matched to 50 at the input and output. These settings enable the LNA to be controlled by the baseband processor based on the received signal strength; the LNA should be placed in its most power-efficient state while still meeting sensitivity and linearity requirements. A standard topology is used for the LNAs, with either a common-emitter (SiGe) or common-source cascode (CMOS) configuration, both with inductive degeneration. Bypass functionality is provided by MOS and for SiGe and for CMOS. The transistors output matching network is integrated, while the input matching network is off-chip, consisting of a series inductor for SiGe and a series inductor and shunt capacitor for CMOS. The simulated and measured performance of the LNAs is summarized in Table I for comparable power consumptions. Each LNA was packaged with the rest of the receiver in a QFN-32 plastic package. Both LNAs meet our performance targets, where the CMOS LNA has slightly lower gain and higher NF with comparable IIP3. The CMOS 1-dB compression point is higher. Also, the model-to-hardware correlation was excellent for both LNAs. Finally, multiple gain modes are available for each LNA to facilitate power consumption, gain, and linearity tradeoffs. The SiGe LNA has 15.6-dB/9.3-mA, 15.1-dB/5.3-mA, 13.5-dB/2.6-mA, and 5-dB/0-mA modes; the CMOS LNA has 14-dB/6-mA, 13.4-dB/4-mA, 13-dB/2-mA, and 6-dB/0-mA modes. In every mode of operation, each LNA has input and output return losses better than 10 dB. Note that the highest current mode is used in the full receiver comparisons. More details on the LNAs can be found in [9], which includes a detailed explanation of the LNA design methodology, as well as the simulated and measured results for the SiGe and CMOS LNAs. In addition, [9] contains measured and simulated results for an 0.18- m SiGe LNA and simulation results for an 0.18- m CMOS LNA.

TABLE I SUMMARY OF MEASURED AND SIMULATED LNA PERFORMANCE

Fig. 3. Schematic of CMOS preamplifier (i.e., LNA2). The same topology is used for SiGe, where NPNs are in place of the FETs.

C. Downconverter The downconverter is composed of a preamplifier, a pair of mixers, and BBVGAs. A schematic of the preamplifier is shown in Fig. 3. The same circuit topology is used for both SiGe and CMOS. A differential amplifier with one side at smallsignal ground is used to perform a single-ended-to-differential

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Fig. 4. Mixer schematics for: (a) SiGe BiCMOS employing a multitanh transconductor and (b) RF-CMOS employing a class-AB transconductor.

conversion. Shunt and series feedback are used to enhance the linearity and input match, and tuned loads are used at the outputs. In simulation, the SiGe preamplifiers have 12.5-dB gain and 4.9-dB NF, at 3.1 mA. The CMOS preamplifier has 15.7-dB gain and 4.2-dB noise figure, at 3.2 mA. The higher gain and lower NF in the CMOS circuit are intended to offset the higher NF of the CMOS mixers. Following the preamplifier are a pair of double-balanced Gilbert-cell mixers. Schematics for the SiGe and CMOS mixers are shown in Fig. 4(a) and (b). The SiGe mixers use a multitanh transconductor [10] to improve the linearity through piecewise approximation [11]. The CMOS mixers instead use a class-AB transconductor which is simply a differential pair with the tail-current source removed [12]. Removing the tail current improves the linearity by eliminating the saturation mechanism caused by that tail current. Current consumption for each mixer is 2.7 mA for SiGe and 2.9 mA for CMOS. Table II summarizes the simulated and measured performance of the SiGe and CMOS downconverters. These results were obtained through wafer-probing and are referred to the 50- preamplifier input. The SiGe downconverter meets all performance targets, while CMOS hits all targets except for NF. Model-to-hardware correlation is excellent for the SiGe downconverter and good for the CMOS downconverter, except for the miss on NF. Comparing CMOS to SiGe, we see that CMOS has comparable gain, higher NF, improved IIP3, and slightly worse IIP2. The CMOS current consumption is higher due to increased current in the LO buffers. The higher average NF (i.e., integrated over a 1.92-MHz bandwidth) in CMOS is caused by flicker noise, due to higher device noise and likely a lower-than-expected LO drive. To offset this increased NF, the preamplifier gain could be increased by 3 dB to lower the total receiver NF to about 4 dB. Of course, in-band linearity would be reduced by 3 dB as well. The LO-to-RF leakage term, which has to be minimized in direct-conversion receivers, is also larger in

TABLE II SUMMARY OF MEASURED AND SIMULATED DOWNCONVERTER PERFORMANCE

the CMOS downconverter. This is due to the physically larger CMOS switching pair in the mixer, which then feeds the LO signal back through the circuit via parasitic capacitance. Finally, the CMOS downconverter’s quadrature accuracy, which originates in the divider, is not as tight. These results suggest that a BiCMOS mixer with CMOS devices in the transconductor and bipolar devices in the switching core [12], [13] would have the best performance of all. Such a mixer would have high IIP3 from the MOS transconductor and low NF from the bipolar switches. D. Frequency Divider A frequency divider is used to generate quadrature LO signals. By coming on chip at twice the desired LO frequency, the LO leakage through the package can be minimized. Both the SiGe and CMOS dividers use current-mode logic (CML), with two D-flip-flops connected in a toggle configuration. One difference between the two is that the bipolar divider includes emitter followers between its evaluate and hold sections in the


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TABLE III MEASURED RESULTS OF THE RECEIVERS AT 25 C ALONG WITH DERIVED PERFORMANCE TARGETS

Fig. 5. Schematic of a CMOS LO buffer using a modified Cherry–Hooper amplifier. The SiGe LO buffer employs simple differential pair (not shown).

Fig. 6. Die photographs of the: (a) CMOS and (b) SiGe receivers. Die sizes are 2.1 2.4 mm and 2.3 2.4 mm , respectively.

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D-flip-flops. The CMOS divider does not use any source-follower buffers, since source followers degraded performance and power consumption. At 2.7–3.3 V, the SiGe divider consumes 1.4 mA while the CMOS divider consumes 1.1 mA. The CMOS divider was targeted for the lowest possible power consumption and a 10-dBm input sensitivity. Since the FET’s is lower, it was necessary to rely on injection locking to meet sensitivity over corners without requiring additional dc current. A risk, though, in using injection locking is that the input sensitivity will degrade quickly if the divider’s self-oscillation frequency comes out lower than expected. The measured results for the CMOS downconverter indicate this model-tohardware miss, since the mixer NF is sensitive to the LO signal. As high as a 3-dBm input signal is required to minimize NF. To remedy this, an additional 1–2 mA should be spent in the divider, increasing the sensitivity, and placing the input-referred self-oscillation frequency well above 4.2 GHz. E. LO Buffers The design of the LO buffer is straightforward for bipolar, but is a challenge for CMOS. The bipolar mixers require a singleended 300-mV signal and present a 160-fF load. This is easily

Fig. 7. Measured frequency response of SiGe and CMOS receiver front-ends normalized to in-band gain.

provided by a bipolar differential pair with resistive loads. Also, due to their diffusion capacitance, bipolar transistors turn off faster. The CMOS mixers, on the other hand, require a much ) and present larger swing of 500 mV (due again to lower a load of 300 fF. Thus, compared to the bipolar LO buffer, the CMOS LO buffer has to provide almost twice the signal swing to twice the capacitive load. At first glance, it would seem that either the power consumption would have to be quadrupled (for a slew-rate limited design) or a different circuit topology would be required. While inductive loads could be used to increase the

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Fig. 8.


Measured: (a) noise figure, (b) in-band IIP3, and (c) in-band IIP2 of SiGe and CMOS receiver front-ends.

output swing, this was ruled out due to their increased size and potential crosstalk. The chosen CMOS LO buffer is a modified Cherry–Hooper amplifier [14], [15], as shown in Fig. 5. It consists of a transadfollowed by a transimpedance stage mittance stage . Both the interstage and output nodes are low impedance due to the feedback resistor, resulting in a high gain–bandwidth product. The traditional Cherry–Hooper stage has been modified by substituting PMOS transistors for the normal resistive loads to the supply. This improves the slew rate of the amplifier. The CMOS LO buffers each consume 1.5 mA.

TABLE IV LITERATURE SURVEY OF BIPOLAR AND CMOS WCDMA RECEIVERS

IV. RECEIVER FRONT-END COMPARISONS Die photographs of the ICs are shown in Fig. 6. The CMOS chip has fill cells occupying the space where the analog baseband would sit. The ICs were packaged in QFN-32 plastic packages and mounted on evaluation boards. These boards have the required external components for the IC, as follows: the LNA dc-blocking capacitor and input-matching network; the SAW filter; supply bypassing capacitors; and a current-setting resistor. Additionally, output buffers are included to drive 50- measurement equipment. A WCDMA test-bed, which includes A/D converters and a software digital baseband, has been developed to verify compliance with 3GPP specifications. Details on this test-bed can be found in [2] and [4]. The test-bed is used to take both analog (e.g., IIP3) and digital (e.g., bit error rate) measurements. Exhaustive measurements have been made to correlate each digital measurement to its analog counterparts, verifying each of our derived circuit specifications. As a result of these correlations, the front-ends can be confidently compared using only analog measurements. The measured performance of each receiver front-end is summarized in Table III, together with our target specifications. These receiver performance targets are discussed in [4]. The worst-case result (over frequency) for each measurement at of 3 V is placed in Table III. To facilitate com25 C and a parisons, the best result among the three receivers is highlighted in bold, while those results which fall short of our targets are underlined. Plots are included of the measured frequency

response (Fig. 7), noise figure [see Fig. 8(a)], in-band IIP3 [see Fig. 8(b)], and in-band IIP2 [see Fig. 8(c)]. In short, our results show that, compared to the SiGe bipolar receiver, the CMOS receiver is superior in terms of in-band IIP3 and 1-dB compression point, comparable in terms of out-of-band IIP2 and IIP3, and inferior in terms of noise figure, in-band IIP2, and LO-RF leakage. This, however, was the first iteration of the


CMOS circuit. Based on these results, improved performance from the CMOS front-end could be achieved by increasing the gain in the LNA and mixer preamp a total of 3 dB, lowering the NF to 4 dB, and reducing in-band IIP3 to 17 dBm. This design point would meet our WCDMA targets with margin. To place these results into context, Table IV compares our WCDMA receiver front-ends to others found in literature [8], [13], [16]–[24]. The results show bipolar receivers with an NF from 2.5 to 4.3 dB, in-band IIP3 from 21 to 11 dBm, and in-band IIP2 from 17 to 49 dBm. CMOS receivers show NF from 3.4 to 6.5 dB, in-band IIP3 from 16 to 1.5 dBm, and in-band IIP2 from 21 to 47 dBm. Clearly, both CMOS and SiGe can be used to successfully implemented WCDMA receivers. It is worth noting that many of the receivers listed in Table IV do not specify out-of-band IIP3 or IIP2. The receivers which demonstrably meet the out-of-band linearity targets are our SiGe chip [2] and Lie et al. [19], both of which use off-chip SAW filters to attenuate the TX leakage and out-of-band blockers.

V. CONCLUSION Choosing the optimal technology for a given application is an important yet complicated decision. Toward this end, this work provides valuable data, benchmarking 0.25- m SiGe BiCMOS and CMOS technologies for a direct-conversion WCDMA receiver application. Ultimately, both technologies can be used to build receivers which meet WCDMA specifications. Our results show that the SiGe front-end achieves 2-dB lower NF at comparable power consumption. Out-of-band linearity for both is equivalent, while SiGe shows 12-dB higher in-band IIP2 but 3-dB lower in-band IIP3. Note that, based on our 0.25- m CMOS results, improved performance could be achieved by increasing the gain in front of the mixer by 3 dB, lowering the CMOS NF to 4 dB, and reducing in-band IIP3 to 17 dBm. Thus, one could expect about a 1-dB difference in sensitivity at the 0.25- m node between SiGe and CMOS for comparable linearity and power consumption. Of course, further refinements in performance are possible for both SiGe and CMOS implementations (e.g., [13], [20], and [23]), which is why a literature survey was performed. This WCDMA survey similarly shows higher NF and higher IIP3 for CMOS but comparable IIP2. Finally, another way to examine the difference between our SiGe and CMOS front-ends is to recast the 1-dB NF difference in terms of current consumption by looking at the authors’ earlier SiGe receiver [8], which achieved 4-dB NF at 14.5 mA. Thus, our SiGe WCDMA front-ends outperform the CMOS front-end by either 1 dB in sensitivity or 10 mA in current consumption. From these data, the authors conclude that, at the 0.25/0.35- m SiGe BiCMOS node and 0.25- m RF-CMOS node, the use of SiGe BiCMOS can result in moderately higher performance and/or lower power RF receiver designs compared to CMOS. Given that each technology is capable of meeting the minimum required performance to assure specification compliance, selection of the optimum technology for a given application can be made by weighing the potentially lower cost

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of the CMOS technology approach against the performance increase achievable in SiGe BiCMOS. ACKNOWLEDGMENT The authors thank the following colleagues with IBM Research, Yorktown Heights, NY: D. Beisser, for layout support, B. Gaucher, D. Friedman, M. Soyuer, and M. Oprysko, for their contributions, and IBM Microelectronics for chip fabrication. REFERENCES [1] L. E. Larson, “Integrated circuit technology options for RFICs—Present status and future directions,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 387–399, Mar. 1998. [2] S. K. Reynolds, B. A. Floyd, T. Beukema, T. Zwick, and U. Pfeiffer, “Design and compliance testing of a SiGe WCDMA receiver IC with integrated analog baseband,” Proc. IEEE, to be published. [3] “Third-generation partnership project (3GPP),” Tech. Spec. Group Radio Access Networks, Tech. Spec. 25.101, v. 3.0.1, Apr. 2000. [Online]. Available: www.3gpp.org. [4] S. K. Reynolds, B. A. Floyd, T. Beukema, T. Zwick, U. Pfeiffer, and H. Ainspan, “A direct conversion receiver IC for WCDMA mobile systems,” IBM J. Res. Dev., vol. 47, no. 2/3, pp. 337–354, Mar./May 2003. [5] L. E. Larson, “Silicon technology tradeoffs for radio-frequency/mixedsignal ‘systems-on-a-chip’,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 683–699, Mar. 2003. [6] V. Aparin and C. Persico, “Effect of out-of-band terminations on intermodulation distortion in common-emitter circuits,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 3, Jun. 1999, pp. 977–980. [7] V. Aparin and L. E. Larson, “Modified derivative superposition method for linearizing FET low noise amplifiers,” in Radio Frequency Integrated Circuits Symp., Fort Worth, TX, Jun. 2004, pp. 105–108. [8] S. Reynolds, B. Floyd, T. Beukema, T. Zwick, U. Pfeiffer, and H. Ainspan, “A direct conversion receiver IC for WCDMA mobile systems,” IEEE J. Solid-State Circuits, vol. 38, no. 9, pp. 1555–1560, Sep. 2003. [9] B. Floyd and D. Ozis, “Low-noise amplifier comparison at 2 GHz in 0.25-m and 0.18-m RF-CMOS and SiGe BiCMOS,” in Radio Frequency Integrated Circuits Symp., Fort Worth, TX, Jun. 2004, pp. 185–188. [10] B. Gilbert, “The multitanh principle: A tutorial overview,” IEEE J. SolidState Circuits, vol. 33, no. 1, pp. 2–17, Jan. 1998. [11] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [12] A. Parssinen, J. Jussila, J. Ryynanen, L. Sumanen, and K. Halonen, “A 2-GHz wide-band direct conversion receiver for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1893–1903, Dec. 1999. [13] R. Gharpurey et al., “A direct-conversion receiver for the 3G WCDMA standard,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 556–560, Mar. 2003. [14] E. M. Cherry and D. E. Hooper, “The design of wide-band transistor feedback amplifier,” Proc. Inst. Elect. Eng., vol. 110, no. 2, pp. 375–389, Feb. 1963. [15] H.-M. Rein and M. Moller, “Design considerations for very-high-speed Si-bipolar IC’s operating up to 50 Gb/s,” IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1076–1090, Aug. 1996. [16] D. Brunel, C. Caron, C. Cordier, and E. Soudee, “A highly integrated 0.25 m BiCMOS chipset for 3G UMTS/WCDMA handset RF subsystem,” in Radio Frequency Integrated Circuits Symp., Jun. 2002, pp. 191–194. [17] J. Jussila, J. Ryynanen, K. Kivekas, L. Sumanen, A. Parssinen, and K. A. I. Halonen, “A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 2025–2029, Dec. 2001. [18] J. Ryynanen, K. Kivekas, J. Jussila, L. Sumanen, A. Parssinen, and K. A. I. Halonen, “A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 594–602, Apr. 2003. [19] D. Y. C. Lie et al., “A direct-conversion W-CDMA front-end SiGe receiver chip,” in Radio Frequency Integrated Circuits Symp., Jun. 2002, pp. 31–34. [20] H. Sjoland, A. Karimi-Sanjaani, and A. A. Abidi, “A merged CMOS LNA and mixer for a WCDMA receiver,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1045–1050, Jun. 2003.

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[21] K. Lim, C.-H. Park, H. K. Ahn, J. J. Kim, and B. Kim, “A fully integrated CMOS RF front-end with on-chip VCO for WCDMA applications,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2001, pp. 286–287. [22] K.-Y. Lee et al., “Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 43–53, Jan. 2003. [23] F. Gatta, D. Manstretta, P. Rossi, and F. Svelto, “A fully integrated 0.18-m CMOS direct conversion receiver front-end with on-chip LO for UMTS,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 15–23, Jan. 2004. [24] J. Rogin, I. Kouchev, G. Brenna, D. Tschopp, and Q. Huang, “A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2239–2248, Dec. 2003.

Brian A. Floyd (S’98–M’01) received the B.S. (with highest honors), M.Eng., and Ph.D. degrees in electrical and computer engineering from the University of Florida, Gainesville, in 1996, 1998, and 2001, respectively. In 2001, he joined IBM. He is currently a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is engaged in millimeter-wave, RF, and high-speed wired integrated-circuit design. Dr. Floyd was the recipient of the Intersil/Semiconductor Research Corporation (SRC) Graduate Fellowship and the Pittman Fellowship while with the University of Florida. His doctoral research on wireless interconnects was a Phase One winner and a Phase Two first runner-up in the 2000 SRC Copper Design Contest.

Scott K. Reynolds received the B.S.E.E. degree from The University of Michigan at Ann Arbor, in 1983, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984 and 1987, respectively. In 1988, he joined IBM. He is currently a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His job responsibilities have involved analog and mixed-signal circuit design for high-speed communication systems, including optical, wired and RF wireless systems, and disk drive channels. He is currently primarily engaged in development of RF integrated circuits (RFICs) for high data-rate wireless communication links.

Thomas Zwick (M’00) received the Dipl.-Ing. (M.S.E.E.) and Dr.-Ing. (Ph.D.E.E.) degrees from the University of Karlsruhe, Karlsruhe, Germany, in 1994 and 1999, respectively. From 1994 to 2001, he was a Research Assistant with the Institut fur Höchstfrequenztechnik und Elektronik (IHE), University of Karlsruhe. Since February 2001, he has been with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research include wave propagation, stochastic channel modeling, channel measurement techniques, material measurements, microwave techniques, wireless communication system design, and millimeter-wave antenna design. He participated as an expert in the European COST231 Evolution of Land Mobile Radio (Including Personal) Communications and COST259 Wireless Flexible Personalized Communications. For the Carl Cranz Series for Scientific Education, he served as a Lecturer for wave propagation. Dr. Zwick was the recipient of the 1998 Best Paper Award presented at the International Symposium on Spread Spectrum Technques and Applications.

Lunal Khuon was born in Phnom Penh, Cambodia, in 1973. He received the B.S. (with highest honors) and M.S. degrees in electrical engineering from the Illinois Institute of Technology, Chicago, in 1994 and 1998, respectively, and is currently working toward the Ph.D. degree in electrical engineering at the Massachusetts Institute of Technology (MIT), Cambridge. From 1994 to 1998, he was a Development Engineer with Motorola Inc., Schaumburg, IL. From 1998 to 2000, he was an RF Subsystem Engineer and Payload System Engineer with Hughes Electronics, El Segundo, CA. In the summer of 2002, he was an intern with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research interests are in the area of RF and analog integrated-circuit design. He holds four patents.

Troy Beukema received the B.S.E.E. and M.S.E.E. degrees from Michigan Technological University, Houghton, in 1984 and 1988, respectively. From 1984 to 1988, he was a Research and Development Engineer with Hewlett-Packard in the area of communications test equipment. In 1989, he joined Motorola and contributed to the development of digital cellular wireless systems with a focus on digital signal-processing algorithm design and implementation. In 1996, he joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is currently a Research Staff Member involved in communications system research. His research interests include communication link system design and simulation with an emphasis on signal-processing algorithms for wireless and high-speed wireline channels.

Ullrich R. Pfeiffer received the Diploma and Ph.D. degrees in physics from the University of Heidelberg, Heidelberg, Germany, in 1996 and 1999, respectively. In 1997, he was a Research Fellow with the Rutherford Appleton Laboratory, Oxfordshire, U.K., where he developed high-speed multichip modules. In 2000, his research was based on high-integrated real-time electronics for a particle physics experiment with the European Organization for Nuclear Research (CERN), Geneva, Switzerland. In 2001, he joined IBM. He is currently a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research involves RF circuit design, high-power amplifier design at 60 and 77 GHz, high-frequency modeling, and packaging for 60-GHz and third-generation (3G) cellular systems.