1.5-bit mismatch-insensitive MDAC with reduced input capacitive loading E. Zhian Tabasy, M. Kamarei and S.J. Ashtiani A new mismatch insensitive 1.5-bit multiplying digital – analogue converter (MDAC) is proposed. This circuit samples the input in closed-loop form using the opamp in non-inverting configuration; hence, only the parasitic input capacitance loads the previous stage. This technique uses a fully-differential four-input OTA instead of two single-ended two-input OTAs to further improve power consumption and matching.
Introduction: Capacitive mismatch is one of the most important challenges in design of high-resolution analogue-to-digital converters. In particular, mismatch causes differential and integral nonlinearity in pipelined ADCs owing to inaccurate function of the multiplying DAC (MDAC) in the gain stages. Various methods have been proposed to alleviate this issue [1–4]. Some of them only address the gain error of the input signal, while the gain error still exists for the reference voltage [2, 3]. This Letter proposes a technique that significantly reduces the effect of mismatch in both input and reference signal paths in the pipelined ADC gain stages without considerable speed penalty. Proposed 1.5-bit MDAC with reduced mismatch sensitivity: The proposed method and the timing of three operating phases are illustrated in Fig. 1. In phase w0 , the input and output nodes of OTA are reset to the common-mode (CM) voltage, while C2 is discharged to zero volts and C1 is charged to Vr , where Vr is the appropriate reference voltage, þVref , 0 or 2Vref , associated with the output of the sub-ADC. Vin should be ready before the hold phase of the previous stage. This can be easily achieved by utilising extra circuitry such as in [5]. It is worth mentioning that, for generation of Vr , a large amount of error can be tolerated by using digital error correction (DEC) in 1.5-bit/ stage architecture. In phase w1 , the input signal is applied to the noninverting input of the OTA, thus sampled by C1. Hence, only the input parasitic capacitance of the OTA loads the previous stage, resulting in the reduction in power consumption. Assuming no settling error due to the finite bandwidth of the opamp, the output voltage at the end of w1 is: Cip;w1 þ C1 C1 Vr Vout;w1 ¼ Vin 1 þ C2 C2 Vout;w1 Cip;w1 þ C1 þ VOS 1þ Aw1 C2
ð1Þ
During w2 , C1 and C2 are replaced as shown in Fig. 1c. Neglecting the settling error, the final output voltage is given by: Cip;w2 Cip;w1 þ Vr Vout ¼ Vin 2 C1 C1 Vout;w1 Cip;w2 Cip;w1 þ VOS þ þ 2 ð2Þ Aw1 C1 C1 Vout;w2 C2 þ Cip;w2 þ Ctp1 þ VOS 1þ Aw2 C1 where Cip,w2 ¼ Ctp2. Since an estimation of the output voltage is generated in w1 , the voltage swing and consequently the slewing of the OTA is dramatically reduced during w2. As (2) implies, the reference voltage appears without any gain error in the final output voltage. More importantly, the gain error of the input signal can be reduced if Cip,w2 is equal to Cip,w1. To make the parasitic capacitances equal, a compensation technique is devised, as explained in the following Section. Compensation of parasitic capacitances: The complete fully-differential representation of the proposed technique is shown in Fig. 2. The compensation scheme consists of capacitors C3 and C4 equal to other feedback capacitors, and their adjacent switches as indicated by dashed lines in Fig. 2. Considering only the upper half circuit, C3 is discharged to zero during w0. Then, in w1 both plates of C3 are connected to Vinþ , hence only the top/bottom parasitic capacitances load the previous stage. During w2 , C3 is connected between the input of the OTA and CM voltage, removing the gain error at the cost of decreased feedback factor. The modified output voltage is: Cip;w2 Cbp3;4 Cip;w1 þ Vr Vout ¼ Vin 2 C1 C1 C1 Vout;w1 Cip;w2 Cbp3;4 Cip;w1 þ VOS þ 2 Aw1 C1 C1 C1 ð3Þ Vout;w2 þ VOS Aw2 C2 þ C3;4 þ Cip;w2 þ Ctp1 þ Cbp3;4 1þ C1 Here, Cbp3,4 is the bottom-plate parasitic capacitance of C3,4 , which is nominally equal to Cbp1 in Fig. 1b. The only remaining gain error is due to the mismatch between parasitic capacitances normalised to C1 value, which is much smaller than the normalised mismatch of C1 and C2. ϕ2 ϕ0,2
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Fig. 1 Proposed 1.5-bit mismatch-insensitive MDAC a Phase w0 b Phase w1 c Phase w2 d Settling response
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Here, Cip,w1 is equal to Cbp1 þ Ctp2 , while Cbp1 is the parasitic bottomplate capacitance of C1 and Ctp2 is the parasitic top-plate capacitance of C2 , as shown in Fig. 1b. VOS and Aw1 are the input-referred offset voltage and the low-frequency gain of the opamp, respectively.
d
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Fig. 2 Complete proposed 1.5-bit mismatch-insensitive MDAC with switches and parasitic-compensation scheme
Nevertheless, if the input parasitic capacitance of the OTA does not remain the same in w1 and w2 , the gain error still exists. This issue stems from the variation of the input CM voltage of the OTA, which is in the range of VCM – Vref to VCM þ Vref in phase w1. In w2 , however,
ELECTRONICS LETTERS 5th November 2009 Vol. 45 No. 23
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it is always equal to VCM. This issue is solved by using the four-input OTA shown in Fig. 3. During w0 the two inputs, Vinþ and Vin2 , are compared. If Vinþ is larger than Vin2 , the output wcmp goes high, hence the NMOS input pair of the OTA is sampling Vinþ , while the PMOS input pair is sampling Vin2 , and vice versa. As a result, the same parasitic capacitance is seen from the input of the OTA.
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Fig. 3 Utilised four-input boosted folded-cascode OTA with one pair of NMOS and one pair of PMOS inputs
The important specifications of the proposed MDAC are compared with the conventional MDAC in Table 1. The reference gain error is completely removed, and the input gain error is decreased proportional to the Cbp/C ratio. Although the feedback factor is 1/3 in w2 owing to the parasitic compensation method, the decreased swing of the output voltage in this phase relaxes the bandwidth requirement of the OTA.
Table 1: Performance comparison of conventional and proposed MDAC
Fig. 4 Output voltage settling error against capacitive mismatch
Conclusions: A novel capacitive mismatch-insensitive 1.5-bit MDAC is proposed for pipelined ADCs. A comparison of the proposed method to the conventional MDAC structure shows more than seven times better insensitivity to capacitive mismatch. Moreover, in the proposed technique only the input parasitic capacitance of the OTA loads the previous stage, which makes the design of each stage in a pipelined ADC almost independent. # The Institution of Engineering and Technology 2009 26 May 2009 doi: 10.1049/el.2009.1500 E. Zhian Tabasy, M. Kamarei and S.J. Ashtiani (School of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran, Campus #2, North Karegar St., Tehran, Iran) E-mail:
[email protected]
Parameter Number of required phases
Conventional MDAC 2
Output mismatch on Vin (sC) Output mismatch on Vref (sC) Worst-case feedback factor Input signal’s load Worst-case capacitive load
(1/2)sC sC 1/2 [in w2] 2C (1/2)C [in w2]
Proposed MDAC 2 þ reset phase p (Cip/C )( 2/2)sCp 0 1/3 [in w2] Cip (2/3)C [in w2]
Implementation and proof of concept: To validate the proposed method a 1.5-bit MDAC has been designed and simulated using HSPICE in a 0.18 mm 1P6M CMOS process with MIM capacitors. The supply voltage is set to the nominal 1.8 V with 1 V reference voltage. The sensitivity of the circuit to capacitive mismatch is tested for a values of 10 and 1%, and b values of 5 and 0.5%, where a and b are the relative bottom-plate and top-plate parasitic capacitances, respectively. The results for 50 Monte Carlo iterations are shown in Fig. 4. As expected, even for the largest a and b, the proposed method achieves almost seven times better accuracy compared to the conventional structure.
References 1 Quinn, P., and Pribytko, M.: ‘Capacitor matching insensitive algorithmic ADC requiring no calibrations’, Integr. VLSI J., 2003, 36, pp. 211–228 2 Lee, K.-S., Choi, Y., and Maloberti, F.: ‘SC amplifier and SC integrator with an accurate gain of 2’, IEEE Trans. Circuits Syst. II: Express Briefs, 2005, 52, (4), pp. 194– 198 3 Zare-Hoseini, H., Shoaei, O., and Kale, I.: ‘Multiply-by-two gain stage with reduced mismatch sensitivity’, Electron. Lett., 2005, 41, (6), pp. 289– 290 4 Goes, J., Pereira, J.C., Paulino, N., and Silva, M.M.: ‘Switched-capacitor multiply-by-two amplifier insensitive to component mismatches’, IEEE Trans. Circuits Syst. II: Express Briefs, 2007, 54, (1), pp. 29–33 5 Norouzpour-Shirazi, A., Mirhaj, A., Ashtiani, S.J., and Shoaei, O.: ‘A novel low power 1 GS/s S&H Architecture with improved analog bandwidth’, IEEE Trans. Circuits Syst. II: Express Briefs, 2008, 55, (10), pp. 971–975
ELECTRONICS LETTERS 5th November 2009 Vol. 45 No. 23
