Highly-Scalable Threshold Switching Select Device based on Chaclogenide Glasses for 3D Nanoscaled Memory Arrays Myoung-Jae Lee, Dongsoo Lee, Hojung Kim, Hyun-Sik Choi, Jong-Bong Park*, Hee Goo Kim*, Young-Kwan Cha**, U-In Chung, In-Kyeong Yoo and Kinam Kim, Semiconductor Device Laboratory, *Analytical Science Group, **Nano Fabrication Group, Samsung Advanced Institute of Technology, Gyeonggi-Do, Korea, 446-712 Tel: 82-31-280-8348, Fax82-31-280-9348, Email:
[email protected] Abstract We present here on a switch device made of a nitridizedchalcogenide glass for application in nanoscale array circuits. Previously, AsTeGeSi-based switches have had key issues with performance degradation over time. This is usually due to changes in the Te concentration in the device active region [13]. However, our AsTeGeSiN switches were able to overcome this limitation as well as scale down to 30 nm with an on current 7 2 of 100 μA (J > 1.1×10 A/cm8 ). Their cycling performance was shown to be greater than 10 . Also, we demonstrate a memory cell using a TaOx resistance memory with the AsTeGeSiN select device. Introduction In order to reach extreme high density such as 1Tbit, we will need to utilize several technologies such as 3D cell stacking, multi-level cell, and scaling down below 10 nm technology node at the same time. In a typical memory system, most memory devices (cells) are composed of a selector (switch device) and storage element. Up to now, traditionally the switch element has been Si based transistor or 2-terminal Si diode due to several limitations such as sufficient on current density and reliability. However currently several materials such as the mixed-ionicelectronic-conduction (MIEC) [4], bidirectional varistor [5] and oxide diodes have recently been proposed as a Si replacements for 3D stack process in crossbar arrauys. Previously chalcogenide glasses have been studied as a storage element due to their relatively stable amorphous and crystalline phases and long history in optical storage [1]. However threshold switching can also be observed in AsTeGeSi-based materials by utilizing electronic charge injection [2]. Figure 1(a) shows the issue of stray current paths which switches are required for. An SEM 2 2 image of our 500 × 500 (nm) and 30 × 30 (nm) devices are demonstrated in Fig. 1(b) and (c) respectively. The typical switching behavior AsTeGeSiN switche is shown in Fig. 1(d), while the inset shows a crossbar array of switch devices. N2 Plasma Nitridation Hardening We analyzed the degradation behavior of AsTeGeSiN switches after annealing to simulate degradation. Figure 2 shows the changes in switching behavior for (a) annealed and (b) N2 plasma treated + annealed samples. As seen in Fig. 2(b), the distribution of threshold voltage and current are greatly reduced for N2 plasma treated samples. XPS composition analysis in Fig. 2(c) and (d) of the two samples shows that indeed Te composition decreased for the non-N2 plasma treated samples. The threshold voltage and current distribution by cycle is shown in Fig. 2 (e) and (f) respectively. We based the modeling for off state conduction on the traplimited conduction (TLC) mechanism [5]. By using the TLC, we extract the total trap-density and trap distance of four samples in Fig. 3(a), (b), (c) and (d). Since the Te concentration can directly relate to the trap density, we conclude that the N2 plasma treatment provides a barrier to Te loss. The trap density and trap distance is shown in Fig. 4 at various process conditions. The Te loss in non-N2 treated samples for different annealing conditions is demonstrated in XPS analysis of Fig. 5(a). After annealing the element tellurium concentration decreased severely as annealing time increased as shown in Fig. 5(a). In contrast the N2 plasma
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treated sample is shown in Fig. 5(b). The decrease in the Te concentration is suppressed and a high Te concentration is maintained even post-annealing in Fig. 5(b). A closer examination reveals that N2 plasma treatment creates a thin SiN layer on the surface. We used SIMS analysis to compare SiN formation during deposition of the AsTeGeSiN film. Figure 6(a) shows the SIMS profiles for films deposited at 0%, 2%, 3%, and 5% N2 partial pressure during reactive sputtering. A comparison of the films deposited at 0% and 2% N2 partial pressure before and after N2 plasma treatment is shown in Fig. 6(b). We observed a thin SiN layer being formed at the surface. The 0% film shows the formation of a SiN film at the sample surface, while the 2% shows an increase SiN signal intensity. Device Performance and Scalability 8 Cycling performance was shown to be greater than 10 at pulse width of 1us as shown in Fig. 7. Next we fabricated 2 2 devices from 100 × 100 (μm) all the way down to 30 × 30 (nm) cell size. Figure 8(a) and (b) demonstrate threshold switching for all of our devices. Figure 8(c) shows the on current density of our cells increasing for smaller sizes as expected2 for a filamentary switching mechanism. For the 30 × 30 (nm) cell the 7 2 current density of 1.1×10 A/cm approaches Si diode current density values. By temperature dependant conduction measurements we found the activation energy as shown in Fig. 9(a) and (b). A band alignment diagram of our material is shown in Fig. 9(c). In addition, high-temperature XRD measurements o show that the amorphous phase is well maintained at past 600 C in Fig. 9(d). Integration As a proof of concept we fabricated a 1 switch and 1 resistor (1S-1R) memory cell. The TEM image of our integrated 500 nm cell is shown in Fig. 7(a). We used a W bottom electrode and a thin 2 nm AlOx layer to passivate the W surface. The TaOx resistive memory is fabricated by reactive sputtering then O2 plasma oxidation to form ~10 nm of insulating Ta2O5 layer [6]. The middle electrode is a Pt/TiN double layer. Next a 40 nm switch layer of AsGeTeSiN is deposited and capped with the top TiN electrode. The device performance of the individual elements is seen in Fig. 7(b). Finally the combined 1S-1R switching behavior is confirmed in Fig. 7(c). Conclusion We provide a summary of the performance of our AsTeGeSiN switch in Table I. By utilizing a nitrogen plasma treatment we were able to solve the aging degradation issue. We also demonstrated that the scalability of our device extends down to at least 30 nm with competitive switching current density. Additionally the fabrication temperature was only 200 o o C, but the device remained stable at 500 C post-processing making it suitable for stacked structures. References
1 Feinleib et al, Appl. Phys. Lett. 18, 254 (1971). 2 Ovshinsky, Phys. ReV. Lett. 22 (1968) 1450. 3 Y. Zhang, J. Appl. Phys., 102, 054517 (2007). 4 G. W. Burr, VLSI 2012, T5-4 (2012). 5 W. Lee, VLSI 2012, T5-2 (2012). 6 M. J. Lee, et al., Nature Mater. 10, 625-630 (2011).
2.6.1
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(b) V read
Ti
TiN
LRS LRS Switch off LRS Switch off (a) Switch off HRS Switch on
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(d) 2 DC 10 cycles x 10 cells
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Afte r
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Current (A)
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Fig. 1 (a) Switch role in cross-bar memory array. (b) SEM image of our 500 nm switch cell using TiN top and bottom electrodes. Conventional photolithography was used to define the cells. (c) SEM image of our 30 nm switch cell using Ti top and bottom electrodes. Electron beam lithography was used to define the cells. (d) Typical switching characteristics of 500 nm cell AsTeGeSiN.
0
100
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Switching cycles
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Fig. 2 Sample degradation observed after annealing at 30 × 30 (μm) cell sizes. (a) DC I-V cycling of annealed films (b) DC I-V cycling of N2 plasma treated and annealed films. (c) XPS concentration profiles of films showing low Te concentration for non-N2 treated films. (d) XPS concentration profiles of films showing high Te concentration for N2 treated films. (e) Threshold voltage distribution by cycle. (f) Threshold current distribution by cycle. 2
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Fig. 3 Measured I-V characteristics of (30 μm) cell size at various process conditions. Each sample was measured for 500 cycles. By using the TLC model we extracted the total trap density (Ntot) and inter-trap distance (•z). (a) As-deposited. (b) N2 treated. (c) Vacuum annealed. (d) N2 treated and annealed. (a) 25 (b) 3
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Fig. 4 Total trap density and trap distance plotted per sample condition from Fig. 3.
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Fig. 8 Scaling behavior of our AsGeTeSiN switches. (a) Device sizes from 100 × 2 2 100 (μm) to 10 × 10 (μm) . (b) Device sizes from 250 × 2 2 250 (nm) to 30 × 30 (nm) . (c) The current density
0.46 eV
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Fig. 9 (a) Temperature dependent conduction measurements for parameter extraction for TLC model. (b) Activation energy extracted from I-V of (a). Average Ea =~0.45 eV. (c) Band alignment of our device structure, calculated from (a) and (b) also o confirmed by UPS measurement. (d) High-temperature XRD of amorphous chalconitride structure up to 600 C. -3
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Selectivity ΔI@Iset, Iread (1/2 Vset)
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Endurance
DC: >103 , Pulse: >108 cycles
Processing temperature
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High Temperature stability
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Table I. Summary of our select device
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Fig. 10 Integration of AsGeTeSiN switches with RRAM memory cell. (a) TEM image of device stack structure. TaOx based ReRAM cell with W/Pt electrodes is below the switch with TiN electrodes. (b) I-V characteristics of the individual switch and memory elements. (c) Combined I-V measurement of the switch and memory cell. The operation window for unselected cells in the on and off state are clearly seen. 2.6.3
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Fig. 7 Cycling endurance of the AsGeTeSiN switch (a) DC I-V data for 100 cycles. (b) Pulse cycling measurements showing 8 2 2 endurance of 10 for 30 × 30 (μm) and 500 × 500 (nm) cells.
Ti / AsTeGeSiN / Ti
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Fig. 6 SIMS analysis of (a) AsGeTeSiN films sputtered under differing N2 partial pressure conditions. (b) Changes to the SIMS profile for 0% and 2% films after N2 plasma treatment. -3
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