2nd Intel MIC & GPU Programming Workshop at LRZ Volker Weinberg Momme Allalen Leibniz Supercomputing Centre (LRZ), Germany contact:
[email protected] For the 2nd time the Leibniz Supercomputing Centre as a PRACE Advanced Training Centre (PATC) organised a three day Intel MIC & GPU programming workshop at Garching next to Munich, dated April 27-29 2015. Around 25 people registered for the workshop and were able to gain experience on high-end GPGPU and Intel Xeon Phi coprocessor based systems. The materials for the presentations and hands-on sessions of the workshop were largely extended to reflect recent developments in parallel programming languages and latest experience with heterogeneous accelerator based systems at LRZ. The workshop covered various GPU and Xeon Phi programming models and optimisation techniques. While the first day focused more on the fundamentals of parallel programming with GPUs using CUDA, OpenACC, Python, R and MATLAB, the second day was devoted to various Intel Xeon Phi programming models like native mode vs. offload mode, parallelisation approaches like OpenMP, MPI, OpenCL and Intel Cilk Plus, as well as libraries like Intel MKL. On the last day invited speakers Dr.-Ing. Jan Eitzinger from the Regional Computing Centre Erlangen (RRZE) and Dr.-Ing. Michael Klemm from Intel gave lectures about advanced Intel Xeon Phi programming using low-level techniques like intrinsics or assembly language, advanced tuning methodologies and the new offload features from OpenMP 4.0. During many hands-on sessions the participants were able to gain experience on different GPU clusters and on the Intel Xeon Phi based system SuperMIC at LRZ (see inSiDE Vol. 12 No. 2 p. 76ff for a description of the system). In addition, the participants also had the opportunity to discuss optimisation techniques and test their own codes. Future Intel Xeon Phi trainings are planned by LRZ for 2016, taking place not only at LRZ, but also e.g. in Hagenberg, Austria, during the PRACE Autumn School 2016 and in the Czech Republic, where currently the largest Intel Xeon Phi based system in Europe (“SALOMON”) is prepared for production use at IT4Innovations / VŠB - Technical University of Ostrava.
Figure 1: Participants of the 2nd Intel Xeon Phi & GPU programming workshop at LRZ. The main lecturers Dr. M. Allalen, Dr. V. Weinberg, Dr. D. Brayford (LRZ), Dr.-Ing. M. Klemm (Intel) and Dr.-Ing. J. Eitzinger (RRZE) are each holding an Intel Xeon Phi coprocessor.
