Intel MIC Programming & HPC for Natural Hazard Assessment and Disaster Mitigation Workshops @ LRZ Volker Weinberg, Momme Allalen, Arndt Bode, Anton Frank, Dieter Kranzlmüller, Megi Sharikadze Leibniz Supercomputing Centre (LRZ), Germany Ondřej Jakl, Branislav Jansík, Martin Palkovic, Vít Vondrák IT4Innovations, Czech Republic Michael Bader Technical University of Munich (TUM), Germany Contact:
[email protected]
For the fourth time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations in the field of environmental sciences. The Czech-Bavarian Competence Centre was established in 2016 by the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of the Technical University of Munich (TUM) and the IT4Innovations National Supercomputing Centre of the Czech Republic to foster the CzechGerman collaboration in high performance computing. One of the main objectives of the Competence Centre is to organise a series of Intel Xeon Phi specific technical workshops combined with scientific symposia on topics like optimisation of simulation codes in environmental science. The successful series of workshops was initiated in February 2016 with an introductory Intel MIC programming workshop concentrating on the Salomon supercomputer at IT4I, currently the largest European Intel Knights Corner (KNC) based system, combined with a symposium on “SeisMIC – Seismic Simulation on Current and Future Supercomputers” at IT4Innovations (see inSiDE Vol. 14 No. 1 p. 76ff, 2016). The series was continued with extended Intel MIC programming workshops on the SuperMIC system at LRZ or on Salomon combined with a scientific workshop on “High Performance Computing for Water Related Hazards” in June 2016 at LRZ (see inSiDE Vol. 14 No. 2 p. 25ff, 2016) and a scientific symposium on “High performance computing in atmosphere modelling and air related environmental hazards” (see inSiDE Vol. 15 No. 1 p. 48ff, 2017) in February 2017 at IT4Innovations.
The fourth edition of this workshop series took place at LRZ on June 26 – 30, 2017. The 3-day Intel MIC programming workshop was organised as a PRACE Advanced Training Centre (PATC) event. It covered a wide range of topics from the description of the hardware of the Intel Xeon Phi co/processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications. The workshop mainly concentrated on techniques relevant for Intel Knights Landing (KNL) based many-core systems. During a public plenary session on Wednesday afternoon (joint session with the scientific workshop) eight invited speakers from IPCC@LRZ, IPCC@TUM, IPCC@IT4Innovations, Intel, RRZE, the University of Regensburg, IPP and MPCDF talked about Intel Xeon Phi experience and best practice recommendations for KNL based systems. Hands-on sessions were done on the KNC based system SuperMIC and two KNL test systems at LRZ. The workshop attracted over 35 international participants. The Intel MIC programming workshop was followed by a two-day symposium on “HPC for natural hazard assessment and disaster mitigation”. Eleven presenters from the Technical University of Munich, the Ludwig-Maximilians-University Munich, the University of Augsburg, the Munich Reinsurance Company and IT4Innovations addressed topics such as simulation of geological or meteorological hazards, floods, tsunamis, earthquakes, dangerous terrain motion, diseases and other hazards to society. A special focus was on demands and desired features of (future) simulation software, parallelisation for current and novel HPC platforms, as well as establishing scalable simulation workflows on supercomputing environments. The next Intel MIC programming workshops will take place at LRZ in June 2018 and will concentrate on the new KNL cluster “CoolMUC3” at LRZ.
Figure 1: Participants of the “Intel MIC programming workshop” at LRZ, June 26 – 28, 2017. The main lecturers in the first row (Dr. M. Allalen (LRZ), Dr. V. Weinberg (LRZ), Dr.-Ing. Michael Klemm (Intel), Dr.-Ing. Jan Eitzinger (RRZE), f.l.t.r.) are holding Intel Xeon Phi co-processors. © A. Podo (LRZ)
Figure 2: Participants during the social event (student organised GARNIX festival at Garching campus).
Acknowledgements The Czech-Bavarian Competence Centre for Supercomputing Applications is funded by the Federal Ministry of Education and Research. The Intel MIC programming workshop was financially also supported by the PRACE-4IP and PRACE-5IP projects funded by the European Commission’s Horizon 2020 research and innovation programme (2014-2020) under grant agreements 653838 and 730913.
References [1] https://www.lrz.de/forschung/projekte/forschung-hpc/CzeBaCCA/ [2] http://www.training.prace-ri.eu/ [3] https://www.lrz.de/services/compute/courses/ [4] http://training.it4i.cz/kurzy-it4innovations/
