To make understandable Verilog HDL coding style for synthesis ... Verilog HDL:
A Guide to Digital Design and Synthesis, Samir Palnitkar 2/e, Pearson.
3/4 B.Tech - FIFTH SEMESTER FE 3
Verilog HDL
Credits: 4
Lecture : 4 periods/week Internal assessment: 30 marks Tutorial: 1 period /week Semester end examination: 70 marks -------------------------------------------------------------------------------------------------------------------------Course Objectives:
To introduce basics of Verilog HDL language, including its use in synthesis of digital designs To make understandable Verilog HDL coding style for synthesis To enable to design of digital systems with Verilog HDL To understand Modelling, Testbench, Simulation and verification of designs with Verilog HDL
UNIT-I Introduction to HDL’s, Simulation, Capabilities of Verilog, Basic concepts, Data Types, System tasks and Compiler directives, modules, ports, Gate level modeling, Gate types, Gate delays, Examples. UNIT- II Dataflow modeling, continuous assignments, Delays, Expressions, Operators, Operands, Operator types, Examples, Writing Test Bench. UNIT-III Behavioral modeling, Structured procedures, Procedural Assignments, Timing controls, Conditional Statements, Multiway Branching, Loops, Sequential and parallel blocks, Generate Blocks, Examples. UNIT- IV Tasks, Functions, Procedural continuous assignments, Overriding parameters, Conditional compilation and execution, timing scales, System tasks UNIT-V Timing and delays, Types of delay models, Path delay modeling, Timing checks, Switch level modeling, Switch modeling elements, Examples. UNIT- VI User defined primitives, Uses of programming language interface. UNIT- VII Finite state machines: Mealy and Moore state Models, Design of FSM using Verilog HDL.
UNIT- VIII Logic synthesis, Impact of logic synthesis, HDL Synthesis, Synthesis design flow, Verification of the Gate-Level Net list, modeling tips for logic Synthesis, Examples of synthesis.
Learning Resources Text Books: 1. Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar 2/e, Pearson Education,2005. 2. Digital Design, M.Morris Mano & Michael D.Ciletti, 4/e, Pearson Education References: 1. . Fundamentals of Digital Logic with Verilog Design . Stephen Brown & Zvonko Vranesic,TMH, 2002. 2 A Verilog HDL Primer, .J. Bhasker 2/e, BS Publications, 2001 3 . Advanced Digital Design with the Verilog HDL . Michael D. Ciletti, PHI, 2005.
