Introduction to Digital Design using Verilog. EE370 ... sequential use for
synthesizing digital hardware fpga asic ... units, Kp = 400. Can Verilog model this
?
Introduction to Digital Design using Verilog EE370 Ashish Bhatia
What is Verilog? models digital hardware to what extent? models digital hardware combinatoric sequential use for synthesizing digital hardware fpga asic
modeling digital hardware to what extent?
A CMOS inverter has nMOS transistor with L = 10 units, W = 20 units, Kn = 400 and pMOS transistor with L = 10 units, W=40 units, Kp = 400 Can Verilog model this?
A CS amplifier has gain = -10 and cut-off freq = 20 MHz Can Verilog model this?
A spice generated netlist of resistors and capacitors Can Verilog model this?
An inverter with Tr = 1 ns, Tf = 500 ps and Tp = 800 ps Can Verilog model this?
Can Verilog model this? A
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Can Verilog model this? Q(n)
X
Q(n+1)
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modeling digital hardware combinatoric sequential
consider combinatoric first
NOT Gate module Not ( input wire x, output wire y); assign y = ~x; endmodule
NOT Gate module Not ( input wire x, output wire y); assign y = ~x; endmodule
NOT Gate module Not ( input wire x, output wire y); assign y = ~x; endmodule
NOT Gate module Not ( input wire x, output wire y); assign y = ~x; endmodule
NOT Gate (of parallel bus) module Not ( input wire [7:0] x, output wire [7:0] y); assign y = ~x; endmodule
AND Gate module And ( input wire x, input wire y output wire z); assign z = x&y; endmodule
do Nand, Nor, Xor, Or gate yourself
Hardware Abstraction behavioral highest level of abstraction farthest from hardware closest to ideas (thinking) dataflow hardware described in boolean (logic) combinatoric sequential structural hardware described in terms of fundamental gates
Let us analyze 1-bit adder for all three cases
Behavioral design (adder) module adder_b(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; assign {carry, sum} = in1 + in2; endmodule
Behavioral design (adder) module adder_b(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; assign {carry, sum} = in1 + in2; endmodule Addition is a high level construct Verilog compiler will generate the code for addition
DataFlow Design (adder) module adder_d(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; assign sum = in1 ^ in2; assign carry = in1 & in2; endmodule
DataFlow Design (adder) module adder_d(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; assign sum = in1 ^ in2; assign carry = in1 & in2; endmodule Boolean logic - more fundamental construct than addition
Structural Design (adder) module adder_s(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; and g0(carry,in1,in2); xor g1(sum,in1,in2); endmodule
Structural Design (adder) module adder_s(in1, in2, sum, carry); input wire in1, in2; output wire sum, carry; and g0(carry,in1,in2); xor g1(sum,in1,in2); endmodule
Assuming and and xor gates are available
Structural Design (adder) module adder_s(in1, in2, sum, carry); //Assume only NAND gates are available input wire in1, in2; output wire sum, carry; wire signal1, signal2, signal3;//intermediate wires nand n0 (signal1, in1, in2); nand n1 (carry, signal1, signal1); nand n2 (signal2, in1, signal1); Assuming only nand gates are nand n3 (signal3, in2, signal1); available nand n4 (sum, signal2, signal3); endmodule
what about sequential elements?
let us consider D F/F
D F/F module D_FF ( input wire clk, input wire d, output reg q ); always @(posedge clk) begin q
