Progress in Electromagnetic Research Symposium 2004, Pisa, Italy, March 28 - 31
3D Modeling and Circuit Model Extraction of Vias in Multilayer Printed Circuit Boards Giuseppe Selli*, Jianmin Zhang*, Mauro Lai**, Andrea De Luca**, Antonio Ciccomancini** Antonio Ciccomancini**, Bruce Archambeault***, Giulio Antonini**, James. L. Drewniak*, Antonio Orlandi**, Jun Fan****, James L. Knighten**** *EMC Laboratory, Department of Electrical and Computer Engineering, University of Missouri-Rolla, 1870 Miner Circle, Rolla, MO, 65401, USA. **Uaq EMC Laboratory, Department of Electrical and Computer Engineering, University of L`Aquila, Poggio di Roio, L’Aquila, I-67040 Italy. ***IBM Co., Research Triangle Park, NC, 27709, USA ****NCR Corporation, San Diego, CA, 92127, USA e-mails:
[email protected],
[email protected],
[email protected],
[email protected] [email protected],
[email protected],
[email protected],
[email protected] [email protected],
[email protected],
[email protected]
Abstract The analysis of vias in multilayered geometries helps to improve the modeling of PCB’s and engineer a good solution from a signal integrity point of view [1-5]. The modeling of such elements is usually performed with full wave simulation tools. Although this is not an optimum approach for circuit analysis, it provides the insight needed for PCB layout. The extraction of circuit models to use in a SPICE tool avoids time consuming 3D simulations and simplifies the board design. Several methods can be employed to extract equivalent circuits from S-parameters, each of which is characterized by a trade-off between accuracy and complexity. Moreover, the need of an accurate model mainly depends upon the frequency range of interest, in fact, the wider the range is, the more complexity is needed in the equivalent circuit in order to reproduce the initial S-parameter data, which can be considered as the reference to estimate the accuracy of the model itself. 1 Circuit Extraction Approaches The via geometry under test is shown in Figure 1. It consists of a multilayer printed circuit board with six solid metal planes of dimensions 300 mils x 300 mils, the planes are 10 mils spaced apart in the z direction, except the middle planes, which are only 5 mils spaced apart. A through hole via connects two 8 mils wide striplines and another via is embedded into the multilayer geometry and shorted to all the six planes.
Figure 1. Via geometry under test.
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Progress in Electromagnetic Research Symposium 2004, Pisa, Italy, March 28 - 31
The substrate of the board is air, while the input and output ports are located at the end of the two striplines with the reference planes being, respectively, the second and the sixth solid plane from the top. The S-parameters are calculated by modeling the geometry with two different 3D full-wave simulation tools, i.e., CST Microwave Studio (MWS) and an FDTD algorithm. Several circuit extraction methods are employed to obtain an equivalent circuit representation of the via geometry from the S-parameter data and the results are compared with a simple Π circuit with element values extracted using a quasi-static PEEC approximation. The network topology imposed for the quasi-static PEEC approximation circuit extraction is shown in Figure 2, and consists of a Π network with two shunt capacitances and one series inductance. 1.78 nH
I1
V1
0.25 pF
I2
0.25 pF
V2
Figure 2. Equivalent circuit extracted with a quasi-static PEEC approximation.
Once the S parameter data are computed, the CST MWS circuit extraction feature yields an equivalent circuit based on a cascaded series of a T-structured transmission line model, the left and right end of this cascade of networks being the two ports of the modeled geometry as shown in Figure 3. As expected, the larger the number of cascaded elements, the better the accuracy and the complexity of the model . T-section I2
I1 Z
Z
Z
Y
Z Y
Z
Z Y V2
V1
Z = R/2 + j L/2 , Y = G + j C Figure 3. MWS circuit model topology extracted from the S-parameter data.
A Vector Fitting Spice Technique (VFST) can be also employed to extract an equivalent circuit from the results of the simulations. The S-parameter data are converted into Y-parameters and a Π topology based on these parameters is enforced as shown in Figure 4. The three admittances are then fitted using a vector fitting algorithm [6], and three sets of poles/residues are given for each element in the Π network. An equivalent circuit can be obtained from these three sets of poles/residues using closed form expressions [7]. According to these formulas, each real pole with the corresponding residue gives 2 circuit elements, whereas 4 circuit elements are calculated from a pair of complex conjugate poles with the corresponding residues. I1
Ybb = -Y21
I2
V1
V2
Ybb = Y11+ Y21
Figure 4.
Ycc = Y22+Y21
network representation of the circuit extracted with the VFST.
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Progress in Electromagnetic Research Symposium 2004, Pisa, Italy, March 28 - 31
2 Results The different circuits extracted are simulated using a SPICE based tool or in MWS (the extraction feature gives this option), the S-parameter data are calculated and then compared in Figure 4 and Figure 5 with the original ones obtained by the 3D full-wave simulations tools. In particular, the circuit extracted with CST MWS consists of 25 cascaded T sections, each of which is realized with the same circuit elements (Table 1) and the extraction frequency set to be equal to 3 GHz. On the other hand, the circuit extracted with the VFST consists of 160 circuit components constituting each branch of the network, for a total of approximately 500 elements. Circuit Element R L G C
Value 4.12 m 54 nH 0 S 146 pF
Table 1. Circuit elements constituting each T-network in the CST MWS model. 0 -10 -20 EZ-FDTD 3D model MWS 3D model Π model MWS ckt VFST
|S11 | [dB]
-30 -40 -50 -60 -70
1
2
3
4 5 6 Frequency [GHz]
7
8
9
10
Figure 5. |S11| comparison between the the 3D modeling tools and the different equivalent circuit simulations.
0.5 0 -0.5
|S21 | [dB]
-1 -1.5 EZ-FDTD 3D model MWS 3D model Π model MWS ckt VFST
-2 -2.5 -3 -3.5
1
2
3
4 5 6 Frequency [GHz]
7
8
9
10
Figure 6. |S21| comparison between the results from the 3D modeling tools and the different equivalent circuit simulations.
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Progress in Electromagnetic Research Symposium 2004, Pisa, Italy, March 28 - 31
4 Discussion and Conclusion The comparison of the S11 magnitude obtained from the two different 3D modeling tools and the simulations of the two complex circuits shows a consistent agreement over the frequency range of interest. On the other hand, the data obtained from the simulation of the simple circuit extracted using a quasi-static PEEC approximation shows a similar trend in the magnitude of S11, but different values. In fact, the simplicity of this model does not allow an accurate equivalent representation of the via geometry over the frequency range of interest and the model fails at higher frequencies. The comparison of the S21 magnitude shows the accuracy of the circuit model extracted with the VFST applied to the S-parameters obtained from the simulation of the via model in CST MWS. In fact, the SPICE simulation of this equivalent model perfectly overlaps with the initial data. Similarly, the simulation of the circuit extracted using the feature of CST MWS shows a slightly less accuracy in the equivalent representation of the via geometry, and the difference is no more than half a dB over the entire range of frequency. Finally, the simulation results of the simple circuit show that the model is not longer valid at higher frequencies. In fact, the magnitude of S21 no longer follows the trend of the other curves, so that the discrepancy is approximately 2 dB at 10 GHz. Three different methods for circuit extraction are presented in this paper. Each of these is characterized by a different compromise between the accuracy of the representation, when looking at the reconstructed S parameters, and the complexity of the equivalent circuit. The circuit extracted using a quasi-static PEEC approximation has a simple topology, but the simulation of the model gives the less accurate S-parameter data, when compared with the initial one. On the other hand, the Vector Fitting Spice Technique gives a very accurate circuit representation over the frequency range of interest, however, with a high complexity. REFERENCES 1.
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