A 12-GHz GaInP/GaAs HBT VCO Based on Push-Push Output ...

A 12-GHz GaInP/GaAs HBT VCO Based on Push-Push Output Extraction from Capacitive Common-Node Jongsik Kim, Sanghoon Jeon*, Seongdae Moon*, Nam-Young Kim, and Hyunchol Shin RFIC Research Center, Kwangwoon University, Seoul 139-701, Korea, * Knowledge*on Inc., Iksan 570-210, Korea Abstract — A new push-push VCO architecture takes the second harmonic output signal from a capacitive common-node in a negative-gm oscillator topology. The generation of the 2nd harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. A prototype 12-GHz MMIC VCO realized in GaInP/GaAs HBT achieves an output power of -5 dBm, a phase noise of -108 dBc/Hz at 1 MHz offset while drawing 10.7 mA from a 2.4-V supply, which is equivalent to -175.8 dBc/Hz of VCO figure-ofmerit. Index Terms — VCO, Push-Push, Negative-gm Oscillator

new push-push technique that extracts an output signal from a capacitive common-node between the base nodes of crosscoupled transistors in a negative-gm oscillator. Simulation and measurement show that the technique is functional and advantageous for MMIC VCO implementation. cc

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I. INTRODUCTION

These issues can be mitigated by lowering the operation frequency of the VCO core while extracting a wanted higher output frequency. A frequency doubler combined with a VCO is a good way to achieve the goal except that it requires additional circuitry and current consumption [1]. Push-push architecture adds two anti-phased output signals from dual balanced VCOs so that it only extracts 2nd harmonic component but suppresses fundamental signals. There have been reported two architectural variations so far. The output signals can be combined at the common collector node [2,3] or at the common emitter node [4,5] of a balanced VCO. However, it is disadvantageous that the hardware complexity needs to be doubled due to the need of dual VCOs for balanced output, or the common-mode rejection get worse due to the additional impedance attached to the common emitter node of a differential pair. A negative-gm differential oscillator topology with crosscoupled transistors is the most preferred topology in integrated circuit VCO implementations because of the advantage of the inherent differential signaling [6]. In this work, we propose a

0-7803-8846-1/05/$20.00 (C) 2005 IEEE

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An MMIC VCO is surely one of the most critical circuit blocks to realize an integrated RF and microwave transceiver that aims at higher frequency, lower power consumption, and smaller size. As the operation frequency of an integrated VCO goes over several tens-of-GHz, number of circuit issues arises; 1) a sub-nH inductance is needed for LC-tank, which would suffer from severe process variation, 2) a tank quality factor degrades rapidly which can be compensated only by a larger current consumption, 3) unwanted VCO signal coupling to other parts of transceivers increases.

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Figure 1. Circuit schematic of a negative-gm differential VCO

II. ARCHITECTURE AND OPERATION PRINCIPLE Fig. 1 shows the circuit schematic of a conventional negative-gm differential oscillator. The cross-coupled Q1,2 generates a negative gm to compensate the tank loss. The capacitive voltage divider composed of C1 and (C2+Cπ of Q1,2) is used to optimize the loop gain (~ 3) by maximizing the tank swing and optimizing the signal amplitudes at the base nodes that are fed back from the collectors of Q1,2. It is known that the phase noise degrades rapidly if the base voltage swing goes over a certain optimum value (~100mVp) since Q1,2 goes into deep saturation region [7]. Meanwhile, it is generally believed that the common-node of capacitive voltage dividers, node CN, behaves as a virtual ground just like the common emitter node E for the fundamental frequency (ωo) even if it is not connected to a real circuit ground. We find out that the capacitive common-node CN would be a very effective summing node for the 2nd harmonics (2ωo) of the differential signals (V+, V-) of the VCO core. Note that the capacitive common-node can be regarded as a common base node compared with the conventional common emitter or collector node. The advantage of using the node CN for output extraction is that it does not require any additional circuitry such as frequency doubler to get 2ωo-output other than the conventional negative-gm oscillator circuit, and does not

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where Is is the saturation current and VT is the thermal voltage. Fig. 3 illustrates conceptually how the upper halfperiod of vBE is distorted via voltage-clipping when the base current is rather a big sinusoidal signal.

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Before we proceed to the circuit design, it will be essential to understand how the 2nd harmonics are generated from the VCO core and extracted from the node CN. A simple 12-GHz VCO circuit is designed based on the circuit schematic of Fig. 1 with a 6-GHz LC tank. Although the circuit operates quite nonlinearly, it would be helpful to use linear circuit analysis concept when appropriate. First, let us look at the nonlinear switching characteristics of the base-emitter junction diode. Fig. 2 gives the simulated waveforms of the base-emitter voltage (vBE) and the base input current (iB) of Q1 and Q2. Note that the base current leads the base-emitter voltage by 90o due to the base input capacitance. It is interesting to note that the upper half period of vBE is apparently distorted compared to the dashed-line undistorted sinusoidal waveform. It is because of the exponential current-voltage relationship of the base-emitter junction diode given as,

The second cause of the 2nd harmonic generation is the different time-constants involved in charging and discharging the base-emitter junctions. The time constants at the baseemitter nodes is given as

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reduce the common-mode impedance at node E. It has been reported that an additional inductance inserted between the node E and the tail current source Io can increase the commonmode impedance and the signal swing at node E, but all at the cost of an additional bulky inductor [8].

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As a result, the base voltage signal will contain significant amount of 2nd harmonic distortion components. When they are summed at the capacitive common-node CN, the fundamental components at ωo are cancelled out due to the 180o phase difference and only the 2nd harmonic components are added constructively, which results in 2ωo output as shown in Fig. 5. 100 75 50

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Figure 5. Voltage waveform at the capacitive common-node.

In order to quantify the power efficiency of this technique, the voltage swing (VCN) at the capacitive common-node is simulated as the tank swing (Vtank) increases, as shown in Fig. 6. Since Vtank usually needs to be about 1 Vp for good phase noise performance, we can obtain 60 mVp of VCN. It is big

Figure 3. Distortion of the base voltage waveform.

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enough to take a reasonable output power with an output buffer amplifier. Therefore, CN node could be an efficient point to take a 2ωo-output signal without significant powerdissipation overhead. Voltage Swing at CN (mV)

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Figure 6. The voltage swing at the capacitive common node vs. the voltage swing at the tank.

of 5 mA. In order to maximize the phase noise performance as well as the 2ωo output swing at the node CN, C1 and C2 are determined to be 785 fF considering 97.5 fF of Cπ, which results in an optimum base voltage swing of 200 mVp. The single-ended voltage swing at the tank (Vc- or Vc+) and the node CN is designed to be 630 mVp and 77 mVp, respectively. The simulated phase noise is -113.2 dBc/Hz for 12 GHz output at 1-MHz offset. A push-push output is extracted from node CN through a cascode buffer amplifier (Q5,Q6) which is biased by a constant current source (Q7). Rb7 is set to be 300 Ω by trading off the output signal power and the phase noise degradation. For the simplicity of measurement, a commercial bias-tee is used as a load of the buffer amplifier for 50Ω-driving. The voltage gain of the buffer amplifier is designed to be 7.3 dB at 12 GHz, which produces output power of -5dBm at the 50-Ω load.

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Figure 8. Micro photograph of the fabricated VCO.

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IV. MEASUREMENT RESULTS Figure 7. Circuit schematic of the 12-GHz VCO extracting output at the capacitive common-node

III. PROTOTYPE VCO DESIGN A 12-GHz MMIC VCO is designed to prove the concept of the new push-push output extraction technique at the capacitive common-node. Fig. 7 gives the circuit schematic. It consists of a negative-gm oscillator and an output buffer amplifier to take the 2ωo output signal from the node CN. LC-tank is resonant at 6-GHz. Spiral inductors of 0.7 nH with Q-factor of 21 at 6-GHz are used. Reverse-biased basecollector junction capacitance of 4x2x20 um2 HBT is employed for the purpose of varactor, whose capacitance varies from 176.3 fF to 225.4 fF. A 3.06-% of frequency tuning ratio is simulated at around a 12-GHz. Cross-coupled HBTs (Q1, Q2) of 1x2x4-µm2 emitter size are used for negative gm-generation. The HBT shows a peak fT of 56 GHz and a peak fMAX of 105 GHz at a collector current

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The VCO is fabricated in a commercial GaInP/GaAs HBT technology. Fig. 8 shows the chip photograph. The total area including pads and output buffer is 729×737µm2. It is measured by using an RF on-wafer probe. The VCO core and the output buffer draws 10.7 mA and 13.1 mA from a 2.4-V supply, respectively. Fig. 9 shows the output spectrum at 11.89 GHz. It clearly exhibits the new push-push output extraction technique is functional at this Ku-band. Phase noise is measured to be -108 dBc/Hz at 1MHz offset. A VCO figure-of-merit is widely used for fair comparison of VCO performances at different frequencies and different power consumptions as following,  f   P  (3) FOM = Φ ( f m ) − 20 log osc  + 10 log diss  1 f mW    m  where Φ(fm) is the measured phase noise, fosc is the oscillation frequency, fm is the offset frequency. The VCOFOM is calculated to be -175.8dBc/Hz, which is quite comparable to the previously published results by other groups.

The suppression of the 6-GHz fundamental component against the 12-GHz output is measured to be -6 dBc as shown in Fig. 10. It is much worse than the simulated result of -25.2 dBc. It could be caused by unexpectedly high signal coupling from the tank directly to the output port or unexpectedly high signal swing at the power and ground lines. Although this level of suppression may not be good enough for practical application, we believe it can be improved by more than 10 dB simply by adopting a tuned load at the buffer amplifier. Fig. 11 measures the frequency tuning range to be 11.65 GHz ~ 12.08 GHz against the tuning voltage (Vtune) of 0 ~ 2.5V. The negative VCO gain is obtained since the reversebiased base-collector junction capacitance increases as Vtune increases. The output power varies within the range of -4.3 dBm ~ -6.1 dBm across the whole oscillation frequency range where the cable loss of 2.4dB at 12GHz is taken into account.

[6] H. Jacobsson, S. Gevorigan, M. Mokhtari, C. Hedenaes, B. Hansson, T. Lewin, H. Berg. W. Rabe, A. Schueppen, “Low Phase Noise Low Power IC VCOs for 5-8-GHz Wireless Applications” IEEE Tran. Microwave Theory and Tech., vol. 48, no. 12, pp. 2533-2539, Dec. 2000. [7] M. Margari, J. Tahm, R. Meyer, M. Deen, “A Low-Noise LowPower VCO with Automatic Amplitude Control for Wireless Applications” IEEE J. Solid-State Circuits., vol. 34, no. 6, pp. 761-771, Dec. 1999. [8] E. Hegazi, H. Sjoland, A. Abidi, “A Filtering Technique to Lower LC Oscillator Phase Noise” IEEE J. Solid-State Circuits., vol. 36, no. 12, pp. 1921-1930, Dec. 2001.

VII. CONCLUSION A new push-push output extraction method from a capacitive common-node is presented based on conventional negative-gm oscillator architecture. A prototype Ku-band MMIC VCO realized in GaInP/GaAs HBT technology achieves -108 dBc/Hz of the phase noise at 1MHz offset, -5 dBm of output power, and 3.6 % of the frequency tuning range at 12-GHz output frequency. We believe the technique would be instrumental for MMIC oscillator design at several tens-ofGHz with low power consumption and good phase noise performance.

Figure 9. Output spectrum and phase noise measurement

ACKNOWLEDGEMENT This work was supported by University IT Research Center Project of the Ministry of Information and Communication, Korea. The authors wish to thank Knowledge*on Inc. for the VCO fabrication using its 6 inch InGaP/GaAs HBT foundry service. REFERENCES

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[1] D. Baek, J. Kim, D. Kang, S. Hong, “Low Phase Noise Ku Band Frequency Multiplied and Divided MMIC VCO using InGaP/GaAs HBT Technology” IEEE MTT-S Int. Microwave Symp. Dig., pp. 2193-2196, June 2003 [2] J. Kim, D. Baek, S. Jeon, J. Park, S. Hong, “A 60GHz InGaP/GaAs HBT Push-Push MMIC VCO,” IEEE MTT-S Int. Microwave Symp. Dig., pp. 885-888, June 2003. [3] L. Dussopt, G. M. Rebeiz, “A Low Phase Noise Silicon 18-GHz Push-Push VCO” IEEE Microwave and Wireless Comp. Lett., vol. 13, no. 1., pp. 4-6, Jan. 2003 [4] K. Kobayashi, A. K. Oki, L. T. Tran, J. C. Cowles, A. GutierrezAitken, F. Yamada, T. Block, D. C. Streit, “A 108-GHz InP HBT Monolithic Push-Push VCO with Low Phase Noise and Wide Tuning Range” IEEE J. Solid-State Circuits, vol. 34, no. 9., pp. 1225-1232, Sept. 1999. [5] C. Lam, B. Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-um CMOS Technology” IEEE J. Solid-State Circuits, vol. 35, no. 5., pp. 788-794, May 2000.

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Tuning Voltage (V) Figure 11. Frequency tuning characteristics and output power.