IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005
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A 60-GHz Push-Push InGaP HBT VCO With Dynamic Frequency Divider Ockgoo Lee, Jeong-Geun Kim, Kyutae Lim, Joy Laskar, Fellow, IEEE, and Songcheol Hong, Member, IEEE
Abstract—We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30 GHz differential outputs and a single-ended 60 GHz push-push output. The 30 GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than T 2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.
Fig. 1. Block diagram of the proposed 60-GHz PLL frequency synthesizer.
Index Terms—Frequency divider, InGaP/GaAs heterojunction bipolar transistor (HBT), phase-locked loop (PLL), voltagecontrolled oscillator (VCO).
I. INTRODUCTION
R
ECENTLY, the rapidly increasing demand for the broadband communication service in wireless and radar systems has stimulated research on millimeter-wave frequency band [1]. Signals at around 60 GHz with severe atmospheric attenuation provide excellent frequency reusability. In all these wireless communications and radar systems, frequency synthesizers are required for frequency translation and channel selection. Furthermore, the increasing demand of these systems has driven the development of cost effective and high performance millimeter-wave frequency sources. InGaP/GaAs heterojunction bipolar transistors (HBTs) have somewhat lower and than CaAs pseudomorphic high-electron-mobility transistors (PHEMTs) or InP based transistors. However, these HBTs are very attractive to be used for millimeter wave application due to their low 1 noise, reliable fabrication process, and lower manufacturing cost. High frequency voltage-controlled oscillator (VCO) and frequency divider play a crucial role in implementing high frequency phased-locked loop (PLL). This is because in the PLL Manuscript received February 25, 2005; revised May 13, 2005. This work was supported by the Agency for Defense Development, Korea, through the Radio Detection Research Center, Korea Advanced Institute of Science and Technology. The review of this letter was arranged by Associate Editor F. Ellinger. O. Lee is with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea and also with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0269 USA (e-mail:
[email protected]). J.-G. Kim and S. Hong are with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea. K. Lim and J. Laskar are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0269 USA. Digital Object Identifier 10.1109/LMWC.2005.856847
Fig. 2.
Schematic of the 60-GHz push-push VCO functional block.
frequency synthesizer, the VCO, and the frequency divider operate at the highest possible frequency as shown in Fig. 1. The operating frequency of the VCO and frequency divider has been increased for high frequency PLL [2], [3]. As operating frequency increases, it becomes difficult to implement an inductor and a varactor with a high quality factor. The use of push-push principle is a practical solution with good frequency stability and low phase noise, and thus allows the extension of the usable frequency range. Also, compared to conventional PLL architecture, a high frequency divider is not required in the PLL architecture using push-push VCO. The operating frequency of the frequency divider in the first stage is half of the desired output frequency. This paper presents 60 GHz push-push VCO with a dynamic frequency divider for PLL using cost effective InGaP/GaAs HBT technology. II. DESIGN OF THE 60-GHZ PUSH-PUSH VCO Fig. 2 shows the schematic of the push-push VCO functional block, which consists of a balanced VCO, two differential amplifiers, and a balanced frequency doubler. This architecture is desirable for high frequency operation using low cost technology. To generate negative resistance, a common base induc-
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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 15, NO. 10, OCTOBER 2005
Fig. 3. Block diagram of the dynamic frequency divider.
tive feedback is applied to both HBTs, whose bases are interconnected through the microstrip line inductor (MLI1, MLI2) [4]. The oscillation frequency is determined by 4 microstrip line resonator (MLR1, MLR2). The core current is controlled by current mirror. Because two differential output pairs are needed to drive a frequency divider and a frequency doubler, two differential amplifiers are used as active baluns. The frequency doubler is biased at near pinch off region, and thus large second harmonics can be generated. To transfer maximum power to output stage, an output matching circuit is optimized at the second harmonic frequency.
Fig. 4. Schematic of the proposed dynamic frequency divider.
III. DESIGN OF THE DYNAMIC FREQUENCY DIVIDER USING ACTIVE LOADS WITH INDUCTIVE PEAKING Because the first stage of any frequency divider has to operate at the same high frequency as the VCO, a high speed frequency divider is required. The dynamic frequency divider is suitable for high frequency operation. The dynamic frequency divider is based on the principle of regenerative frequency division. Fig. 3 shows the block diagram of the dynamic frequency divider. The input signal is applied to a mixer, which is followed by a low-pass filter and an amplifier. The output signal is fed back to the other mixer input. The maximum operating of the dynamic frequency divider is determined frequency . For the circuit to divide by the loop’s cutoff frequency properly, the loop gain at 2 must be at least unity. Normally, resistive loads are used in the upper differential pair of , the inductive peaking dynamic divider. For increasing method or active load method is used in the upper differential pair, which compensates for the loss at high frequencies [5], [6]. , the combination of active In this paper, to further increase loads and inductive peaking method is proposed. Fig. 4 shows the schematic of the proposed dynamic frequency divider. Active loads with inductive peaking are incorporated into the upper differential pair. The loop gain versus frequency characteristics for frequency dividers using resistive loads, active loads, and active loads with inductive peaking are simulated by a HP ADS of a simulator as shown in Fig. 5. According to Fig. 5, the conventional dynamic frequency divider is 13 GHz, and that of the dynamic divider using only active loads is 16 GHz. Addition of inductors can give rise to considerable gain peaking, thus the further improved. The increasing gain peaking shown in Fig. 5 corresponds to when the value of the active loads with 0.5, 1.0, and 1.5 nH, respectively. inductive peaking are increases up to about 19 GHz. To implement the inThe ductive load, a spiral inductor is used for its large inductance for a given die area. The inductance value is carefully selected to increase bandwidth without self-resonance. We selected 0.5 nH with a self-resonance frequency above 40 GHz.
Fig. 5. Open-loop gain of the conventional divider, the divider using active loads and the divider using active loads with inductive peaking.
Fig. 6. Photograph of the VCO with the proposed frequency divider using active loads with inductive peaking.
IV. MEASUREMENT RESULTS The push-push VCO with a dynamic frequency divider has been fabricated in 6-in InGaP/GaAs HBT process of Knowledge*on foundry. The chip sizes of the push-push VCO and the dynamic frequency divider are 2.2 1.2 mm and 0.9 0.9 mm , respectively, as shown in Fig. 6. The two chips are connected with the stitched wire bonds. The output spectrum and phase noise performance at 60 GHz were measured using
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Fig. 9. Measurement results of the proposed dynamic frequency divider (a) input and output waveforms at 30 GHz input frequency and (b) input sensitivity versus input frequency.
TABLE I FREQUENCY DIVIDER COMPARISON Fig. 7. Measurement results of 60-GHz push-push output phase noise.
V. CONCLUSION Fig. 8. Measurement results of 15 GHz output (a) output spectrum and (b) phase noise.
HP E4407B with HP 1194V (50 75 GHz) harmonic mixer. The 3.4 dB losses of probe tip and waveguide components in V-band measurement setup are measured and compensated at 60 GHz. The output spectrum and phase noise of 15 GHz were obtained from HP 8565E spectrum analyzer. The total losses of the microprobe, the cable and the connectors are about 4.5 dB at 15 GHz. Fig. 7 shows the phase noise of the push-push output frequency of 60 GHz with a tuning range of 1.4 GHz. Output power of 14 dBm and phase noise of 77.5 dBc/Hz at 1 MHz offset frequency are measured at the push-push output. Fig. 8 illustrates the output spectrum and phase noise from the proposed dynamic frequency divider connected to the 60-GHz push-push VCO. A differential output power of 5.4 dBm and phase noise of 92 dBc/Hz at 1-MHz offset frequency are measured at the dynamic frequency divider of 15 GHz. The suppression of 30 GHz is about 34 dB [7]–[9]. Fig. 9(a) shows input and output waveforms of the proposed frequency divider at 30 GHz input frequency. Input sensitivity versus frequency is shown in Fig. 9(b). The operating frequency range of the proposed dynamic frequency divider is from 10 GHz to 36 GHz. This proposed dynamic frequency divider is implemented using an InGaP/GaAs HBT technology of 50 GHz and operates much higher than 2 with of transistor. In Table I, the proposed frequency divider is compared with previously published CMOS and SiGe implementations. Although it consumes large power, it operates up ratio of 0.72 and has larger locking range than the to injection-locked dividers.
We presented a 60-GHz push-push VCO with a dynamic frequency divider using a cost effective InGaP/GaAs HBT technology. To the best of our knowledge, the operating frequency of 60-GHz is the highest among the value reported for the VCO with a frequency divider using an InGaP/GaAs HBT technology. The dynamic frequency divider is firstly implemented with both active loads and peaking inductors. REFERENCES [1] S. Reynolds, B. Floyd, U. Pfeiffer, and T. Zwick, “60 GHz transceiver circuits in SiGe bipolar technology,” in IEEE Int. Solid-State Circuit Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, pp. 442–538. [2] O. Lee, J.-G. Kim, and S. Hong, “A V-band VCO and frequency divider MMICs for phase-locked loop,” in IEEE MTT-S Int. Dig., vol. 3, Jun. 2004, pp. 1321–1324. [3] G. Ritzberger, J. Böck, and A. L. Scholtz, “45 GHz highy integrated phased-locked loop frequency synthesizer in SiGe bipolar technolodgy,” in IEEE MTT-S. Int Dig., vol. 2, Jun. 2002, pp. 831–834. [4] J.-G. Kim, D.-H. Back, and S. Hong, “A 60 GHz InGaP/GaAs HBT push-push MMIC VCO,” in IEEE MTT-S Int. Dig., vol. 2, Jun. 2003, pp. 885–888. [5] H. Ichhino, N. Ishihara, M. susuki, and S. Konaka, “18-GHz 1/8 dynamic frequency divider using Si bipolar technology,” IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1723–1728, Dec. 1989. [6] M. Kurisu, G. Uemura, and T. Tashiro, “A Si bipolar 28-GHz dynamic frequency divier,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1799–1803, Dec. 1992. [7] A. Rylyakov and T. Zwick, “96-GHz static frequency divider in SiGe bipolar technology,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1799–1803, Oct. 2004. [8] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18 m CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1799–1803, Oct. 2004. [9] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
