A Class-E PA With Pulse-Width and Pulse-Position ... - IEEE Xplore

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A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS Jeffrey S. Walling, Member, IEEE, Hasnain Lakdawala, Member, IEEE, Yorgos Palaskas, Member, IEEE, Ashoke Ravi, Member, IEEE, Ofir Degani, Member, IEEE, Krishnamurthy Soumyanath, Member, IEEE, and David J. Allstot, Fellow, IEEE

Abstract—A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK 4-DQPSK (PAR 4 dB) modulated signals, respectively. and Index Terms—Class-E, linearization, outphasing, power-added efficiency, power amplifier, pulse-position modulation, pulse-width modulation.

I. INTRODUCTION

R

ECENT trends in wireless circuits portend the promise of completely integrated radio solutions in CMOS. Almost all elements of a transceiver are easily integrated onto a single chip with the exception of the power amplifier (PA), which is difficult to integrate due to the low breakdown voltages of deepsubmicron CMOS devices. The on-chip PA often interfaces to an off-chip filter or antenna, so it should usually drive a load. To deliver appreciable power, however, it must be loaded with an optimum resistance given by (1) In a 65 nm CMOS process, the maximum power supply voltage for the core circuitry is and the minimum MOSFET saturation voltage is . Thus, to produce an output power of 1 W, the PA should be terminated with . A matching network is usually used to transform Manuscript received November 09, 2008; revised January 11, 2009. Current version published May 28, 2009. This work was supported by the National Science Foundation under Contract CCR-0086032 and by the Semiconductor Research Corporation under Contract 2001-HJ-1427 and Contract 2003-TJ-1093. The work of Dr. Walling was supported by an Intel Foundation Predoctoral Fellowship. J. S. Walling and D. J. Allstot are with the Depatment of Electrical Engineering, University of Washington, Seattle, WA 98195 USA (e-mail: [email protected]). H. Lakdawala, Y. Palaskas, A. Ravi, O. Degani, and K. Soumyanath are with Intel Corporation, Hillsboro, OR 97124 USA. Digital Object Identifier 10.1109/JSSC.2009.2020205

Fig. 1. Illustration of (a) Amplitude (pulse-width) and (b) phase (pulse-position) information storage in a PWPM signal.

into , but it exhibits increased loss with an increased transformation ratio. A switching power amplifier can potentially exploit the everimproving switching characteristics of CMOS transistors to provide high output power and power efficiency using a simple matching network. In practice, however, it is not often implemented in CMOS for two reasons: First, a switching PA is highly non-linear with respect to input amplitude variations, which either requires linearization (supply modulation, outphasing, etc.) or limits its application to constant envelope modulation standards. It also often experiences relatively high output voltages that stress the on-chip CMOS power devices. Power amplifier linearization systems using supply modulation methods have shown impressive results [1]–[3]; but, the circuitry is somewhat complicated and unnecessary for modulation standards with moderate peak-to-average ratios (PAR). This paper describes an approach that uses pulse-width and pulseposition modulation (PWPM) to directly modulate the gate of a CMOS class-E power amplifier [4], [5]. PWPM modulation

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WALLING et al.: A CLASS-E PA WITH PULSE-WIDTH AND PULSE-POSITION MODULATION IN 65 nm CMOS

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Fig. 2. PWPM generator and representative waveforms in the analog domain.

works well for systems that use modulation standards with mod3-6 dB . In addition, switching PAs often exhibit erate PARs relatively large output voltage swings, which stress the CMOS power switching devices. Design techniques to reduce voltage stress on the output power devices of a class-E PA are also presented. The RF PWPM principle is reviewed in Section II, and tradeoffs between different switching PA topologies are given in Section III, which motivates the choice of a class-E PA for the PWPM system. Design considerations for the circuit blocks in the PWPM generator and class-E PA are given in Section IV, and a complete PWPM PA prototype and measurement results are presented in Section V.

Fig. 3. Illustration of information storage in an outphasing system. (a) When outphasing angle,  , is small a large envelope (S + S ) results, and (b) When  is large a small envelope results.

II. RF PULSE-WIDTH AND PULSE-POSITION MODULATION In an RF PWPM system, one pulse is transmitted during each period of the RF carrier signal [6]: (2) where and are the envelope and phase signals, respectively, and is the carrier frequency. A PWPM signal is generto the width of a single pulse and to ated by mapping the edge timing of the same pulse as depicted in Fig. 1(a) and (b), respectively. The pulse modulated waveform of Fig. 1 is desirable in power amplification applications because of its fixed amplitude; i.e., information is carried in its width and timing, which allows the PA to be driven into compression. With proper wave shaping networks, compressed amplifiers (e.g., class-D, -E, -F) ideally achieve power efficiencies of 100%, which is much higher than their uncompressed (linear) counterparts. Many methods are available to generate the PWPM signal. One technique that uses digital signal processing (DSP) in conjunction with a bandpass delta-sigma modulator (BPDSM) offers easy generation of the digital driving signal [7]; however, the quantization noise is shaped into out-of-band frequencies, which requires care to guarantee that the spectral emissions mask is not violated. Another approach uses an analog comparator in a feedback loop to linearize the signal [6]. In addition to stability issues, a predistorted version of the signal must be generated for use as a reference for the loop. An alternative for the generation of RF PWPM signals is illustrated in Fig. 2 wherein two outphased signals are generated

via DSP techniques including a coordinate rotation digital computer (CORDIC) algorithm. The outphased signals are used to phase modulate the RF carrier, and the resulting signals ( and ) are limited and compared (using logic gates) to genand ). erate the differential PWPM waveforms ( The vector diagrams of Fig. 3 show how amplitude information is contained in the two constituent phase modulated signals. The signal envelope, which is normalized and bound to function. The resulting the range 0 to 1, is applied to a output, known as the outphasing angle, , is bound to the range 0 to 90 degrees. Signals with large envelope amplitudes (i.e., ) produce , whereas small envelopes (i.e., 0) give 90 degrees. Note that the outphasing operation is linear, but the relationship between the amplitude of the envelope and the pulse-width is inherently nonlinear. A Fourier expansion of a PWPM signal reveals that the relationship between the fundamental envelope amplitude, , and the duty cycle, , is given by (3) Furthermore, as the duty cycle is varied, harmonic tones are also generated according to (4) wherein is the harmonic number. A plot of the peak ampli, second , and third hartudes of the fundamental is shown in Fig. 4. Because monics versus pulse duty cycle

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Fig. 4. Harmonic amplitude versus input duty cycle, 50%.

D. In this design, D 

of the obvious nonlinearity between and , predistortion is needed for this method of PWPM generation; to a first order, it is applied as an arc cosine function on the envelope of the original input signal. Note also from Fig. 4 that although significant higher harmonics are generated, filtering at the output of the PA usually suppresses them to insignificant levels. III. PA TOPOLOGY SELECTION A switched-mode PA that achieves an ideal power efficiency of 100% is selected for use with a PWPM signal. The three main types of switching power amplifier stages (Fig. 5) are (a) class-D, (b) class-F, and (c) class-E. The class-D amplifier [Fig. 5(a)] is the simplest configuration; it comprises a series resonant filter connected to the output and of a push-pull amplifier consisting of CMOS transistors . A drawback of this configuration is dynamic power dissipation, which is proportional to frequency due to the charging and discharging of the parasitic capacitances at the common drain node. Unlike the class-E or class-F amplifiers, the drain capacitance is not used as part of the termination network, so it must be charged and discharged with every cycle. This capacitance can be tuned with a high-Q resonant network, but this network narrows the range of frequencies over which the output stage operates. Furthermore, short-circuit transient currents consume significant power in the active devices if proper care is not taken [7]. A class-F amplifier [Fig. 5(b)] is formed using an output netthat work that creates an impedance seen from the drain of is high for odd harmonics but low for even harmonics. Consequently a square voltage waveform is created at the drain of , and a half-wave rectified current flows through only during the time when the drain voltage is low; i.e., the voltage and current waveforms are non-overlapping so that no power . The harmonic termination network of a is dissipated in class-F amplifier is typically implemented using transmission lines or lumped-element approximations, which consume large chip area and are lossy. In a practical integrated class-F PA, only the first few harmonic frequencies can be terminated, which degrades the peak power efficiency [8].

Fig. 5. Basic switch-mode power amplifiers. (a) Class-D, (b) Class-F, and (c) Class-E.

A class-E PA [Fig. 5(c)] uses zero voltage switching techniques, much like the other switching PAs, to shape the drain voltage and current waveforms so they do not overlap in time [9], [10]. The class-E topology has two key advantages over other topologies. First, its passive output network is nearly as simple and compact as that of the class-D network, and much smaller and simpler than that of the class-F circuit. Second, the power dissipation, and hence the power efficiency, of the class-E PA is not tightly coupled to the input switching frequency as with the class-D topology. One notable drawback of a class-E PA is the large voltage swing at the drain node of the switching device (Fig. 6), which [11]. Because of the possibility of can be as large as 3.6 overstressing the switching device, therefore, class-E PAs generally do not operate at the nominal maximum supply voltage for a given CMOS process. This tradeoff is problematic because a reduced supply voltage means that the PA must operate into a smaller impedance in order to deliver a specified interface, the matching network needs output power. For a

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Fig. 6. Drain voltage stress in a conventional class-E PA.

Fig. 8. (a) Output power versus duty cycle. (b) Efficiency versus output power backoff for a class-E PA.

Fig. 7. Drain voltage stresses in a cascode class-E PA with finite drain inductance, L .

a large impedance transformation ratio (e.g., 10–50), and such networks are lossy in integrated CMOS PAs [12]. The peak drain voltage occurs when the driver transistor is in the OFF state. Thus, there are no hot carrier effects, which occur when a high electric field exists in the gate oxide between the drain and gate terminals coincident with current flow through the channel. Because a high drain-to-gate voltage may cause catastrophic oxide breakdown; however, it should, as a rule of thumb in the design of a PA, not exceed twice the supply voltage [11]. Other prudent technology and design choices mitigate the effects of voltage stress. For example, many deep-submicron CMOS processes offer thick gate-oxide I/O devices that exhibit a higher breakdown voltage than their fully scaled counterparts. Furthermore, in a cascode connection of switching devices, the voltage stress is shared between the two devices. Another design option is the use of a finite supply inductance, whereby to about the peak drain voltage stress is reduced from [13]. A cascode class-E PA that uses a low breakdown transistor as the switching device, followed by a high breakdown device for the cascode, along with a finite supply inductance is

shown in Fig. 7[11]. With careful design, it operates at the maximum rated power supply voltage for 1.2 and 2.5 V low- and high-breakdown voltage transistors, respectively, without overstressing any devices. In the next section, the class-E PA and its associated PWPM generation circuitry are described. To justify the use of a class-E PA in a PWPM system, the effects of PWPM are examined to verify that variations in the pulse-width and duty cycle give predictable output amplitude , output variations. The sensitivities of the input power , and drain efficiency to variations in the input power duty cycle are given by [10] (5) (6) (7) where is the power supply voltage, is the DC–AC power transfer ratio, is the optimal termination resistance, and is the equivalent DC-resistance of the switching element. Paare dependent on the input duty cycle . rameters and 50% in Fig. 8(a), and (7) is Equation (6) is plotted for plotted versus normalized output power in Fig. 8(b). An ideal

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Fig. 10. PWPM generator clock receiver (RX).

Fig. 9. Top-level topology of the PWPM PA.

class-B PA efficiency characteristic is also plotted, which shows the efficiency advantages of the PWPM class-E PA. IV. CIRCUIT DETAILS A top-level schematic (Fig. 9) of the complete PWPM and (Fig. 2) are first PA shows that outphased signals processed by clock receive/retime circuits; the outputs drive combiner gates that generate four separate differential signal paths that are enabled or disabled via control bits for coarse power control. Each path includes a tapered inverter string that acts as a PA driver and a cascode class-E PA output stage that uses on-chip passives to form the class-E matching networks. All circuits are designed in a standard 65 nm low-leakage CMOS process with eight standard layers of metallization; no ultra-thick metal (UTM) layer is used. A. PWPM Generator The PWPM generator comprises three differential circuit blocks: clock receiver, buffer/retime chain, and PWPM combiner with tapered output buffers. The blocks are designed using digital standard cells for ease of layout and characterization.

The fully differential clock receiver circuit uses an input differential pair with a mode-locked active load (Fig. 10). The and ensures that the remode locking provided by ceiver is able to operate at speeds up to 4 GHz; the ratios and are 1/6 those of and to prevent oscilof interface lation. A simple resistive input match provides a that allows the PA to be tested as a stand-alone device. Note that the clock receiver circuit is not needed in a fully-integrated transmitter implementation wherein the PA is on chip along with the DSP outphasing and up-converter blocks. The differential clock receiver (Fig. 10) drives three stages of buffer/retime circuits; the first stage shown in Fig. 11 uses self-biased inverters at the front end to ensure high-speed operation whereas the following stages use conventional CMOS two) inverters. Each inverter consists of multiple (e.g., unit-cell inverters (inset) connected in parallel. Unit-cell design enables easy layout and verification using automatic placement and routing software. Retiming is performed using cross-coupled inverters connected between corresponding differential signals after every three stages to ensure propagation of properly phased differential signals. The PWPM combining function is accomplished using the differential NOR gate shown in Fig. 12. Its inputs are the differential clock signal outputs from the third buffering/retime stage (Fig. 11). The outputs of the differential NOR gate drive three tapered buffer stages implemented using parallel connections of the unit standard cell shown in the inset. A small taper factor of 1.5 is used in the unit cell so that swallowing of narrow pulses by the buffer chain is minimized. Example waveforms that depict operation of the circuit are shown in Fig. 12. Another feature of the PWPM combiner circuit is the enable function implemented , , , and , which provides coarse power conusing trol over a 4X range. The PA driver comprises a nine-stage tapered chain shown with a tapering factor of 1.5. It uses the same standard unit buffer cell (inset) as in the PWPM combiner circuit, which ensures that narrow pulses (e.g., longer than tens of picoseconds) are not swallowed by the drivers. This is accomplished at the expense of additional power consumption, which lowers the overall power

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Fig. 11. Schematic of the buffer/retime stage.

efficiency of the PA. Note that narrow pulses must be processed to provide a high dynamic range for the system. The driver chain design is designed to respond to a signal with a minimum 10% at 2.2 GHz. The measured pulse-width of 40 ps, or minimum pulse-width was 60 ps.

net susceptance rather than as separate inductances and capacitances. Because a finite inductor (capacitor) contributes a negative (positive) susceptance, the design equations become (12) (13)

B. Class-E Output Stage The class-E topology of Fig. 5(c) is well known [9]. It comprises a positive shunt susceptance at the output of connected to a series resonant circuit an NMOS switch designed for excess reactance at the desired operating frequency. The traditional design equations are [9], [10]

(8) (9) (10) (11) is created by matching the external load impedance (typi) using, for example, the -match network consisting cally of and in Fig. 5(c). The drain capacitance is formed by adding explicit capacitance to the parasitic at the drain of . The design equations above assume that is an RF choke, . which contributes no susceptance at the drain of It has been shown that the use of a finite inductance for reduces the voltage swing at the drain [13], [14]. In this case, it is best to view the circuit elements at the drain as a combined

is the optimum susceptance, and and are the where susceptances of the capacitor and inductor, respectively. A value is found using a circuit simulator to for the drain inductance monitor the drain voltage, in order to insure the proper shape, while sweeping the inductance and tuning the capacitance simultaneously to maintain the same net susceptance; an analytic approach is described in [14]. Using a finite inductance for the supply inductor has the added practical benefit that it can be realized as a slab inductance, which is formed in this case by connecting together the top two layers of metal to minimize loss due to the unavailability of a UTM. A slab layout is optimal because it requires no lossy “crossunder” using a lower metal layer, which also allows it to be made considerably wider than an equivalent spiral. The metal is made wide to handle the large average current. Note that the slab inductor is essentially a microstrip shorted stub, which can be designed and shaped to fit efficiently into the layout. It is important to note that because of parasitic and other loss 50% can mechanisms, operation of a class-E PA with a result in peak drain voltages larger than for 50% [15]. Hence, care should be taken to ensure that this voltage does not exceed the breakdown or life cycle voltage associated with the chosen CMOS process. Another consideration in the design of a class-E power amplifier is the series inductance, , between the NMOS switch and the ground terminal of the single-ended PA as shown in Fig. 13.

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Fig. 14. Fully differential class-E PA output amplifier comprising four selectable stages.

Fig. 12. PWPM combiner differential NOR gate and tapered output buffers.

Fig. 15. Class-E PA microphotograph in 65 nm CMOS.

differential pair, and the enabled signal paths are combined at the drains of the PA output devices. The segmented PA output stage is detailed in Fig. 14. V. EXPERIMENTAL RESULTS Fig. 13. Class-E PA with source degeneration inductor L .

It stores energy when is ON, but does not transfer that enswitches OFF [16]. As the energy is ergy to the load when proportional to the current and the inductance, it is desired to minimize this parasitic inductance. One way to minimize the source degeneration inductance in a differential implementation is to split the input stage into several small differential pairs with short local routing distances for each. Because of the spatial distribution of the differential pairs using this layout technique, the parasitic inductance is minimized and the devices can be spread apart more to prevent overheating due to concentrated power dissipation. Moreover, coarse power control is easily implemented as each of the four differential signal paths from the PWPM generator drive one small

Shown in Fig. 15 is a chip microphotograph of the prototype PA fabricated in a 65 nm low-leakage CMOS process with eight layers of metallization; including probe pads, the complete PA of Fig. 9 uses a die area of 1.6 mm 1.3 mm. With the output , and the rest of the stage of Fig. 14 operating from , the PA delivers 28.6 dBm into circuitry from , and it achieves its maximum PAE at 2.2 GHz. In addition to coarse control of the output power as described above, fine control is accomplished by varying the duty cycle of the input waveform. The output power, power added efficiency and drain efficiency of the PA with all four paths activated are plotted versus input duty cycle in Fig. 16. As expected, output power [Fig. 16(a)] increases as the duty cycle increases; a peak output power of 28.6 dBm and PAE of 28.5% are obtained for 50%

WALLING et al.: A CLASS-E PA WITH PULSE-WIDTH AND PULSE-POSITION MODULATION IN 65 nm CMOS

Fig. 16. Measured (a) output power and (b) PAE and DE versus input duty cycle.

duty cycle. Fig. 16(a) also shows that the PA has a dynamic 6 dB over the practical input duty cycle range of range of 20%–50%. This dynamic range characteristic constrains the PA to process signals of moderate PAR. The minimum input duty cycle constraint, and hence the dynamic range limitation, is determined by the narrowest pulse that the driver chain and PA can process without pulse swallowing. In this design, the narrowest pulse-width is 60 ps, limited by pulse swallowing in the PA driver chain and PA input; this corresponds to a duty cycle of 20% for signals near 2 GHz. In principle, a class-E PA may operate with 50%; however, the PWPM combiner used in this design does not allow such signals. Furthermore, the PA is tuned to operate with op50%. As a consequence, any variations timal efficiency for from 50% result in reduced efficiency [Fig. 16(b)]. Note that for a general class-E PA, the output power increases with increases in , but at the cost of increases in dc power consumption [15]. The simulated overall drain efficiency of an ideal class-B PA is compared with the measured efficiency of the PWPM class-E PA in Fig. 16(b), under the conditions of equal peak output power and drain efficiency. The PWPM PA is superior over the entire measured range of output power. This advantage leads to higher average efficiency for a transmitter employing PWPM. Of course, the dynamic range is limited compared to a linear PA;

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Fig. 17. Measured (a) output power and (b) PAE with coarse power control versus input duty cycle.

however, this technique performs well for signals with moderate dynamic range. The measured coarse power control is illustrated in Fig. 17. Using the digital enable/disable inputs to the PWPM combiner stage, the number of signal paths is programmed. With only one path enabled, the output power varies from 15.3 to 18 dBm, and with all four paths active, it varies from 21.6 to 28.6 dBm. Thus, an additional 6 dB of power control is achieved, which, when added to that of the PWPM circuitry enables processing of signals with larger PARs. The output power of the PA and its corresponding PAE are also changed via the power supply voltage of the output stage as shown in Fig. 18. In this design, the of the output matching network is relatively low ( 2–3), which enables good output power and PAE performance over a wide range of frequencies (Fig. 19). (The dip in performance around 1.9 GHz is caused by the characteristics of the external balun used in the measurements). Overall, the 3 dB bandwidth of the PA is about 1 GHz. Note also, as shown in Fig. 20, that the low factor of the matching network does not significantly impact harmonic performance as the second and third harmonics are 43 and 30 dB, respectively, below the fundamental output power. The class-E PWPM PA is applicable to standards with either constant envelopes or moderate PARs ( 3–6 dB). To validate

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Fig. 18. Measured output power and PAE versus output stage supply voltage.

Fig. 21. Measured performance with a GMSK (constant envelope) input signal and symbol rate 270 kHz.

=

4

Fig. 22. Measured performance with a = -DQPSK (non-constant envelope) input signal and symbol rate 192 kHz.

=

Fig. 19. Measured output power and PAE versus frequency (duty cycle 50%).

=

Fig. 20. Measured relative harmonic frequency power versus varying duty cycle).

P

(with

this salient point, the PA is tested with two different signals. wherein The first is a GMSK modulated signal with PWPM is used for fine output power control. The PA exhibits an at an output power error vector magnitude (EVM) of 1.2% level of 27.5 dBm as shown in Fig. 21. In the second test, a -DQPSK signal with a symbol rate of 192 kHz and a PAR of about 4 dB is applied to demonstrate the response of the PA

TABLE I COMPARISON TO PRIOR ART

to non-constant envelope modulation. The PA gives an EVM of at an output power of 26.7 dBm (Fig. 22). 4.6% A comparison to other CMOS RF PWPM PAs is made in Table I. The previous designs show higher efficiency, but the present PA operates at higher frequency and output power levels. Simulations suggest that a reduction in output power and operating frequency to similar values would yield similar efficiency results in the 65 nm design. VI. CONCLUSION A class-E PA that realizes envelope restoration by pulse-width and pulse-position modulation (PWPM) is presented in this paper. Using PWPM, signals with moderate PARs ( 3–6 dB) are amplified using non-linear switching power amplifiers. The design methodology for a circuit that

WALLING et al.: A CLASS-E PA WITH PULSE-WIDTH AND PULSE-POSITION MODULATION IN 65 nm CMOS

generates a PWPM signal from two input outphased signals is described. A class-E cascode PA design that also employs a finite DC feed inductance to reduce high-voltage device stress is also presented. A prototype circuit fabricated in 65 nm CMOS achieves a peak output power and PAE of 28.6 dBm and 28.5%, respectively. The design is validated using both a constant-envelope GMSK signal and a non-constant envelope -DQPSK signal, and achieves good EVM and average efficiency performance. ACKNOWLEDGMENT The authors would like to acknowledge Ralph Bishop and Stefano Pellerano for valuable measurement help. REFERENCES [1] A. Kavousian, D. K. Su, and B. A. Wooley, “A digitally modulated polar CMOS PA with 20 MHz signal BW,” in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 78–79. [2] F. Wang, D. F. Kimball, J. D. Popp, A. H. Yang, D. Y. Lie, P. M. Asbeck, and L. E. Larson, “An improved power-added efficiency 19-dBm hybrid envelope elimination and restoration power amplifier for 802.11 g WLAN applications,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4086–4099, Dec. 2006. [3] D. K. Su and W. J. McFarland, “An IC for linearizing RF power amplifiers using envelope elimination and restoration,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2252–2258, Dec. 1998. [4] J. S. Walling, H. Lakdawala, Y. Palaskas, A. Ravi, O. Degani, K. Soumyanath, and D. J. Allstot, “A 28.6 dBm 65 nm class-E PA with envelope restoration by pulse-width and pulse-position modulation,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 566–567. [5] F. H. Raab, “Radio frequency pulsewidth modulation,” IEEE Trans. Commun., vol. 21, pp. 958–966, Aug. 1973. [6] M. Nielsen and T. Larsen, “A 2-GHz GaAs HBT RF pulsewidth modulator,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 300–304, Feb. 2008. [7] T.-P. Hung, J. Rode, L. E. Larson, and P. M. Asbeck, “Design of H-bridge class-D power amplifiers for digital pulse modulation transmitters,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 12, pp. 2845–2855, Dec. 2007. [8] F. H. Raab, “Class-F power amplifiers with maximally flat waveforms,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 11, pp. 2007–2012, Nov. 1997. [9] N. O. Sokal and A. D. Sokal, “Class-E: A new class of high-efficiency tuned single-ended switching power amplifiers,” IEEE J. Solid-State Circuits, vol. 10, no. 5, pp. 168–176, May 1975. [10] F. H. Raab, “Idealized operation of the class E tuned power amplifier,” IEEE Trans. Circuits Syst., vol. 24, pp. 725–735, Dec. 1977. [11] A. Mazzanti, L. Larcher, R. Brama, and F. Svelto, “Analysis of reliability and power efficiency in cascode class-E PAs,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1222–1229, May 2006. [12] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002. [13] C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-m CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 823–830, May 2001. [14] R. E. Zulinski and J. W. Steadman, “Class E power amplifiers and frequency multipliers with finite DC-feed inductance,” IEEE Trans. Circuits Syst., vol. 34, pp. 1074–1087, Sep. 1987. [15] F. H. Raab, “Effects of circuit variations on the class E tuned power amplifier,” IEEE J. Solid-State Circuits, vol. 13, pp. 239–247, Feb. 1978.

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[16] F. H. Raab and N. O. Sokal, “Transistor power losses in the class E tuned power amplifier,” IEEE J. Solid-State Circuits, vol. 13, pp. 912–914, Dec. 1978. [17] P. Wagh, P. Midya, P. Rakers, J. Caldwell, and T. Schooler, “An all-digital universal RF transmitter,” in Proc. IEEE CICC, 2004, pp. 549–552. [18] P. Reynaert and M. S. J. Steyaert, “A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2598–2608, Dec. 2005. [19] J. T. Stauth and S. R. Sanders, “A 2.4 GHz, 20 dBm class-D PA with single-bit digital polar modulation in 90 nm CMOS,” in Proc. IEEE CICC, 2008, pp. 2431–2434. [20] S. Moloudi, K. Takinami, M. Youssef, M. Mikhemar, and A. Abidi, “An outphasing power amplifier for a software-defined radio transmitter,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 568–569. Jeffrey S. Walling (S’03–M’08) received the B.S. degree from the University of South Florida, Tampa, in 2000, and the M.S. and Ph.D. degrees from the University of Washington, Seattle, in 2005 and 2008, respectively. Prior to starting his graduate education, he was employed at Motorola, Plantation, FL, working in cellular handset development. He interned for Intel, Hillsboro, OR, from 2006 to 2007, where he worked on highly digital transmitter architectures and CMOS power amplifiers. He is currently with the University of Washington, where his research interests include low-power wireless circuits, energy scavenging, high-efficiency transmitter architectures and CMOS power amplifier design. Dr. Walling received the Analog Devices Outstanding Student Designer Award (2006), the Intel Foundation Ph.D. Fellowship (2007–2008), and the Andrew Yang Award for outstanding graduate research from the University of Washington, Department of Electrical Engineering (2008).

Hasnain Lakdawala (S’96–M’03) received the undergraduate degree from the Indian Institute of Technology, Bombay, India, in 1995, and the Master’s degree from the University of Hawaii, Manoa, in 1997, both in electrical engineering. He received the Doctorate degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, in 2002. From 2002 to 2004, he was a Product Architect at IC Mechanics Inc., Pittsburgh, responsible for the development of single-chip CMOS-based HDD shock sensors. He has been a Research Scientist at Intel Corporation, Hillsboro, OR, since 2004. His research interests include RF and analog circuits for WLAN transceivers that exploit scaled CMOS processes.

Yorgos Palaskas (S’98–M’02) was born in Kallithea Aitoloakarnanias, Greece, in 1973. He received the Diploma in electrical and computer engineering from the National Technical University of Athens, Greece, in 1996, and the M.S. and Ph.D. degrees, both in electrical engineering, from Columbia University, New York, in 1999 and 2002, respectively. Since January 2003, he has been with the Communications Technology Lab of Intel Corporation, Hillsboro, OR, where he is currently an Engineering Manager. His research focuses on wireless transceivers for WiMAX-WLAN and 60 GHz in nanometer CMOS technologies. Dr. Palaskas is currently serving on the Technical Program Committee for the IEEE International Solid-State Circuits Conference and the IEEE European Solid-State Circuits Conference.

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Ashoke Ravi (S’99–M’07) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, and the M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA. Since February 2001, he has been with Communications Technology Laboratory, Intel Corporation, Hillsboro, OR, working on circuits and architectures for CMOS wireless transceivers.

Ofir Degani (S’97–M’03) received the B.Sc. degree in electrical engineering and the B.A. degree in physics (both summa cum laude) in 1996, the M.Sc. degree and the Ph.D. degree in 1999 and 2005, respectively, all from the Technion–Israel Institute of Technology, Haifa, Israel. His Ph.D. research was focused on MEMS inertial sensors and modeling and simulations of MEMS electrostatic actuators. He is now with the Mobility Wireless Group, Intel, Israel. His recent research interest includes integrated transceivers, digital transmitters and mmWave radios in CMOS technology. He has published more than 40 journal and conference papers and filed several patents. Dr. Degani is the recipient of the prestigious 2002 Graduate Student Fellowship from the IEEE Electron Devices Society and was awarded the Charles Clore Scholarship by the Charles Clore Foundation.

Krishnamurthy Soumyanath (M’93) received the Ph.D. degree in computer science and engineering in 1993. He joined Intel in 1996, where he is a Fellow and is also the Director of the Communications Circuits Laboratory. While at Intel, he has led a variety of digital, mixed signal and RF CMOS projects. These include on chip sampling techniques for interconnect metrology, high speed data path circuits for several processor families, and CMOS transceivers for WLAN and multi-standard applications. He has

published over 50 papers in VLSI and related areas, and has over 30 patents issued and several pending.

David J. Allstot (S’72–M’72–SM’83–F’92) received the B.S., M.S., and Ph.D. degrees from the University of Portland, Oregon State University, and the University of California, Berkeley, respectively. He has held several industrial and academic positions and has been the Boeing-Egtvedt Chair Professor of Engineering at the University of Washington since 1999. He was Chair of the Department of Electrical Engineering from 2004 to 2007. Dr. Allstot has advised approximately 100 M.S. and Ph.D. graduates, published about 275 papers, and received several awards for outstanding teaching and graduate advising. Awards include the 1980 IEEE W.R.G. Baker Award, 1995 IEEE Circuits and Systems Society (CASS) Darlington Award, 1998 IEEE International Solid-State Circuits Conference (ISSCC) Beatrice Winner Award, 1999 IEEE CASS Golden Jubilee Medal, 2004 IEEE CASS Technical Achievement Award, 2005 Semiconductor Research Corporation Aristotle Award, and 2008 Semiconductor Industries Association University Research Award. His service includes: 1990–1993 Associate Editor and 1993–1995 Editor of IEEE TCAS II, 1990–1993 Member of Technical Program Committee of the IEEE Custom IC Conference, 1992–1995 Member, Board of Governors of IEEE CASS, 1994–2004 Member, Technical Program Committee, IEEE ISSCC, 1996–2000 Member, Executive Committee of IEEE ISSCC, 1996–2000 Short Course Chair of IEEE ISSCC, 2000–2001 Distinguished Lecturer, IEEE CASS, 2001 and 2008 Co-General Chair of IEEE ISCAS, 2006–2007 Distinguished Lecturer, IEEE Solid-State Circuits Society and 2009 President of IEEE CASS.