2010 19th IEEE Asian Test Symposium
A Complete Logic BIST Technology with No Storage Requirement Wei-Cheng Lien and Kuen-Jong Lee Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101 E-mail:
[email protected]
Abstract
generating control signals to select different positions for scan data inversion, it is shown that a single weight set is often enough to achieve full fault coverage. The single weight set does not need to be stored because it can be embedded into the LFSR logic. However, long test application time may be needed for a circuit containing many hard-to-detect faults. The mixed-mode BIST technique [1] takes advantages of both pseudo random and deterministic patterns to achieve the complete fault coverage in a short time. The main idea lies in first using an LFSR to generate a set of pseudo random patterns so as to drop the easy-to-detect faults and then applying deterministic patterns to detect the hard-to-detect faults. The deterministic patterns can be stored in external testers or on-chip ROM. For example, the so-called hybrid BIST technique [4] stores the deterministic patterns in external testers. Since the storage device in a tester is usually quite expensive, the volume of deterministic patterns should be minimized. Test data compression techniques [1] are thus often adopted to reduce the volume of test data. Storing deterministic patterns in on-chip ROM eliminates the need of tester memory and reduces the test equipment cost. However, the on-chip ROM may induce high area overhead and the ROM itself needs extra test techniques (such as memory BIST). To reduce the required ROM space, some reseeding techniques [5-6] have been proposed to compress the required test data into some small-size seeds, which can then be decompressed by an LFSR or similar logic during test application time. Another mixed-mode technique, namly mapping logic [7-9], uses additional logic to modify the outputs or internal states of the LFSR so as to translate some pseudo random patterns into deterministic ones. The bit-flipping technique [7] modifies the LFSR contents by inverting some LFSR output bits. In [8] a ring architecture is used to fix unwanted values at certain bits of pseudo random patterns by using some specific mask patterns. All mask patterns can be embedded to a mapping logic and thus no storage device is required. Rather than revising the outputs of the LFSR, the on-the-fly reseeding technique proposed in [9] inverts the logic values in some bits of the LFSR to modify its next state. These methods [7-9] may require large area overhead for the mapping logic if a large number of patterns need to be translated. Some techniques use the circuit responses to directly produce deterministic patterns. The circular BIST scheme [10-11] replaces each primary IO with a special BIST cell and connects them together with the internal scan chains to form a long circular self-test path. In this scheme both
Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.
1. Introduction The traditional test methods using external test equipment have become cost-ineffective for VLSI circuits due to long test application time, limited I/O channels and expensive memory storages. One way to alleviate this problem is known as built-in self-test (BIST) which embeds some specific test infra-structure into the circuit-under-test (CUT) and thus can reduce the requirement of external testers. Pseudo-random testing based on linear feedback shift registers (LFSRs) is commonly used as the basis of BIST due to its simplicity and effectiveness. However a complex circuit often contains some hard-to-detect faults that are random-pattern resistant and thus a pseudo random test scheme usually requires long time to reach satisfactory fault coverage. To shorten the test application time, several methods have been proposed. The weighted random test method [1] applies single or multiple sets of weights to adjust the 0/1 probability of each input port so as to enhance the detectability of hard-to-detect faults. This method requires to store all weights in an on-chip ROM and thus may require large area overhead. To reduce the storage data volume, in [2] an iterative process is used to minimize the total number of weights. In each iteration, the process generates a test set that maximizes the number of X-bits such that by filling these X-bits carefully, the number of weights for each test set can be minimized and thus leading to small area overhead. In [3] the weighted random testing is combined with a shift-inversion mechanism which can invert scan shift data at some selected positions of scan paths. By on-chip 1081-7735/10 $26.00 © 2010 IEEE DOI 10.1109/ATS.2010.31
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connecting some internal nets of the CUT to the LFSR so as to change the state of the LFSR. In this paper, we name the test methodology that generates the deterministic patterns by extracting the responses of internal nets as feedback testing (FT). During FT a set of feedback patterns to detect the hard-to-detect faults will be generated. In order to achieve complete fault coverage, we may need different sets of internal nets to provide all required test data. Each such set of internal nets will be called a configuration of the FT. As shown in the figure, the selection of configurations is through a multiplexer. When one configuration is employed, the internal nets associated with the configuration will feed their responses back to the LFSR to provide one new feedback pattern per cycle. In our scheme each configuration will provide a series of feedback patterns for the CUT. It should be pointed out that although more than one configuration may be required in order to achieve 100% fault coverage, our experimental results show that in general only a very small number of configurations is needed using our method.
pattern generation and signature analysis can be done by the self-test path, and thus only small area overhead is needed. However if some states required to detect some faults cannot be reached by the self-test path, the fault coverage will degrade. The work in [12] addresses this problem by using a jumping logic for state transition such that the desired patterns can be generated effectively. Recently, the CircularScan method [13] modifies each scan chain to a circular scan chain and circularly shifts the captured response for each circular chain independently to construct the next pattern. In [14] the authors propose to connect some internal nets of the CUT to its inputs so as to provide the required logic values of the next pattern directly. By exploring the relation between the responses of internal nets and a pre-computed test set, this method can generate a series of deterministic patterns that are compatible with the pre-computed patterns. However, since the test set is pre-defined, it is difficult to identify a set of connections that can generate all required patterns. To get high enough fault coverage, different sets of connections, each with a special initial pattern, are required. Therefore the area overhead can be high and it still needs some storage to store the initial test pattern for each set of connections. In this paper, a mixed-mode BIST scheme requiring no any internal or external storage device is presented. This scheme first applies pseudo random testing to drop easy-to-detect faults and then generates deterministic patterns by utilizing the responses of internal nets (include outputs). Unlike the work in [14] which selects patterns from a given test set and tries to identify a set of internal nets to provide the required logic values, we propose an efficient algorithm to regenerate effective test patterns based on the current circuit response. Thus, we do not require any test data to initialize the internal state of the test pattern generator. Furthermore, an X-filling process is embedded in our algorithm to utilize the X-bits in each decided pattern so as to speed up the fault detection process. In the experimental results, we show that our method can achieve full fault coverage within 1000 cycles for all ISCAS 85 benchmark circuits, which is significantly shorter than those of previous work that also requires no storage device [3][8][9]. The comparison with [14] also shows that we can use much lower area overhead and shorter test time to reach the same fault coverage. In the rest of this paper we first describe our BIST architecture in Section 2. The algorithm to generate all test patterns and associated hardware configurations are then detailed in Section 3. Experimental results are given in Section 4 where comparisons with previous work are also given. Finally, we conclude the paper in Section 5.
Figure 1: Proposed BIST architecture. The control unit shown in the left side of Figure 1 is employed to control the switching between pseudo random testing and feedback testing as well as to control the selection of different configurations. The control unit consists of a pattern counter and a combinational decoder. The pattern counter is used to indicate the current pattern index and the decoder will provide the desired switch signals according to the pattern index. In general the decoder is quite simple since the modes of the LFSR only switch once (from pseudo random test mode to feedback mode) and the number of configurations is quite small. Thus the area overhead of our BIST is mainly on the connection wires from the CUT to the MUX and the MUX itself, which highly depends on the total number of configurations that are required to achieve complete fault coverage. Next, we present an efficient algorithm which aims to minimize the total number of configurations without compromising the fault coverage.
2. BIST Architecture
3. Test Generation and Configuration Determination Algorithm
As shown in Figure 1, the proposed mixed-mode BIST architecture mainly consists of a test pattern generator (TPG) and an on-chip control unit. In the TPG, an LFSR is used to generate a set of pseudo random patterns to detect easy-to-detect faults. The other parts in the TPG are responsible for generating deterministic patterns by
Figure 2 shows an overview of our test generation and configuration determination algorithm. The pseudo random patterns are first generated. If any faults are not detected after this procedure, a new configuration and a set of test patterns that can be generated by the configuration are determined. The configuration will be
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utilized until all faults are detected or it cannot detect more faults for a specified number of test cycles. The algorithm will terminate for the former case and will start another configuration for the latter case.
the 3rd and 5th input ports so far in the current configuration can all be provided by connecting the 1st internal net to them. Since CM63 = CM65 = 0, the 3rd and 5th input ports can also be connected to the 6th internal net in this configuration, which means that no matter what values the 3rd and 5th input ports require for the next pattern, a valid connection always exists that can provide the required logic values. On the other hand, the entry CM32 = ‘-’ indicates that the 3rd internal net cannot be connected to the 2nd input port of the circuit under the current configuration. Algorithm Test Generation & Configuration Determination Input: polynomial P(X), fault list F, PRL and LZERO Output: a set of BIST patterns BPT and the information of each configuration
Figure 2: Overview of the proposed algorithm. Figure 3 shows the pseudo-code of our algorithm. The algorithm outputs the information of each configuration and the set of patterns BPT that will be generated by the determined BIST architecture during test application time. Two user-defined input parameters, PRL and LZERO, are respectively used to limit the maximum number of pseudo random patterns and the maximum number of consecutive feedback patterns that do not detect any new fault. When executing pseudo random testing, the initial state of the LFSR is set to the pattern that detects the largest number of faults (based on a pre-determined fully-specified test set). According to the initial pattern and the LFSR polynomial P(X), a pseudo random test set containing PRL patterns is generated (line 1). The last few patterns of the test set will be removed if they do not detect any new fault. We then put all the remaining patterns into BPT and drop those faults detected by the test set from the fault list F (line 2). If all faults are detected, the procedure finishes (line 3), otherwise we will enter the feedback testing procedure. Two variables, zeroc and config, are used to record the number of consecutive feedback patterns that detect no new fault and the total number of configurations, respectively (line 4). Each new configuration will start with a test pattern denoted as tprev which is the last pattern in BPT. A partially-specified test set PT is generated for all the remaining faults in F (line 5). This set will be used to help determine the feedback patterns in the following process. In our algorithm, we build a special data structure, called a configuration matrix (CM), to keep track of two kinds of important information: the current response of all internal nets under the current test pattern, and the validity of the connections between the input ports and the internal nets under the current configuration. We use the example shown in Figure 4 to explain the concept of an CM. Each entry CMij can be at one of the three states ‘0’, ‘1’ or ‘-’, where i is an index of the internal nets and j is an index of the input ports. If an entry CMij is ‘0’ (‘1’), it means that the current response of the i-th internal net is ‘0’ (‘1’), and it is still valid to connect the i-th internal net to the j-th input port. If CMij has the state ‘-’, then it is invalid to connect the i-th internal net to the j-th input port in this configuration. For instance, CM13 = CM15 = 1 in Figure 4 indicates that the 1st internal net will have a value of 1 under the current test pattern, and the test data required at
1. Determine an initial pattern to perform pseudo random test for PRL cycles, 2. Remove the last few pseudo random patterns that detect no faults and add all useful patterns into BPT. Drop all faults detected by pseudo random test from F 3. if F = then Exit 4. zeroc 0, config 1, tprev the last pattern in BPT 5. Generate a partially-specified test set PT for F 6. Form the initial response matrix CM based on tprev 7. while F do 8. tc Valid cube identified from CM 9. tselect Pattern Selected from PT based on tc 10. if tselect = NULL then 11. tnext tc 12. else 13. tnext intersection of tc and tselect 14. Remove tselect from PT 15. if any X-bit exists in tnext then 16. Perform X-filling to refine tnext 17. Add tnext to BPT 18. if any faults are detected by tnext then 19. Drop all detected faults from F, zeroc 0 20. else zeroc zeroc + 1 21. if tnext = tprev or zeroc = LZERO then 22. Record the information of the current configuration 23. Remove the last zeroc patterns from BPT 24. tprev the last pattern in BPT 25. zeroc 0, config config + 1 26. Generate a partially-specified test set PT for F 27. Form a new CM based on tprev 28. else 29. tprev tnext 30. Update CM based on tprev 31. endwhile
Figure 3: Test Generation and Configuration Determination Algorithm.
Figure 4: An example of a configuration matrix.
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patterns of BPT will be removed to avoid wasting time on useless patterns. When either of the above conditions occurs, we record the information of the current configuration and start to work on a new configuration (lines 21-27). The last pattern in BPT will be used as the first tprev of the new configuration. We also reset zeroc and increment config. We then regenerate a new PT for all the remaining faults in F and form a new CM based on tprev and then start another iteration. If both conditions are not satisfied, then more test patterns can be generated by the current configuration and thus we replace tprev with tnext, update the current CM (line 29-30), and then enter the next iteration. There are two steps for updating CM. First, all invalid connections are pruned off according to tnext. Second, all valid connections are updated based on the responses after applying tnext. Use Figure 4 again as an example. Assume that tnext is (00001) and the response will become (110010) after applying tnext. Figure 5 shows the results of the two steps to update CM. At the left side of the figure, the step 1 will invalidate the entry CM13, CM33, CM53 and CM65 by setting them to ‘-’ since input 3 and input 5 will require logic 0 and logic 1 respectively for the next pattern (00001). At the right side of the figure, the step 2 updates the entries CM21, CM22 and CM24 to 1 and the entry CM35 to 0 because the current response of the 2nd and 3rd internal nets becomes 1 and 0, respectively. The while loop (lines 7-31) will be executed until all faults are detected. Next we use an example to illustrate our algorithm.
Now back to the algorithm in Figure 3. Before entering the while loop (line 7), we form the initial configuration matrix by performing a logic simulation (LSIM) with the last pattern tprev in BPT and setting each entry CMij as the response of the i-th internal net (line 6). In our algorithm, the first configuration will use the last pseudo random pattern as its initial pattern, and each of the following configurations will use the response of the last pattern of its preceding configuration as its initial pattern. Thus, our method needs no storage space. Also note that when a new configuration starts, all entries in the same row of the CM will have the same valid value, i.e., the value of the internal net corresponding to the row. In each iteration of the while loop, one feedback pattern will be determined by the following procedure. From all valid connections of CM, we determine a candidate cube tc which represents all input patterns that can be generated by the current configuration. For example, in Figure 4, tc is (00X0X) because any of (00000), (00100), (00001) and (00101) can be generated as the feedback pattern in the next cycle. Based on tc, we then execute a pattern selection process to select a pattern tselect from the pre-generated partially-specified test set PT that is compatible to tc (line 9). The compatibility makes sure that each specified input bit of tselect has at least one valid connection in the current configuration. If more than one pattern are compatible to tc, we select the pattern that is likely to detect the most number of undetected faults. If a compatible pattern tselect can be found, then we intersect tselect and tc bit by bit to form the next feedback pattern tnext and then remove tselect from PT. Otherwise we simply set tnext to be tc (lines 10-14). If tnext contains any X-bits, a two-stage X-filling is utilized to specify X-bits (lines 15-16). In the first stage of X-filling, a commercial ATPG tool is employed to fill the X-bits aiming to detect as many undetected faults as possible. If any X-bit still exists in tnext after this stage, the second stage will fill all remained X-bits in a way that the most number of valid connections in CM are retained. In the example of Figure 4, if tnext is (0000X) after the first filling stage, the 5-th bit of tnext will be specified as 1 in the second stage since it retains three valid connections CM15, CM35 and CM55 and only invalidates the entry CM65. After X-filling, the next feedback pattern is fully specified and added to BPT (line 17). If the refined tnext does not detect any new fault, zeroc is increased by one, otherwise all faults detected by tnext will be dropped from F and zeroc is reset to 0 (lines 18-20). The pattern generation of the current configuration will terminate if either of the following conditions occurs. The first one is when the next pattern tnext is the same as tprev, which means that the current configuration will repeatedly generate the same pattern, a phenomenon due to the structure correlation of the circuit that leads the circuit responses to a steady state [11]. The second one is when a number of consecutively generated feedback patterns do not detect any new faults. This condition is checked by comparing the value of zeroc and the pre-defined limit LZERO. When the second condition occurs, the last zeroc
Figure 5: An example to update a configuration matrix. Example: Assume the CUT has five input ports, six internal nets {W1, W2, …, W6} and the TPG contains an external LFSR with a primitive polynomial P(X) = 1+X4+X5. We set PRL to 4 and LZERO to 2 in this example. Figure 6 show the procedure of our algorithm to deal with this circuit. The cycle number of each pattern indicates when the corresponding pattern is generated. Figure 6(a) first shows the generation of PRL pseudo random patterns to drop the easy-to-detect faults. Of the four patterns assume that the 4th one does not detect any fault and thus can be removed. We then generate a test set PT for the remaining faults and assume PT contains 4 patterns {PT1, PT2, PT3 and PT4}. A logic simulation on the last pseudo-random pattern (cycle3, 11100) is performed. Assume the response of the internal nets is (010100). The CM is initialized by this response as shown in the bottom right of Figure 6(a), which indicates that all connections are valid now. After initialization, the first iteration to decide the feedback pattern for cycle 4 is
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(c) Iterations 2 to 3
shown in Figure 6(b). The cube identification process will find tc as (XXXXX), and the pattern selection process will select PT1 (assuming PT1 detects the most number of undetected faults) and form tnext as (X101X). All X-bits in tnext will be filled by the two-stage X-filling. We then drop all detected faults and simulate the circuit with tnext = (11010). Assume the response of circuit is now (101010). After updating the CM as shown in the top of Figure 6(c), two more patterns (cycle 5 and cycle 6) are generated after the execution of the following two iterations. Assume that the patterns in cycles 5 and 6 are the same as indicated. Then the first termination condition of a configuration is satisfied and thus we will need to start a new configuration. After deleting the pattern of cycle 6, a new test set PT will be generated and the response of the pattern of cycle 5 will be used to form a new CM as shown in Figure 6(d). By using the new CM, Figure 6(d) also shows that two more patterns will be identified (cycles 6 and 7). Assuming that after cycle 7 all faults are detected, the test generation procedure will then finish at this cycle.
(d) Iterations 3 to 5 Figure 6: An example of Test Generation and Configuration Determination Algorithm.
4. Experimental Results In this section, we provide the experimental results of our BIST scheme on ISCAS 85 benchmark circuits and compare the results with those of related work. For all experiments, the input parameter LZERO is set to 50 which is large enough to avoid wasting long time in applying useless test patterns for these circuits. To enlarge the solution space, not only the responses of internal nets but also their inversions are recorded in the configuration matrix. A commercial ATPG tool is employed to complete the X-filling process. All of our programs are implemented in C++ and executed on an IBM PC server. Table 1 shows the experimental results when 100% fault coverage (FC) is targeted. The first four columns show the circuit name (CKT), the number of input ports (#IN), the number of testable faults (#TF), and the number of ATPG patterns without BIST. The fifth column (PRL) shows the number of random patterns to be generated. The column #CF shows the number of configurations required to achieve 100% fault coverage in our BIST. It can be seen that the largest number of configurations is 5 while most circuits require 3 or less configurations. The data under column #Cycles show the numbers of required cycles of our method and those of previous work that also requires no storage device. In the subcolumn Ours we provide the number of used pseudo random test patterns (PRT), the number of feedback test patterns (FT) and the total test length for each circuit using our BIST. The results show that our method can achieve 100% fault coverage within 1000 test cycles for all circuits. The other three subcolumns under #Cycles provide the
(a) Initialization
(b) Iteration 1
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first BIST work that can detect all irredundant faults in each of the ISCAS 85 circuits within 1000 cycles without requiring external or on-chip storage to store test data. One problem that deserves further investigation is that although the number of configurations is small, the connections from the internal nets to the circuit outputs still require large routing area. We are currently exploring the possibility to reduce and share these connections among the internal nets and the input ports of the circuit such that the area overhead can be minimized.
required test cycles reported in [9], [8] and [3]. Both [9] and [8] employ the mapping logic method and [3] presents a weighted random test with shift-inversion mechanism. From the table it is clear that our method requires much less test time than these methods for all circuits. Table 1: Experimental results and comparisons with previous work when fault coverage = 100%. CKT
#PI #TF #TP PRL #CF
c432 36 523 47 279 c499 41 750 54 300 c880 60 942 35 300 c1355 41 1566 86 600 c1908 33 1870 116 800 c2670 233 2630 59 300 c3540 50 3291 131 900 c5315 178 5293 69 500 c6288 32 7710 23 100 c7552 207 7419 105 500
0 1 1 1 3 5 3 1 0 5
#Cycles Ours [9] PRT FT Total 279 0 279 293 5 298 266 12 278 980 585 10 595 1046 785 115 900 3327 285 58 343 1002 900 19 919 479 28 507 40 0 40 496 241 737 3958
[8]
[3]
1K 2K 4K 5K 4.5K 8K
1024 1024 2048 4096 8192 6144 32768 4096 1024 32768
Acknowledgement: This work was supported in part by the National Science Council of Taiwan under contract number NSC 97-2221-E-006-248-MY3. References [1]
[2]
Table 2 compares our results with the recent work [14] which also generates patterns by feeding the responses of circuit back to its inputs. For fair comparisons, we target the same fault coverage as those reported in [14] which are shown in the second column of the table. It can be seen that our BIST can achieve the same fault coverage with much less numbers of configurations within comparable test application time. It is also worth to point out that different from [14] which still needs some storage device to store the initial pattern for each configuration, our method requires absolutely no storage device.
[3]
[4]
[5]
[6]
Table 2: Comparisons with [14] under the same fault coverage. CKT c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Total
Target FC % 99.81 100 100 97.84 98.50 99.20 99.60 99.91 100 99.00
Ours 0 1 1 0 1 3 1 1 0 2
#CF [14] 3 3 2 3 3 3 3 2 1 3
#Cycles Ours [14] 279 99 298 315 278 234 542 520 798 691 322 842 907 786 487 587 40 35 634 849 4585 4958
[7]
[8]
[9]
[10]
5. Conclusions [11]
This paper proposes a novel mixed-mode BIST that can reach complete stuck-at fault coverage in a short time without using any storage device. The proposed BIST applies pseudo random testing to detect the easy-to-detect faults first and then using a test method called feedback testing to detect hard-to-detect faults. An efficient algorithm to concurrently determine the test patterns and the feedback connections is provided which results in very short test time and very small area overhead as compared to previous work. To the best of our knowledge, this is the
[12]
[13]
[14]
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