A FPGA Floating Point Interpolator

A FPGA Floating Point Interpolator M.M. Balas1, M. Socaci2 and O. Olaru3 Abstract – The fuzzy-interpolative systems, a class of the Sugeno family fuzzy controllers, merge the linguistic representation of the knowledge with the effective interpolative implementations. Their application is immediate in any possible software environment, by look-up-table structures. However, their hardware implementation is not so easy. This paper is reporting a little step forward for the application of the fuzzy-interpolative systems in the field of the embedded systems: a specific FPGA block that is able to perform floating point interpolations, which can stand for a core of a future FPGA fuzzy-interpolative controller. Keywords – fuzzy-interpolative system, floating point interpolation, FPGA.

1 Introduction The interpolative side of the fuzzy and the neural controllers was initially mentioned by L. Zadeh [1]. In-depth studies on this matter showed that the fuzzy systems are universal approximators [2] and that they can be equalized or approximated at their turn by numerical mappings. The interpolation connection builds a bridge between the theoretical AI and Soft Computing concepts and the field control applications [3], [4]. Our approach in this matter is materialized by the fuzzyinterpolative methodology [5], which enables us to leave behind the comprehensive software that are commonly associated to AI and to develop fuzzy expert systems at the level of the simple programmable devices (C, DSP) or even with analog circuitry. The most attractive technology in the embedded systems domain is obviously the FPGA [6], [7]. Comparing FPGAs with the conventional digital computer architecture one observes that computers and the other similar binary architectures (P, C, DSP, etc.) are build around a central spine bone: the data/address/control bus, while FPGAs are distributed and purely parallel. That is why FPGAs are extremely fast, reliable, robust, portable, low energy consuming and cheap. If Soft Computing will be conveniently transferred into FPGAs we could expect a significant boost of the intelligent applications in all the aspects of our lives. --------------------------------------------------------------------------------------------------1 Associate Professor at “Aurel Vlaicu” University of Arad, Romania, e-mail: [email protected], tel. 0040.756.577992. 2 Master student at “Aurel Vlaicu” University of Arad, Romania, e-mail: [email protected]. 3 Professor at “Constantin Brancusi” University of Tîrgu Jiu, Romania, e-mail: [email protected].

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In a previous paper [8] our first step in this direction was done: a 8 bit interpolative controller on a FPGA Altera Cyclone II board, working with Quartus II Web Edition software. That controller was build for processing integer numbers, so the next step, presented in his paper, is the construction of an interpolation controller able to work with floating point represented numbers, in order to ensure a wide range of values and a satisfactory precision of the calculus [9].

2 A Floating Point Interpolator Our goal is to build a VHDL block for the piecewise linear interpolation (Fig. 1).

Fig. 1. The piecewise linear interpolation

The following interpolator is designed and realized using the support of the most accessible FPGA development board on the market: Digilent Spartan 3 equipped with the FPGA circuit Xilinx XC3S200-4FT256. The Xilinx iMPACT software (included into the Xilinx ISE Design Suite 14.1 package) [10], which is the programming tool, is connected with the system by means of the board’s JTAG port. A specific software tool that is assisting the floating point units design in ISE is the Xilinx Core Generator (see Fig. 2), which overlaps the IEEE-754 standard [9]. The Fig. 3 parallel interpolator is composed by six floating point units in single precision: three subtractions, one addition, one divider and one multiplier. Its performance is shown in Fig. 4. The speed of this purely parallel architecture is obviously very good: the latency is 1.22 μs, but on the other hand this circuit is consuming all the resources of the FPGA (193 bonded IOBs) and the overmapping limit is reached.

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Fig. 2. The Xilinx Core Generator for the design of the floating point units

Although if using more powerful FPGAs the problem could be enshrouded, a good interpolator should be optimized simultaneously in both senses: decreasing the number of the gates (minimizing if possible) and the latency. A possible solution to this optimization problem is to introduce pipelines techniques, but in this early stage of the research this approach would be rather costly and inadequate. We intend to fully apply the pipelining when reaching the final development stages of a complete fuzzy-interpolative controller.

Fig. 3. The VHDL parallel interpolator

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Fig. 4. The testing of the parallel VHDL interpolator

3 A Subtraction Sharing Floating Point Interpolator A simple and effective method to reduce the interpolator’s number of used gates is the resource sharing [12]. In this case we built a single floating point subtraction unit and share it for the three subtraction stages of the interpolation operation [11]. Furthermore, the subtraction unit was merged with the addition unit. A control input selects the actual operation. The interpolation is losing its implicit parallel operation, which is turned into a sequential one, controlled by the finite-state-automation presented in Fig. 5. Due to the more flexible structure different functional optimizations can be taken into consideration. For instance, the partial results can be memorized and reused, if we need several point of the same interpolated function. The latency of this interpolator for a new set of input data is 6.6 s. When computing a new point on a previously computed interpolated function, the latency can decrease to 0.78 s. The number of bonded IOBs is 69. The sequences of the interpolations are also presented in Fig. 5. The introducing of the input data can be repeated, as well as the reading of the corresponding results. The implementation of this version of the interpolator was written directly in VHDL.

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NOP, unassigned idle read_x0, read_x1

reset read_f0, read_f1

newx1

rst read_x

not ready ready newf div

ready

not ready ready AND NOT skip

not ready

ready AND skip

newx

ready ready add

not ready

mul ready

not ready

not ready

Fig. 5. The controller of the subtraction sharing floating point interpolator

4 Discussion The paper is presenting the implementation of a floating point piecewise linear interpolation FPGA block, written in VHDL, on a Digilent Spartan 3 board. Two architectures were realized and tested: 1) A parallel interpolator containing six floating point units: three subtractions, one addition, one divider and one multiplier, which has a latency of 1.22 μs. 2) A minimized interpolator containing three floating point units: one multiplier, one divider, and one addition/subtraction merged unit, which is shared by three different stages of the interpolation algorithm, with a latency of 6.6 μs. The final goal of this research is to implement fuzzy-interpolative applications into FPGA circuits, in other words to bring Soft Computing into the world of the field FPGA embedded systems.

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References 1. Zadeh, L.A.: Interpolative reasoning as a common basis for inference in fuzzy logic, neural network theory and the calculus of fuzzy If/Then rules. Opening Talk, Proceedings of 2nd International conference on fuzzy logic and neural networks, Iizuka, pp. XIII-XIV (1992). 2. Bauer, P., Klement, E.P., Moser, B., Leikermoser, A.: Modeling of Control Functions by Fuzzy Controllers. In: Theoretical Aspects of Fuzzy Control. Edited by H.T. Nguyen, M. Sugeno, R. Tong and R. Yager, John Wiley & Sons, pp. 91-116 (1995). 3. Dale, S., Dragomir, T.L.: Interpolative-Type Control Solutions. In: Studies in Computational Intelligence - Soft Computing Based Modeling in Intelligent Systems. Springer, Volume 196, pp. 169203 (2009). 4. Dale, S., Bara, A., Gabor, G.: Comparative study case for interpolative-type synthetic input controllers on a ball and beam system. Proceedings of the 10th WSEAS International Conference on Fuzzy Systems FS'09, Prague, pp. 76-83 (2009). 5. Balas, M.M.: The Fuzzy Interpolative Methodology. In: Studies in Computational Intelligence, Vol. Soft Computing Based Modeling in Intelligent Systems, eds. V.E. Balas, A. Varkonyi-Koczy, J. Fodor, Springer Verlag, pp. 145-167 (2009). 6. Rodriguez-Andina, J.J., Moure, M.J., Valdes, M.D.: Features, Design Tools, and Application Domains of FPGAs. IEEE Transactions on Industrial Electronics, Vol. 54, No. 4, August 2007, pp. 1810-1823 (2007). 7. Computer Engineering Research Group - University of Toronto: The FPGA Place-and-Route Challenge. http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html. 8. Balas, M.M., Sajgo, B.A., Belean, P.: On the FPGA Implementation of the Fuzzy-Interpolative Systems. The 5th International Symposium on Computational Intelligence and Intelligent Informatics ISCII’11. Floriana, Malta, September 15–17, 2011, pp. 139 – 142 (2011). 9. IEEE Computer Society: IEEE Std 754™-2008. IEEE Standard for Floating-Point Arithmetic. IEEE Inc., New York (2008). 10. Xilinx: ISE In-Depth Tutorial. 18 Ianuary 2012 (2012). 11. Socaci, M.: Aplicaţie VHDL pentru calcul în virgulă mobilă pe FPGA. Master disertation, University Aurel Vlaicu of Arad (2012). 12. Kilts, S.: Design, Architecture, Implementation and Optimization. Wiley-Interscience (2007).