2016 2nd IEEE International Conference on Computer and Communications
A High Precision Carrier Tracking Scheme Based on Phase Estimation and Compensation Ying Li, Ruisong Zhang, Wei Jiang
School of Electronics Engineering and Computer Science Peking University Beijing, China e-mail:
[email protected]
Abstract-When phase locked loop
(PLL)
works
in
this kind of schemes. Extended Kalman fIlter (EKF) [7]-[9] or unscented Kalman fIlter (UKF) [10] have been proposed to track the carrier in high dynamic environment and these Kalman fIlter-based schemes exhibit good tracking performance, except that their complexity is a bit high. In this paper, we focus on the problem of achieving high precISIon carrier tracking in dynamic environments. Although how to keep the carrier tracking loop from losing lock is important in such environment, yet we do not discuss it in this paper. We concern about how to reduce the tracking error when the carrier tracking loop is in lock. We propose a new scheme which implements a phase estimation and compensation module after the traditional PLL. This new scheme may maintain the tracking ability of the original PLL while at the same time eliminate the dynamic stress error and thus increase the carrier tracking accuracy. In Section II, we briefly introduce the results about phase tracking error of PLL. In Section III, we propose our new scheme and theoretically analyze the steady error and phase jitter of this new scheme. Simulation results are presented in Section IV to prove the effectiveness of our new scheme and then conclusions come in Section V.
high
dynamic environments, the dynamic stress error may be not
ignorable, which limits the accuracy of carrier tracking. In this paper, we propose a new carrier tracking scheme to reduce the dynamic
stress
error
of
the
PLL
by
concatenating
the
traditional PLL with a phase estimation and compensation
(PEC)
the
module. The PEC module can estimate and compensate
steady
state
phase
error
of
the
PLL's
output.
We
theoretically analyze the phase error performance of this new scheme, namely PLL-PEC. Simulation results show that PLL PEC reduces the dynamic stress error and increases the carrier tracking accuracy remarkably. Besides, PLL-PEC is very simple and easy to implement.
Keywords-carrier synchronization; phase locked loop; phase
estimation and compensation; dynamic stress error
I.
INTRODUCTION
Phase locked loop (PLL) is widely used in communi cation or satellite navigation receivers to track the signal's carrier phase. The phase tracking error consists of two parts: the random error and the steady state error. The random error is mainly caused by thermal noise and the steady state error, namely dynamic stress error, which is caused by imperfect tracking the dynamics of the transmitter or receiver. In high dynamic environment or when PLL using very narrow loop noise bandwidth to suppress the thermal noise, the dynamic stress error may grow very high and become the main factor which limits the carrier tracking accuracy. The error of carrier tracking loop in global position system (GPS) has been systematically discussed in [1]. The loop noise bandwidth is a key parameter concerning about the tracking error of PLL. But there is a dilemma when trying to decrease the phase error by just adjusting the loop noise bandwidth since when the loop noise bandwidth decreases, the thermal noise is suppressed while the dynamic stress error increases, or vice versa. [2], [3] proposed to add a fuzzy logic controller into PLL, which estimates the phase error and frequency error and then accordingly changes the loop order and noise bandwidth to reduce the total phase error of the PLL. An alternative way to reduce the total phase error of carrier tracking loop is taking use of some extra information about the velocity or acceleration. The receiver can use this information to remove the dynamics fIrst and then use narrow bandwidth to suppress the thermal noise [4] [6]. But the need of extra information restricts the usage of
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II.
DYNAMIC STRESS ERROR OF PLL
In dynamic environment, the phase error of a PLL tracking loop mainly consists of phase jitter (caused by thermal noise and oscillator noise) and dynamic stress error. The dynamic stress error grows rapidly as the noise bandwidth of PLL gets narrower for suppressing the thermal noise. Unlike the random phase jitter, the dynamic stress error is a steady state error, which means that it is almost unchanged for a period of time. According to [1], the dynamic stress error of an Lth order PLL is: (1) where dLe/dtL is the Lth order derivative of receiving signal's carrier phase e, Bm ron is the noise bandwidth and natural radian frequency of PLL, a = Bjroo is a constant which depends on the actual loop fIlter of PLL. For an Lth order PLL, if the Lth and higher order derivative of e is zero, then the dynamic stress error is zero and the PLL can track the carrier phase without bias. Otherwise, the PLL would track the carrier phase with a nonzero bias as ee. From (1) we
294
concatenate the traditional PLL with a phase estimation and compensation (PEC) module. We call this new scheme " PLL-PEC". Since the dynamic stress error is almost unchanged for a period of time, we can expect that this PEC module will estimate the dynamic stress error and eliminate it. Fig. 1 is the schematic diagram of PLL-PEC. Without loss of generality, assume the Lth order digital PLL is tracking a M-ary phase shift keying (M PSK) signal. Then the kth sample input to the PLL is:
can see that the dynamic stress error is inversely proportional to B; , which means that the nonzero bias of tracking phase may be significant for high order PLLs with narrow noise bandwidth. The phase error of a PLL caused by thermal noise is random and its variance is: cr
2 I,PLL
=
(2)
A� C INo
Ii (k) = s(k)eJ9(k) +n(k),
where c/No is the carrier to noise power ratio (unit is dB-Hz), and A is a coefficient related to the phase discriminator type and the predetection signal to noise ratio TCINo (T is the predetection integration time), For tracking BPSK signals using an arctangent PLL, A = 1 + No / 2TC, cr ; PLL is propor
where s(k) = e-J¢(k) is the M PSK symbol and �(k) {a, 2n/M, ... , 2(M - l)n/M }, n(k) is the independent and E
identically distributed (ij.d.) additive channel noise with zero mean and E(nn*) = NrlTC, e(k) is the carrier phase of receiving signal at time t = kT, T is the sampling period (and is also the predetection integration time). The kth sample of PLL's output is:
,
tional to the noise bandwidth Bn of PLL. When we consider both the dynamic stress error and the phase jitter caused by thermal noise, the variance of phase error of PLL is: (3)
cr
� is minimized
when choosing the noise bandwidth
Bn
(6)
rpo
(k)
=
lj
(k)e-A(k)
=
s
(k)eJ[e(k)-e(k)] + n(k), (7)
e(k) is the phase of NCO's output signal and n(k) = n(k)e-}J(k) is the equivalent channel noise with the same distribution as n(k). If the Lth order derivative of e is a where
of
PLL as:
nonzero constant, there will be a steady phase error in the PLL's output rpo(k). When the PLL is locked, the phase estimator is activated and it performs an estimation as:
()�
and the minimized
2 cr
is:
9,min
=
(
)
1 ABllopl 1 +---' ' 2L C / No
(8) (5)
Then the estimation of steady phase error is compensated by multiplying rpo(k) with e-A(k). So we get roCk) as:
Equation (5) suggests that with the existence of dynamic stress error, there is a lower bound for the total phase error when just optimizing the loop noise bandwidth. In order to track the carrier phase more precisely, we should find some other ways to reduce the dynamic stress error. III.
--- --- --- --- ----, PEe
-
-
-
-
(9)
j
THE PLL-PEC SCHEME
According to (1), using a higher order PLL is a simple way to reduce the dynamic stress error. For example, if the 4th and higher order derivative of e is zero, then a 4th order PLL can eliminate the dynamic stress error completely. But increasing the PLL's order is not always a good idea because high order PLL may be unstable and difficult to design. Another drawback of high order PLL is that although the steady phase error is zero for a Lth order PLL when tracking a signal whose carrier phase has all zero derivatives of Lth and higher order, yet when the carrier phase's (L - l)th order derivative changes suddenly, the PLL may encounter loss of lock. This phenomenon is demonstrated later in simulations.
- --- -----
.
'i
---
-
-
---
-
-
-
-
-------
- ---
(k)
I
j L
____________
Figure I.
A. BasicJdea a/PLL-PEC
���� � � ��
____________
j
j j
Schematic diagram of PLL-PEC.
B. Linearized Model a/PLL-PEC
Fig. 2 is the linearized model of PLL-PEC. Using the z transform, the PLL's closed-loop transfer function is:
We propose a new scheme to eliminate the dynamic stress error. The basic idea of this new scheme is to
295
II C
8(k ) = L ----E!.k. "' , k = 0,1, 2 ,... , m=O m!
(10) -I ' and the phase error transfer l-z -I function isHPLL e ( z ) = 1 HpLL c (Z ) The transfer function ,
d l118 dtl11 tive of 8 at t=° . Applying the Lemma 1 below, it is easy to see that the z-transform of 8(k) is:
Z
where C
where NCO ( z )=---
-
111
,
,
(17)
of the phase estimator in PEC module is:
=TI11 --1,-0 is the nonnalized mth order deriva-
m (18) 8(z) = CII (z_lr(Il+1) +t Dm(z-lr , m=O where Dn" m = 1,2, ..., n are some coefficients decided by Cm, m = 1,2, ..., n. Lemma 1: For nonnegative integer n, the z-transform of
l-z-N (11) . N(z-l) So the phase error transfer function of PLL-PEC is:
xn
kn (k )= , k=0,1, 2, -
n!
...
•
has the followmg form:
and the closed-loop transfer function of proposed scheme is:
He(z) =1-Ho(z) = HpLL,c(z)+HPLL,e(z)G( z) (13) �'-'-'-'-'-'-'-'-'-'-'-'I
!
PEe
+
where An., are constants. We put the proof of Lemma appendix. G(z) in (11) satisfies:
i
1 m
. 1-G(z ) . Nz-(N+1) +z -N N+1 (20) lIm =--. =hm 2 2 z->1 z->I (z -1) N(z -1) Substitute (19) and (20) into (14),
0, L (N+l)Td( +I8 ) . 0 (k )= IIm8 , k->oo 2())� dP+l)
8(k)
._._._._._._._
(15), then we get:
���i!�� � .
._._._._._._._._.
and
Figure 2. Linearized model of proposed scheme.
1
00,
n
L+l
nL
k-wc
Comparing (22) with (21), we find that PLL-PEC based on Lth order PLL (we call it Lth order PLL-PEC later in this paper) may totally eliminate the steady phase error caused by nonzero Lth order derivative of the signal's phase, which is the same as an (L + 1 )th order PLL.
of the original PLL is:
E� 8 (k) = �i2?( -1) HpLL,e ( )8( ) po
Z
z
z
.
(22)
(15)
The phase error transfer function of an Lth order DPLL can be described as:
D.
Phase Jitter Caused by Thermal Noise
PLL-PEC may add extra thermal noise because of the imperfect estimation of steady phase error. The phase error caused by thermal noise is calculated using (2) by replacing
the noise bandwidth Bn with Bn which is calculated by:
. I 2n . 2 2BIl = - f I He ( elm)1 d()), 2nT 0
Assuming the input signal's phase has nonzero constant derivative of not more than nth order, which means that
296
(23)
can see that the 2nd order PLL and 2nd order PLL-PEC still keep in lock, while the Doppler frequency rate jerk causes the 3rd order PLL to lose lock. This reminds us that although the 3rd order PLL is insensitive to constant Doppler frequency rate, yet it is sensitive to the Doppler frequency rate jerk. Then we change the input BPSK signal's carrier phase to satisfy:
Or we can use an approximation expression of the phase error caused by the thermal noise: '2 cr"PU-PEC ""
A
Bn
1/ (2NT) . C / No
+
(24)
From (24), we can see that to avoid too much thermal noise added by the PEC module, the parameter N should be chosen to satisfy NTBn > > 1. IV.
8(k) (80 =
SIMULATION RESULTS
Fig. 3 shows the instantaneous phase error of an 2nd order PLL, 3rd order PLL and 2nd order PLL-PEC respectively when tracking a BPSK modulated signal. The signal's carrier phase has a nonzero second order derivative as:
