LETTER
IEICE Electronics Express, Vol.14, No.1, 1–8
A high voltage multiplexer with rail to rail output swing for battery management system applications Xinchang Li1,2, Dawei Xu1,2a), Hongyue Zhu1,2, Zhuojun Chen1,2, Zhiqiang Yang1,2, Xinhong Cheng1,2, Yuehui Yu1,2, and Wai Tung Ng3 1
Graduate University of Chinese Academy of Sciences, Beijing 100049, P.R. China
2
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of
Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P.R. China 3
Edward S. Rogers Sr. Department of Electrical and Computer Engineering,
University of Toronto, Toronto, ON M5S 3G4 Canada a)
[email protected]
Abstract: This work presents a dual channel 8:1 high voltage (HV) multiplexer (MUX) with a 3-to-8 decoder and 16 HV switches for Battery Management Systems (BMS). Each HV switch consists of two pairs of sub-switches using n- and p-channel drain extended MOS devices with back to back body diode protection, respectively. The two pairs of sub-switches, connected in parallel and with dedicated gate drive signals, allow the HV MUX to have a rail-to-rail output swing and improved sampling accuracy. An experimental prototype is implemented using a 0.35 µm 60 V BCD process. The measurement results reveal that the maximum error of the HV MUX is ²0.2 mV, and the power dissipation is below 2.3 mW with a chip area of only 1.9 × 0.57 mm2. Keywords: multiplexer, switch, rail-to-rail output, high voltage, back to back protection Classification: Integrated circuits References
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
[1] D. Andrea: Battery Management Systems for Large Lithium-Lon Battery Packs (Artech House, Norwood MA, 2010) 51. [2] Analog Devices, Inc.: Analog Switches and Multiplexers Basics (2009) http:// www.analog.com. [3] Linear Technology, Inc.: LTC6803 Datasheet (2011) http://www.linear.com. [4] C. L. Chen, et al.: “A high voltage analog multiplexer with digital calibration for battery management systems,” IEEE ICICDT (2012) 1 (DOI: 10.1109/ ICICDT.2012.6232881). [5] C. L. Chen, et al.: “A voltage monitoring IC with HV multiplexer and HV Transceiver for battery management systems,” IEEE Trans. Very Large Scale Integration (VLSI) Syst. 23 (2015) 244 (DOI: 10.1109/TVLSI.2014.2303989).
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[6] C. L. Chen, et al.: “A battery interconnect module with high voltage transceiver using 0.25 µm 60 V BCD process for battery management systems,” ISOCC (2012) 1 (DOI: 10.1109/ISOCC.2012.6406910). [7] F. Yamashita, et al.: “A new compact, low on resistance and high off isolation high voltage analog switch IC without using high voltage power supplies for ultrasound imaging system,” ISPSD (2016) 415 (DOI: 10.1109/ISPSD.2016. 7520866). [8] P. Amrozik, et al.: “Alternative design approach for signal switchboxes in nanometer process,” CADSM (2009) 60. [9] S. Mouhoubi, et al.: “A family of robust DMOS devices for automotive applications,” ISPSD (2012) 97 (DOI: 10.1109/ISPSD.2012.6229032). [10] M. Jankowski: “High-voltage current-controlled analog switches for various kinds of application,” CADSM (2011) 42. [11] Analog Devices Inc.: The Data Conversion Handbook http://www.analog.com.
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Introduction
High voltage (HV) battery management systems (BMS) are required in many applications such as electric vehicles and hybrid electric vehicles, where a large number of battery cells are assembled together to form a battery pack. The BMS is required to measure, manage and analyze the status of each battery cell and communicate with the Electronic Control Unit (ECU) in the vehicle to assure safe and efficient operation of the battery pack [1]. As shown in Fig. 1, a HV multiplexer (HV MUX) acts as the front end of the BMS to connect the positive and negative nodes of individual lithium battery cells to the measurement circuit.
Fig. 1. A block diagram of a typical battery management system.
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
The analog MUXs used in the BMS often require high voltage handling capability, wide output swing, good crosstalk and isolation performance [2, 3]. MUXs implemented using low voltage transistors cannot meet these requirements. The availability of Bipolar-CMOS-DMOS (BCD) technology with high breakdown voltage has eliminated these limitations. In order to realize improved accuracy with reduced power dissipation, various topologies for HV MUX based on BCD technologies have been reported [4, 5, 6]. A multi-channel high voltage analog MUX with digital calibration for BMS using a 0.25 µm 1P3M (1-poly 3-metal) 60 V BCD process is presented in [4]. A voltage monitoring IC with HV MUX and HV transceiver for the battery interconnect module (BIM) in a battery management systems (BMSs) is proposed in [5]. In [4] and [5], the HV input signals are first
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stepped down to low voltage using a subtracting circuit and then sampled. Rail to rail output is also required for HV MUX. Reference [7] presents a new floating gate driving circuit and switch which can achieve rail to rail output for ultrasound imaging system. In this work, a novel HV MUX topology without subtracting circuit is proposed to achieve improved transmission accuracy and rail-to-rail output swing. HV switches in the MUX consist of paralleled sub-switches, which are formed by ndrain extended MOS transistor pairs and p-drain extended MOS transistor pairs. The HV MUX is fabricated with a 0.35 µm 1P3M (1 poly 3 metals) 60 V BCD process. The simulation and measurement results show that the proposed topology can provide rail to rail output swing from 0 V to HVDD, reducing the transmission error down to less than 0:2 mV, a power consumption of 2.3 mW and with a layout area of 1:9 0:57 mm2. This paper is organized as follows. In Section II, the basic architecture and specifications of the proposed HV MUX are introduced. In Section III, the drain extended MOS switches and their dedicated gate drive circuits are described and analyzed in detail. In Section IV, the implementation and the measurement results are discussed. Finally, a brief conclusion is given in Section V. 2
Architecture of the proposed HV MUX
The proposed dual channel 8:1 HV MUX is shown in Fig. 2, including a 3-to-8 decoder and 16 HV switches. Each set of HV switches are connected to one of the battery cells. The high channels in the 8:1 HV MUX are used to connect the positive terminals of the battery cells to HV sampling capacitor C1 of the ADC. The low channels are used to connect the negative terminals to C2. Bat.1, Bat.2, … represent one of the 8 lithium-ion battery cells connected in series.
Fig. 2.
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
Basic structure of the HV multiplexer connected to an ADC.
In a typical 60 V BCD process, high voltage capacitors C1 and C2 can be used as the fully differential input module of the ADC. The HV input signal charges the capacitors directly. The access to the differential voltage of Vout+ and Vout−, eliminates the requirement for a voltage subtraction circuit.
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Schematic of each HV switches
In low-voltage applications, a CMOS transmission gate can be used as the switch to pass the full range of voltages [8]. HV transistors are structurally asymmetrical, the source and drain terminals cannot be used interchangeably [9]. Consequently, a single HV pass transistor cannot act as transmission switch in the HV MUX [10]. Moreover, the gate control circuit in the HV switch becomes even complex. The proposed HV switch is composed of two sub-switches connected in parallel. There are two drain extended MOS devices connected back to back due to the presence of the built-in body diodes in each sub-switch as shown in Fig. 3. HVDD is the anode voltage of Bat.8. S[x] is the digital signal (0 or 5 Volt) provided by the 3-to-8 decoder to control the on-off action of the switches in the MUX. Diodes D1 thru D4 are floating polysilicon p+/n diodes. Due to the large series resistance in these polysilicon diodes, the actual reverse voltage is dependent on the reverse current after breakdown. In this case, VD1,reverse at 230 nA is approximately 4.1 V.
Fig. 3.
Schematic of each HV switches in the HV MUX.
3.1 HV n-MOS sub-switch The HV n-MOS sub-switch is consisted of back to back connected drain extended MOSFETs M1, M2 and their driving circuit (see Fig. 3). The threshold voltage of n-DMOS is about 1 V. When S[x] = 5 V, Mn1 and Mp1 turn on. D1 will breakdown and allow reverse conduction temporarily. M1 and M2 will turn on because: VGS,M1 ¼ VGS,M2 ¼ VD1,reverse þ VSG,Mp1 5:1V
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
ð1Þ
When S[x] = 0 V, Mn1 and Mp1 are off, and Mn2 is on. This pulls the gate voltage of M1, M2 down to GND. M1 and M2 will be turned off immediately. It should be noted that the output swing of this sub-switch can be as low as 0 V, but it cannot reach the supply level, HVDD (see Fig. 4) due to the following limitation: 0 Vout HVDD VGS,M1
ð2Þ
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3.2 HV p-MOS sub-switch The p-MOS sub-switch consists of back to back connected drain extended MOSFETs M3 and M4, together with their driving circuits: Gate Driver A, Gate Driver B and the Level shifter, as shown in Fig. 3. M3 and M4 should be controlled separately as their source terminals are not connected together. Gate Driver A is used for controlling M3 with the current sourced from the input batteries. When the current Ibias2 flows through R1, there will be a voltage drop (VR1 ) across R1. The value of R1 should be chosen to meet the turn-on requirement of M3. D2 is used for protection. VTH,M3 VR1 ¼ R1 Ibias2 5V
ð3Þ
M4 is controlled by Gate Driver B and the Level Shifter. Given that the Vout terminal cannot provide current supply, an independent current bias Ibias5 from HVDD is designed to achieve current-mode control of M4. The function of the Level Shifter is to shift Vout to a higher value: Vfb ¼ Vout þ VSG,MP2
ð4Þ
When S[x] = 0 V, Mn4 turns off, the current from Ibias4 flows through the D3 to Mp2 . M4 turns off because VB ¼ Vfb þ VD3,forward
ð5Þ
VGS,M4 ¼ VSG,Mp2 þ VD3,forward > 0
ð6Þ
When S[x] = 5 V, Mn4 turns on. No current will flows through D3 to Mp2 because the current sink Ibias3 is twice as large as the current source Ibias4 . On the contrary, VB will drop to very low value, forcing D3 to be in reverse breakdown. The reverse current ID3,reverse ¼ Ibias3 Ibias4 . This will cause M4 to turn on because: VB ¼ Vfb VD3,reverse
ð7Þ
VGS,M4 ¼ VSG,Mp2 VD3,reverse 4V
ð8Þ
The output swing of this sub-switch can be as high as HVDD, but not lower than VR1 . This voltage must be high enough to keep M3 to be fully on (see Fig. 4) because VR1 Vout HVDD
ð9Þ
In Gate Driver B, the value of Ibias3 is critical in order to prevent M4 from failing to turn on. D3 can be replaced by a resistor R2, whose value is the same as R1. Under this condition, Ibias3 acts as a large current sink to make sure the voltage drop on R2 is large enough to turn M4 on.
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
3.3 HV rail-to-rail output switch As mentioned above, both the HV n-MOS or p-MOS sub-switches cannot pass the full voltage swing from 0 to HVDD. However, when both pairs of drain extended MOS are utilized in parallel to form a new switch, rail-to-rail output can be achieved. Moreover, paralleling both sub-switches can also lower the on-resistance of the HV MUX than single sub-switch by a half, reducing the ADC input impedance.
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Implementation and measurement
Simulation results of the output swing with a 50 µA load, utilizing both an n-MOS sub-switch and a p-MOS sub-switch, is provided in Fig. 4. Neither the n-MOS nor the p-MOS sub-switch can achieve rail-to-rail output alone. Full voltage swing is available when they are in parallel. The difference in achieving rail-to-rail output between [7] and this work is the supply voltage of the controlling circuit. A large HVDD is necessary in this work as opposed to the low voltage in [7]. Neither design needs higher driving voltage than HVDD.
Fig. 4.
Simulation result of n-DMOS and p-DMOS sub-switch output swing.
The proposed design was implemented by a 0.35 µm 1-poly 3-metal 60 V BCD process to verify the performance. Fig. 5 shows the die photo of the fabricated HV MUX IC. The core area is 1:9 0:57 mm2.
Fig. 5.
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
Die photo of the proposed design.
The die is housed in a SOP-32A package and measured on a printed circuit board as shown in Fig. 6(a). The test-bench is constructed according to the topology shown in Fig. 2. In this configuration, the Logic Control signal comes from an ARM controller, C1 and C2 are replaced by two 1 pF multiplayer ceramic chip capacitors. Fig. 6(b) shows the measurement results for a battery pack with 8 lithium-ion cells in series. Each cell can be selected with input logic signal varying from 000 to 111. The differential voltage between the two channels (yellow and
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blue) is the voltage of each battery cell. Oscilloscope traces show that the HV MUX has rail to rail output from 0 V to HVDD.
(a)
Fig. 6.
(b)
(a) The HV MUX test-bench, (b) Test results with 8 lithium-ion battery cells in series. (CH1: 5 V/div, yellow; CH2: 5 V/div, blue)
The error distribution of the HV MUX is also examined under the configuration as shown in Fig. 6(a). There is some conduction loss (Vloss,i+ and Vloss,i ) in each set of HV switches. Vloss,i+ and Vloss,i are caused by the voltage drop on an electrostatic discharge (ESD) resistor, R (see Fig. 7) where a constant current Ibias2 flows into Gate Driver A. The battery voltage error (Verror,i ) is calculated according to equation (10) and listed in Fig. 8.
Fig. 7.
© IEICE 2017 DOI: 10.1587/elex.13.20161144 Received November 21, 2016 Accepted November 29, 2016 Publicized December 16, 2016 Copyedited January 10, 2017
Electro-Static Discharge circuit design for the input pads.
Fig. 8.
Error distribution of each battery voltage.
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Verror,i ¼ jVloss,i+ Vloss,i j
ð10Þ
Table I compares the performance of the proposed design with several prior works. Our design achieves the least power dissipation and smallest chip area. Moreover, a rail to rail output swing is achieved. A large on resistance (Ron ) in the MUX is acceptable as the RC constant is small enough for the most ADC in battery management systems [11]. For an N-bit un-buffered ADC with sampling capacitor C, the charging time t can be expressed as t ¼ Ron C N ln 2
ð11Þ
For example, a 16-bit ADC with a 1 pF sampling capacitor needs a charging time t ¼ 35:5 ns, which is small enough in most BMS applications. As a result, the proposed HV MUX topology without a subtraction circuit compared to [4] and [5] is more feasible in BMS. Moreover, the tolerance for large on resistance of drain extended MOS means small device size, reducing the chip area and power dissipation significantly. Table I.
Comparison between the proposed HV MUX and prior works This work
[4]
[5]
[7]
Process
0.35 µm 60 V BCD
0.35 µm 60 V BCD
0.35 µm 60 V BCD
SOI
I/O range
0 to 32 V Full range
2 to 29.2 V
4 to 32 V
−100 to 100 V Full range
3200 Ω
16.8 Ω
N/A
18 Ω
−60.2 dB@ 10 MHz
−79.4 dB@ 10 MHz
−92 dB@ 1 MHz
−54 dB@ 5 MHz
