A Highly Linear Integrated Temperature Sensor on a ... - IEEE Xplore

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014

A Highly Linear Integrated Temperature Sensor on a GaN Smart Power IC Platform Alex Man Ho Kwan, Member, IEEE, Yue Guan, Xiaosen Liu, Student Member, IEEE, and Kevin J. Chen, Fellow, IEEE Abstract— On a GaN smart power integrated circuit (IC) platform, a highly linear (i.e., proportional to absolute temperature) temperature sensor IC is demonstrated for building voltage references as well as temperature compensation functional blocks. The circuit is designed based on the temperature-dependent characteristics of GaN-based peripheral devices (e.g., heterojunction Schottky barrier diode, enhancement-/depletion-mode high electron mobility transistors, and lateral field-effect rectifiers) that are monolithically integrated with high-voltage power devices. This monolithic integration scheme facilitates the design efforts in taking full advantages of GaN’s superior capability to operate at high temperatures. Proper circuit operation was demonstrated at 275 °C. Index Terms— AlGaN/GaN high electron mobility transistor (HEMT), AlGaN/GaN SBD, GaN smart power platform, lateral field-effect rectifier (L-FER), monolithic integration, on-chip temperature sensing, proportional-to-absolute-temperature (PTAT) voltage source.

I. I NTRODUCTION

F

AST switching speed, low ON-resistance, and high breakdown voltage are the features of the wide-bandgap GaN-based lateral heterojunction power devices, such as transistors and rectifiers. These devices are becoming attractive candidates for the next generation high-efficiency power converters. Their inherent high-temperature operating capability also allows higher junction/ambient temperatures that can lead to simpler and low-cost cooling solutions. In a complete power converter, peripheral sensing/control/protection circuits [1]–[6] are necessary to provide robust control, increased functionality, and enhanced reliability to the core

Manuscript received January 1, 2014; accepted May 23, 2014. Date of publication June 12, 2014; date of current version July 21, 2014. This work was supported in part by Hong Kong under Grant ITS/122/09FP and in part by the General Research Fund, Hong Kong, under Grant 611311. The review of this paper was arranged by Editor A. M. Ionescu. A. M. H. Kwan was with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong. He is now with Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu 30010, Taiwan (e-mail: [email protected]). Y. Guan was with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong. She is now with PricewaterhouseCoopers Ltd., Hong Kong (e-mail: [email protected]). X. Liu was with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong. He is now with Texas A&M University, College Station, TX 77843 USA (e-mail: [email protected]). K. J. Chen is with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2327386

Fig. 1. Schematic platform for temperature-sensitive devices, such as E-/D-HEMTs, a heterojunction SBD, and an L-FER on the GaN smart power platform.

high-voltage GaN power components [7], [8], and to protect them against harmful operating conditions, such as overcurrent, over-voltage, and over-temperature. While peripheral controllers can be implemented with separate Si integrated circuits (ICs), it is highly desirable to develop a system-on-chip solution with a GaN smart power IC technology [9] that can better take advantage of the superior material properties of GaN, such as high-temperature operation. The GaN functional blocks and devices normally exhibit temperature dependences. Without proper compensation by bias adjustments using temperature sensing and control modules, the circuit performance would be compromised as the junction/ambient temperatures vary during circuit operation. One key performance parameter for temperature sensor circuit is its linearity. Although a simpler GaN temperature sensing circuit has been used in an over-temperature protection circuit [5], it is used for a nonlinear triggering operation and its linearity is relatively poor. In this paper, a highly linear proportional-to-absolutetemperature (PTAT) voltage source is demonstrated using monolithically integrated GaN-based heterojunction devices for the first time. This IC is designed based on the temperature-dependent characteristics of the low-voltagerating peripheral devices, including GaN heterojunction Schottky barrier diodes (SBDs), enhancement-/depletion-mode high electron mobility transistors (E-/D-HEMTs), and HEMTcompatible lateral field-effect rectifier (L-FER) on a baseline AlGaN/GaN-on-Si wafer, as shown in Fig. 1. The integration of E-/D-HEMTs allows simpler circuit configuration by eliminating the negative supply voltage. II. G A N D EVICES FOR T EMPERATURE S ENSING On the GaN smart power IC platform, several types of devices (e.g., E-/D-HEMTs, L-FERs, and SBDs) show

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KWAN et al.: HIGHLY LINEAR INTEGRATED TEMPERATURE SENSOR

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TABLE I T EMPERATURE C OEFFICIENTS OF D EVICES ON THE GaN S MART P OWER P LATFORM (E XTRACTED F ROM F IG . 2)

Fig. 2. Output (I D –VDS ) and transfer (I D –VGS ) characteristics of (a) E- and (b) D-mode AlGaN/GaN HEMTs, and I –V characteristics of (c) L-FER and (d) SBD measured at different temperatures on the same wafer available for monolithic integration to the proposed circuits. All the devices shown here have a width (e.g., gate width for HEMTs and anode width for L-FER and SBD) of 10 μm.

temperature-dependent characteristics in terms of bias currents and can be potentially used to build temperature sensors. Current–voltage (I –V ) characteristics of these devices are summarized in Fig. 2. At an ambient temperature of 25 °C, an E-HEMT [Fig. 2(a)] shows a threshold voltage VTH of 0.15 V at a drain current level of 0.1 mA/mm and a drain current I D of 307 mA/mm at a VGS of 3 V and a VDS of 10 V, while

a D-HEMT [Fig. 2(b)] exhibits a VTH of −2.15 V and an I D of 285 mA/mm. The L-FER shows a forward conduction current I D of 301 mA/mm at a forward voltage of 3 V at room temperature [Fig. 2(c)]. The SBD also exhibits 351 mA/mm at 2 V [Fig. 2(d)]. The devices shown in Fig. 2 exhibit various temperature dependences. Similar to devices in other technologies, such as CMOS [10], GaN-based E-/D-HEMTs [Fig. 2(a) and (b)] and SBDs show zero-temperature coefficient (ZTC) bias point at which the devices exhibit minimum temperature sensitivity. The E-/D-HEMTs’ ZTC bias points occur at very low current level, and these HEMTs are used in the bias range where the temperature coefficient is negative, as is the case for L-FERs, when the conduction current is mainly affected by phonon scattering in the 2-D electron gas (EG) channels [11]. The GaN heterojunction SBD shows a positive temperature coefficient in conduction current when the forward bias is below 1.45 V, which is the ZTC forward bias Vf (ZTC) . Below Vf (ZTC) , the forward current is dominated by thermionic emission over the Schottky barrier and increases with temperature [1]–[12]. When biased by a current mirror at a fixed current level, the forward voltage across the SBD exhibits a negative temperature coefficient from 25 °C to 300 °C [Fig. 2(d)]. Above the ZTC bias point, SBDs forward current decreases with temperature due to the negative TC of the series resistance R S . At a certain bias voltage, the temperature coefficient of the conduction current in various devices is extracted and summarized in Table I. The magnitude of temperature coefficient of E-HEMT and the L-FER is comparatively smaller than the D-HEMT. It is because during the fluorine implantation, a small amount of fluorine ions is introduced to the channel, which contributes to the impurity scattering that exhibits weak temperature dependence [13]. III. GaN PTAT VOLTAGE S OURCE A. Accurate Temperature Sensor: PTAT Voltage Source A PTAT voltage source is expected to generate an output voltage VOUT that increases linearly with temperature. It is used for high-precision applications, such as on-chip thermometers for high-power switches in a GaN power converter. The PTAT voltage source can also be used to compensate a voltage

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I2 ≈ A D2 Js exp q(V f,D2 − I2 R S,D2)/n s kT z

(2)

where A D1 and A D2 are the device areas of D1 and D2 respectively, Js is the normalized reverse saturation current density, and n s is the ideality factor of SBDs with n s ∼ 4 at 25 °C and n s ∼ 3.2 at 250 °C. Below a forward current level of ∼20 mA/mm shown in Fig. 2(d), the conduction current in SBD is mainly dominated by thermionic emission, while the effect of series resistance (Rs ) can be ignored because of the small current level. After rearranging the terms in (1) and (2), we can obtain I1 n s kT 1 ln · V f,D1 ≈ (3) q JS A D1 I2 n s kT 1 ln (4) · V f,D2 ≈ q JS A D2 where the reverse saturation current density JS has a nonlinear relationship with the absolute temperature T , described as Fig. 3.

Circuit schematic diagram of PTAT voltage source.

source with a negative temperature coefficient, to create a temperature-independent voltage source [14]. While Si-based PTAT voltage sources are usually designed by utilizing the temperature-dependent forward I –V characteristics of built-in p-n junctions, with this relation: I D ∼ eq V f /nkT, where I D is the forward current across the p-n junction, V f is the forward bias voltage, q ∼ 1.602 × 10−19 C is the electron charge, n is the ideality factor of the p-n junction, k is the Boltzmann constant 8.62 × 10−5 eV · K−1 , and T is the absolute temperature [14]–[17]. Such design approach, however, cannot be implemented in GaN due to the lack of high-performance p-n junctions in the GaN HEMT structures [18], [19]. Instead, GaN-based heterojunction SBDs exhibit similar temperature dependence in I –V characteristics. The fabrication of GaN heterojunction SBDs is compatible with the process of HEMTs. B. Temperature Sensing Stage The circuit schematic diagram of the proposed GaN PTAT voltage generator is shown in Fig. 3. This circuit is composed of two parts: 1) the temperature sensing stage and 2) the upper rail D-HEMT current mirror. In the temperature sensing stage, the E-HEMTs M5 and M6 are matched (with a gate length L g of 2 μm and a width Wg of 30 μm) and are placed next to each other in layout. When these two E-HEMTs are biased at the saturation region, their gate-source voltages VGS5 and VGS6 are mainly dependent on the drain current, and become less sensitive to VDS . To further minimize the effect of drain bias on the gate-source voltages of M5 and M6, their gate lengths (2 μm) are long. D1 and D2 are two SBDs with different area size. For D1 and D2, the forward voltages (V f,D1 and V f,D2 ) and the biasing currents (J1 and J2 ) can be approximately modeled by I1 ≈ A D1 Js exp q(V f,D1 − I1 R S,D1)/n s kT (1)

JS ∝ T 2 e −

q B kT

(5)

where B is the Schottky barrier height. As an accurate temperature sensor, the nonlinear terms JS should be eliminated in this temperature sensing stage. By assuming VS5 ≈ VS6 , the output voltage VOUT of the PTAT across the output resistor R can be derived as VOUT = VS5 − V f,D1(and VS6 = V f,D2) ≈ V f,D2 − V f,D1 ≈ (nkT /q) ln[(A D1 I2 )/(A D2 I1 )] ≈ (nkT /q) ln(A D1 /A D2)

(6)

where I1 is equal to I2 as the two currents are from the current mirror. When V f,D1 and V f,D2 are compared by subtraction in (6), the nonlinear terms ( JS ) are canceled out through a division in the log function. As a result, VOUT becomes linear to the absolute temperature T and is independent of R. VOUT can be designed by the area ratio of the SBDs. In the circuit shown in Fig. 3, D1 (with a device width W of 176 μm and a length of drift region L D of 2 μm) is 11 times larger than D2 (W = 16 μm and L D = 2 μm). R is used to determine the value of I1 and I2 , and is related to the area ratio of SBDs by I2 ≈ I1 = VOUT /R ≈ [(nkT /q)/R] ln(A D1/A D2 ).

(7)

The proposed temperature sensor is capable of providing chip-level temperature measurement and over-temperature protection to the core power devices. It is noted that this temperature sensor is aimed at sensing gradual chip-level temperature change due to the self-heating of the power devices or ambient heating, but may not be suitable for sensing the transient variation in the junction temperature of the power switches. C. Upper Rail D-HEMT Current Mirror Due to the lack of p-channel devices on the GaN smart power IC platform, the upper rail current mirror is designed using two cross-coupled D-mode transistors, which was first proposed in [20]. However, such a circuit is not a true


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current mirror, because the change in input current is opposite to that in the output current. In this paper, we propose to cascade two stages of cross-coupled D-HEMTs, as shown in Fig. 3. Stage 1 includes transistors M1 and M2, and M3 and M4 belong to Stage 2. The gate-source voltage VGS of the transistors in each stage is VGS1 = −VGS2 (Stage 1) VGS3 = −VGS4 (Stage 2).

(8)

Suppose that D-HEMTs M1–M4 in Fig. 3 are matched, their threshold voltages are all equal to −VTH . When they all operate at the saturation region, their gate-source voltages VGS and the bias current I1 , I2 , and I3 can be approximately modeled as

Fig. 4. (a) Scanning electron microphotograph of the fabricated PTAT voltage source circuit with a size of 500 × 414 μm2 . (b) Corresponding resistor R (with reference to Fig. 3) has extra metal connections that can be cut by laser to adjust its resistance.

I1 ≈ k(VGS1 − VTH )2 for M1 I3 ≈ k(VGS2 − VTH )2 ≈ k(VGS3 − VTH )2 for M2 and M3 I2 ≈ k(VGS4 − VTH )2 for M4

(9)

where k is a constant related to the device parameters of the transistor, on the condition that all four transistors are matched. By rewriting (9) (i.e., relating M1 and M2 with respect to I1 and I3 ) and using (8) (i.e., VGS1 = −VGS2 ), I1 and I3 are closely related as √ I1 + I3 = −(2 k · VTH ) > 0 (10) where VTH < 0 for D-HEMT. In other words, when I1 increases in Stage 1, I3 will decrease such that (10) holds. To realize a true current mirror, Stage 2 is cascaded to Stage 1, such that I2 increases, while I3 decreases. From (9), we have VGS2 ≈ VGS3 . Thus, (8) yields VGS1 ≈ VGS4 . Then, from (9), I2 can be related to I1 as I2 ≈ I1 .

(11)

Clearly, the static current bias of I2 follows I1 . Dimensions of M1–M4 should be small (L g = 2 μm and Wg = 10 μm), such that (9) approximately holds at small current bias. When temperature increases, electron mobility and k parameters in (9) are reduced [11]. Since M1–M4 are matched, their k parameters decrease at the same rate, and (10) and (11) are still valid at higher temperature. Thus, the upper rail D-HEMT current mirror can operate properly at various temperatures. To avoid I1 and I3 being affected by channel length modulation due to different VDS1 and VDS2 across the pair M1 and M2, two lateral field-effect rectifiers L-FER1 and L-FER2 in Fig. 3 are added to minimize the difference of V D1 and V D2. Similarly, four rectifiers L-FER5–L-FER8 are added to minimize the difference of VS1 and VS2 . In the same principle, L-FER3 and LFER4 are added to minimize the difference of V D5 and V D6. Such difference still exists, because forward voltage of L-FERs is also a function of the current level, as shown in Fig. 2(c). Thus, drain–source voltages of the transistor pair are not exactly matched. To further minimize the effect of channel length modulation in the transistor pairs, large gate length (2 μm) of all transistors is chosen. All L-FERs have the same size (L g = 1.5 μm and Wg = 40 μm).

Fig. 5. Temperature-dependent dc characteristics of an upper rail D-HEMT current mirror.

IV. FABRICATION AND C HARACTERIZATION A. Chip Fabrication The proposed modules were fabricated on a 4-in commercially available Al0.26 Ga0.74 N/GaN-on-Si(111) wafer. The epitaxial structure includes a 1.8-μm-thick GaN, a thin AlN interface enhancement layer, an 18-nm undoped AlGaN barrier, and a 2-nm GaN cap layer. E-HEMTs and L-FERs were fabricated using the fluorine implantation technique [21] on selective gate regions, where the D-mode channel is converted to E-mode. The microphotograph of the fabricated PTAT voltage source is shown in Fig. 4. B. Characterization of the PTAT Voltage Sensor 1) DC Characteristics of Current Mirror: To characterize the dc performance of the upper rail D-HEMT current mirror, a test circuit was implemented similar to that shown in Fig. 3, but the temperature sensing stage is removed. The source electrode of M1 was driven by a current source as I1 . Output current I2 was monitored at the cathode electrode of L-FER4, which is connected to a 1-k resistor. The measurement was performed from 25 °C to 250 °C, and the results are shown in Fig. 5. At 25 °C, when I1 is in the range of 170–360 μA, I2 proportionally follows I1 and this is consistent with (12). Nevertheless, when I1 exceeds this range, the output I2 starts to saturate. It is because M2 and M3 in Fig. 3 are driven to the linear region where I1 is too low, while M1 and M4 enter the

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Fig. 6. (a) VOUT of the PTAT voltage source shows a temperature dependence in the range between 25 °C and 275 °C. (b) VOUT extracted from (a) at a VDD of 12 V shows an approximately linear dependence with temperature.

Fig. 7. PSRR (VDD (ac) /VOUT (ac) ) of the PTAT voltage source (a) at different frequencies from 10 kHz to 1 MHz, measured at 25 °C, and (b) at various temperatures from 25 °C to 250 °C, measured at 1 MHz. The inset schematic circuit diagram illustrates the test setup. TABLE II

linear region when I1 is too high. When temperature increases, as described in Section II, the magnitude of the temperature coefficient of D-HEMT is larger than that of L-FER, and in turn, the sum of forward voltages in L-FER1 and L-FER2 in Fig. 3 is slightly larger than VDS3 of D-HEMT M3, and it is easier to drive M1 to its linear region at higher temperatures at lower I1 . Similarly, it is easier to drive M4 to the linear region at higher I1 , due to the mismatch between the forward voltages over L-FERs (L-FER3 and L-FER4) and source–drain voltage VDS2 of M2. As a result, I2 saturates earlier at higher temperatures. 2) DC Characteristics of the PTAT Voltage Source: To match the current level of the temperature sensing stage with the proportional range of the current mirror, resistor R in Fig. 3 can be adjusted by reconfiguring the 2-D EG resistor ladder using laser cutting, as shown in Fig. 4(b). At room temperature, VOUT was measured with the supply voltage VDD swept from 0 to 15 V. To understand the temperature-dependent characteristics of VOUT , the measurement was performed from 25 °C to 250 °C. As shown in Fig. 6(a), VOUT reaches a plateau and becomes independent of VDD when VDD is above 12 V and all transistors operate at the saturation region. The extracted VOUT at a VDD of 12 V shows an increase with temperature [Fig. 6(b)] at a rate of 0.35 mV/°C. Its linearity can be characterized by the goodness of fit 2 /(σ 2 σ 2 ), which is defined as the correlation of R 2 = σVT V T the sensor output to a straight linear line. The fitting straight 2 is the line is found by least mean square method. σVT covariance of the sensor output and the temperature, defined by 1/n − 1 nj =1 (V j − V )(T j − T ), where V j is the sensor output, T j is the corresponding measured temperature, and V and T are the sample mean of voltage and temperature, 2 respectively. variance of voltage defined as n σV is the sample 1/n − 1 j =1 (V j − V )2 , while σT2 is the sample variance of temperature defined as 1/n − 1 nj =1 (T j − T )2 . R 2 is close to one when the sensor output has linear relationship with the temperature. The GaN PTAT sensor shows an excellent linearity, with an R 2 of 0.993. Nevertheless, the offset of VOUT ∼ 0.14 V at 0 K is possibly due to the mismatch of the node voltages VS5 and VS6.

PTAT V OLTAGE S OURCES IN VARIOUS T ECHNOLOGIES

3) Power Supply Rejection Ratio of the PTAT Voltage Source: VOUT of the sensor should not be affected by ripples appearing at VDD due to the switching noise of power devices, such that unfavorable false control signals from the comparator would not be generated. To characterize the robustness of this circuit in terms of noise immunity, power supply rejection ratio (PSRR) is adopted. PSRR is defined as the ratio of ripples at VDD over the ripples appearing at the output. The test setup is shown in the inset of Fig. 7(a). A sinusoidal ac signal with a 1 V peak-to-peak amplitude VDD (ac) is applied to VDD in


addition to the 12 V dc bias. The variation of VOUT [labeled as VOUT (ac) ] was then monitored using the high impedance probe. PSRR [VDD (ac) /VOUT (ac) ] was obtained from 10 kHz to 1 MHz [Fig. 7(a)] and from 25 °C to 250 °C [Fig. 7(b)], and was well above 50 dB. The high PSRR is a result of the effective rejection of voltage ripples in the transistors M1–M4 working in the saturation region. 4) PTAT Voltage Sources in Various Technologies: The result of this paper is listed together with other technologies in Table II. GaN PTAT voltage source can operate at much higher temperatures. Moreover, it has high linearity, PSRR, and sensitivity. On the other hand, the power supply VDD of the GaN PTAT is comparatively higher because each current branch is stacked with E-/D-HEMTs that need minimum drain–source voltages (VDS min ∼ 2 V) to operate in the saturation region. VDS min can be reduced by decreasing the ON -resistance of the transistors through decreasing the gatesource and the gate-drain distances (L gs and L gd ).

V. C ONCLUSION On a GaN smart power IC platform, monolithically integrated temperature sensing modules have been realized, using the temperature-dependent characteristics of SBDs, L-FERs, and E-/D-HEMTs. The proposed PTAT voltage source features small size and is capable of monitoring the on-chip temperature, with a highly desirable linear output at the rate of 0.35 mV/°C. R EFERENCES [1] K.-Y. Wong, W. Chen, and K. J. Chen, “Integrated voltage reference generator for GaN smart power chip technology,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 952–955, Apr. 2010. [2] X. Liu and K. J. Chen, “GaN single-polarity power supply bootstrapped comparator for high temperature-electronics,” IEEE Electron Device Lett., vol. 32, no. 1, pp. 27–29, Jan. 2011. [3] A. M. H. Kwan, K. Y. Wong, X. Liu, and K. J. Chen, “High-gain and high-bandwidth AlGaN/GaN high electron mobility transistor comparator with high-temperature operation,” Jpn. J. Appl. Phys., vol. 50, no. 04, pp. 04DF02-1–04DF02-4, Apr. 2011. [4] A. M. H. Kwan and K. J. Chen, “A gate overdrive protection technique for improved reliability in AlGaN/GaN enhancement-mode HEMTs,” IEEE Electron Device Lett., vol. 34, no. 1, pp. 30–32, Jan. 2013. [5] A. M. H. Kwan, Y. Guan, X. Liu, and K. J. Chen, “Integrated over-temperature protection circuit for GaN smart power ICs,” Jpn. J. Appl. Phys., vol. 52, no. 8S, p. 08JN15, May. 2013. [6] K. J. Chen and A. M. H. Kwan, “Device technology for GaN mixed-signal integrated circuits,” Jpn. J. Appl. Phys., vol. 52, no. 11S, p. 11NH05, Nov. 2013. [7] W. Chen, K.-Y. Wong, W. Huang, and K. J. Chen, “High-performance AlGaN/GaN lateral field-effect rectifiers compatible with high electron mobility transistors,” Appl. Phys. Lett., vol. 92, no. 25, p. 253501, 2008. [8] W. Chen, K.-Y. Wong, and K. J. Chen, “Single-chip boost converter using monolithically integrated AlGaN/GaN lateral field-effect rectifier and normally off HEMT,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 430–432, May 2009. [9] K.-Y. Wong, W. Chen, X. Liu, C. Zhou, and K. J. Chen, “GaN smart power IC technology,” Phys. Status Solidi B, vol. 247, no. 7, pp. 1732–1734, Jul. 2010. [10] F. S. Shoucair, “Design consideration in high temperature analog CMOS integrated circuits,” IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 9, no. 3, pp. 242–251, Sep. 1986.

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[11] W. S. Tan, M. J. Uren, P. W. Fry, P. A. Houston, R. S. Balmer, and T. Martin, “High temperature performance of AlGaN/GaN HEMTs on Si substrates,” Solid-State Electron., vol. 50, no. 3, pp. 511–513, Mar. 2006. [12] S. Demirezen and S. Altindal, “Possible current-transport mechanisms in the (Ni/Au)/Al0.22 Ga0.78 N/AlN/GaN Schottky barrier diodes at the wide temperature range,” Current. Appl. Phys., vol. 10, no. 4, pp. 1188–1195, Jul. 2010. [13] B. K. Li, W. K. Ge, J. N. Wang, and K. J. Chen, “Persistent photoconductivity and carrier transport in AlGaN/GaN heterostructures treated by fluorine plasma,” Appl. Phys. Lett., vol. 92, no. 8, pp. 082105-1–082105-3, 2008. [14] G. C. M. Meijer, G. Wang, and F. Fruett, “Temperature sensors and voltage references implemented in CMOS technology,” IEEE Sensors J., vol. 1, no. 3, pp. 225–234, Oct. 2001. [15] A. Bakker, “CMOS smart temperature sensors—An overview,” in Proc. IEEE Sensors, vol. 2. Nov. 2002, pp. 1423–1427. [16] R. A. Bianchi, F. V. D. Santos, J. M. Karam, B. Courtois, F. Pressecq, and S. Siffiet, “CMOS-compatible smart temperature sensors,” Microelectron. J., vol. 29, no. 9, pp. 627–636, Sep. 1998. [17] M. A. P. Pertijs, K. A. A. Makinwa, and J. H. Huijsing, “A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1 °C from–55 °C to 125 °C,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2805–2815, Dec. 2005. [18] J. K. Sheu and G. C. Chi, “The doping process and dopant characteristics of GaN,” J. Phys., Condens. Matter, vol. 14, no. 22, pp. R657–R702, May 2002. [19] J. K. Sheu et al., “n + -GaN formed by Si implantation into p-GaN,” J. Appl. Phys., vol. 91, no. 4, pp. 1845–1848, Feb. 2002. [20] C. Toumazou and D. G. Haigh, “Design and application of GaAs MESFET current mirror circuits,” IEE Proc.-G., vol. 137, no. 2, pp.1/1–1/5, Apr. 1990. [21] Y. Cai, Z. Cheng, W. C. W. Tang, K. M. Lau, and K. J. Chen, “Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT inverters and ring oscillators using CF4 plasma treatment,” IEEE Trans. Electron. Devices, vol. 53, no. 9, pp. 2223–2230, Sep. 2006. [22] F. Serra-Graells and J. L. Huertas, “Sub-1-V CMOS proportional-to-absolute temperature references,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 84–88, Jan. 2003. [23] A. Syal, V. Lee, A. Ivanov, and J. Altet, “CMOS differential and absolute thermal sensors,” J. Electron. Test., vol 18, no. 3, pp. 295–304, Jun. 2002. [24] J. T.-S. Tsai and H. Chiueh, “High linear voltage references for on-chip CMOS temperature sensor,” in Proc. 13th IEEE ICECS, Dec. 2006, pp. 216–219. [25] S. Amon, M. Mozek, D. Vrtacnik, D. Resnik, U. Aljancic, and M. Cavr, “Compact BJT/JFET PTAT,” in Proc. Adv. EMAP, Nov. 2001, pp. 96–102. [26] J. B. Casady, W. C. Dillard, R. W. Johnson, and U. Rao, “A hybrid 6H-SiC temperature sensor operational from 25 °C to 500 °C,” IEEE Compon., Packag., Manuf. Technol., vol. 19, no. 3, pp. 416–422, Sep. 1996. [27] A. H. Zahmani, A. Nishijima, Y. Morimoto, H. Weng, J.-F. Li, and A. Sandhu, “Temperature dependence of the resistance of AlGaN/GaN heterostructures and their applications as temperature sensors,” Jpn. J. Appl. Phys., vol. 49, no. 4S, p. 04DF14, Apr. 2010.

Alex Man Ho Kwan (S’03–M’05) received the B.Eng. (Hons.) degree in electronic and communication engineering from the University of Hong Kong, Hong Kong, in 2003, and the M.Phil. and Ph.D. degrees from the Hong Kong University of Science and Technology, Hong Kong, in 2005 and 2013, respectively. He is currently a Principle Engineer with Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan.

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Yue Guan received the B.Sc. degree in microelectronics from Xidian University, Xi’an, China, in 2009, and the M.Phil. degree from the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, in 2011. She is currently with PricewaterhouseCoopers, Ltd., Hong Kong.

Xiaosen Liu (S’08) received the M.Phil. degree in electronic and computer engineering from the Hong Kong University of Science and Technology, Hong Kong, in 2011. He is currently pursuing the Ph.D. degree in electronic engineering from the Texas A&M University, College Station, TX, USA. His current research interests include analog and mixed-signal circuits.

Kevin J. Chen (M’96–SM’06–F’14) received the B.S. degree from Peking University, Beijing, China, and the Ph.D. degree from the University of Maryland, College Park, MD, USA. He is currently a Professor with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong.