veloped at Detroit Edison for this project. These macros develop data areas and Callstatements to the Notre Dame interface. Short Circuit Calculation Methods.
. Taps along a line. The origin of the Taps feature is from a small interactive program of the same name. By using Taps, a multi-tapped tie line like the
[3] T. E. Dy Liacco, K. A. Ramarao, "Short-Circuit Calculations for Multiline Switching and End Faults," IEEE PAS July/August 1970.
following
k>
-CM A
A A
A could be represented in the batch short circuit program as a single branch thus saving three or more buses. This allowed more sig¬ nificant buses to be included in one batch short circuit run. The old Taps program was used to reconstruct the tie line and display the fault currents along the tie line. It was decided to incorporate this feature in ISC.
ISC System Description
Hardware and software ISC is designed to run on an IBM System/370 (or equivalent) with
the Time Sharing Option (TSO). The designed-for terminal is an IBM 3270 Information Display System (or equivalent). A characteristic of these terminals is a display size of 24 lines.80 characters per line. These CRT terminals are monochromatic and nongraphic. All application programs are written in PL/I. The interface between the application programs and TSO is an assembler language program developed by the University of Nortre Dame in Indiana entitled "3270 Full Screen Support for COBOL using TSO." Although designed for COBOL, this interface program can also be used by PL/I. To facilitate programming, a group of PL/I macros were de¬ veloped at Detroit Edison for this project. These macros develop data areas and Call statements to the Notre Dame interface. Short Circuit Calculation Methods The bus impedance matrix (Z-bus) for both the positive sequence network and the zero sequence network are part of a Study. These matrices are modified to reflect changes to the Study. For adding lines and buses, the methods of Brown, Kirchmayer, Stagg, and Person are used [1]. To open lines with mutuals, the method described by Tarsi [2] and Dy Liacco and Ramarao [3] is used.
February 1982, p. 426
A Microprocessor Based Three-Phase
Transformer Differential Relay
J. S. Thorp, Senior Member IEEE Cornell University, Ithaca, NY A. G. Phadke, Fellow IEEE American Electric Power Service Corporation,
NewYork,NY
Digital computer-based protection has been the subject of several during recent years. It has been recognized that such protection systems are likely to be parts of a hierarchical computer system within the substation; dedicated to protection, control, alarm and data logging functions of a substation. Computer based protective devices are independent of all other subsystems, yet they are able to share certain data paths with other subsystems in order to improve the redundancy in the total system. Work in progress at the American Electric Power Service Cor¬ poration has been reported in several earlier publications. Effort at AEP to studies
up
this time has concentrated upon transmission line
protection and the general framework for the hierarchical computer system. This paper considers the problem of transformer protection within the context of the hierarchical system. The transformers considered are three phase, multi-winding transformers. The protection under consideration is the percent differential protection of the transformer. The slope of percent differential characteristic is adjusted to make the differential relay insensitive to CT and relay inaccuracies, as well as the off-nominal tap positions of the transformer. It has been known for many years that magnetizing inrush current may cause the percent differential relay to trip during transformer energization. An early solution to the inrush problem was the use of a "tripping suppressor" which used a voltage relay to suppress the tripping function of the differential relay when the voltages were high. By far the most common technique used for preventing false trips during energization is the use of a 'harmonic
relay. The harmonic restraint function should be so that it restrains during the magnetizing inrush and Conclusions overexcitation conditions, while during an internal fault the har¬ The Interactive Short Circuit System has been in use at Detroit monics generated by a saturated CT should not restrain the dif¬ relay. Edison for 11 months. The design criteria have been realized. Our ferential This paper describes a transformer protection algorithm for a relay engineers have a comprehensive data base of nine cases three-phase three-winding transformer which is compatible with covering most of the transmission and subtransmission networks in digital line protection. The major issue in compatibility is the ability Southeastern Michigan. More cases are planned. A fundamental restriction imposed by this re¬ The criterion of "modest" utilization has proven true. ISC uses less to share samples. quirement is that the sampling rate of 720 Hz must be used for the computer resource than other time sharing users. (The principal use transformer of time sharing at Detroit Edison is for computer program de¬ calculation ofalgorithm. The 720 Hz sampling rate makes the harmonics as straightforward as the fundamental velopment.) frequency calculations used in line relaying. If the signal f(t) is ISC is, indeed, interactive. Investigation of proposed circuit assumed be periodic with a fundamental frequency of 60Hz and changes are now studied in one session with no batch short circuit limited totothe fifth harmonic by the anti-aliasing filter then the runs needed. A local printer is frequently used to record the results of relation between the samples and the harmonics computed be¬ investigations. Experience to date has disclosed no serious deficiencies in the ginning at the stn sample is overall system design. A future need is the capability to add and change mututal im¬ fk f{kAt)t At 720 pedances interactively. The authors know of no convenient method of altering a Z-bus to reflect the addition of a mutual impedance. restraint'
designed
=
References
[1] H. E. Brown, L. K. Kirchmayer, C. E. Person, and C. W. Stagg, "Digital Calculation of Three-phase Short-Circuits by Matrix Method," AIEE Paper No. CP 60-181.1959. [2] D. C. Tarsi, "Simultaneous Solution of Line-Out and Open-End Line-to-Ground Short Circuits," IEEE Transactions PAS, vol. 89 July/August 1970. 28.
"
or
--
vhfkG
12
+r2['-2
-fr]e-
in recursive form (r+1)
2-nnr
~Y1
PER FEB
There is evidence that a secure restraint function for a three-phase transformer can be obtained if a single harmonic restraint signal is derived by combining the harmonics of the three phases. The algorithm was programmed with two harmonic restaints per phase: one a second harmonic obtained by summing the magnitude of the second harmonic for all phases and the other a fifth harmonic restraint developed in a similar manner. The fundamental frequency phasors for the trip and restraint signals for each phase are computed using the recursive DFT formulation. In total, ten updates are computed for each phase (real and imaginary parts). It is clear that the simplicity in computation produced by the 720 Hz sampling rate is critical if 30 such calculations are to be made at each time step. The algorithm was programmed in Fortran for off-line processing of sampled data. The nine currents were sampled in real time and the data stored in a file which was subsequently processed by the Fortran program. The transformer was simulated on the AEP Simulator with a 765 kV Y connected primary, 345 kV Y connected secondary and 138 kVA connected tertiary. The model transformers were single phase units connected to make a three-phase unit. The model transformer exhibited inrush phenomena. A total of 19 faults and energizations were simulated to test the various features of the
In this paper, the leakage is used advantageously for detecting fluctuations in the power system frequency. Considering the oscillatory nature of the frequency decay, and the randomness associated with the oscillations, a Kaiman filter is developed to optimally estimate the average rate of frequency decay as well as the mean value of the frequency.
Determination of the Frequency Fluctuations As previously mentioned, the leakage in the FFT is used advantageously to detect fluctuations in the fundamental frequency of a power system. The method is based on a leakage coefficient defined as V=
J2
\X(k)\-\X(V\ /IW)I (1)
where X{k) denotes the discrete Fourier transform (DFT) and *=1 corresponds to the fundamental component, viz. 60Hz. Since the leakage coefficient (t?) is defined for only one frequency component, the waveform must be low pass filtered. The waveform is then algorithm. at a sampling rate of 32 samples per cycle; therefore, the Since the development of the fundamental frequency signal sampled frequency is 1.92kHz. Now if is zero, no leakage has sampling always lags the development of the harmonic signals during a occurred, which in turn implies that ther¡frequency component at transition period, the restraint function prevails immediately fol¬ 60Hz has not deviated. Whenever the 60 Hz deviates by ±Afthe lowing the occurrence of a fault, until fault data of one cycle duration leakage coefficient will be nonzero. is available, at which time a secure relaying decision can be made. In To examine how the leakage coefficient varies with the frequency this sense the transient response of the DFT calculations is ideal for deviation, the frequency of a sinusoidal waveform was reduced from the transformer protection problem. The algorithm never mis- 60 to 55Hz; thus the frequency deviation range (A/) was 5Hz. The operated: for all noninternal faults and energizations the restraint leakage coefficient (77) was computed every 0.05Hz deviation. The signal dominated the trip signal and for all internal faults the proper curve appeared to be linear over this frequency range, a leasttrip signal was developed. squares fit was made to the results and a slope of 0.095584345 sec An ulta high speed version of the "tripping supressor" can also be was obtained. This slope represents a deviation of 0.07 percent from implemented digitally. It has been shown that fundamental fre¬ that calculated directly from the first and last points on the curve. quency phasors for both voltage and current can be computed in as Therefore, the curve is essentially linear over the 5Hz range. In¬ little as one quarter of a cycle. Using the quarter cycle calculations creasing the frequency from 60 to 65Hz, the same curve was the differential check can be computed more rapdily than the obtained. Therefore, rj will only give the magnitude of the frequency harmonic restraint is available. If the voltage phasor is computed deviation. To determine if the deviation is an increase or a decrease, with the same quarter cycle algorithm then the voltage restraint can the real part of the fundamental frequency must be examined. If Real be used instead of the harmonic restraint. then the deviation is a decrease, whereas Real {X(1)}>0 {X(1)}