energies Article
A Modularized Discharge-Type Balancing Topology for Series-Connected Super Capacitor String Shaogui Fan 1 1 2
*
ID
, Li Sun 1 , Jiandong Duan 1, * and Dong Zhang 2
School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin 150001, China;
[email protected] (S.F.);
[email protected] (L.S.) State Grid Heilongjiang Electric Power Company Limited, Qiqihar Power Supply Company Power Dispatching Center, Qiqihar 161005, China;
[email protected] Correspondence:
[email protected]; Tel.: +86-158-0451-0569
Received: 6 May 2018; Accepted: 31 May 2018; Published: 4 June 2018
Abstract: This paper proposed a modularized discharge-type topology for the voltage balance of series-connected super capacitor (SC) string. The proposed topology consists of cascaded converter modules and a boost converter. The cascaded converter modules discharge the higher voltage SCs directly with the ideal output current to realize a fast balancing speed and the boost converter feedbacks the extra energy from the higher voltage SCs to the super capacitor energy storage system (SCESS). The modular design of the cascaded converter modules makes the balancing system suitable for different voltage levels of SCESS. Unlike the charge-type topologies which discharge the higher voltage SCs indirectly, the proposed topology discharges the higher voltage SCs directly with a big current, and the over voltage phenomenon of SCs is then avoided, which means the reliability of the SCESS can be improved. The voltage stress of the switches inside the cascaded converter modules is low, which is different from the existing modularized discharge-type balancing topology. What is more, the control of cascaded converter modules and the boost converter can be implemented by analog devices which will simplify the control of the whole system. The control degree of freedom is high and the voltage of each cell can be controlled. An in-depth comparison analysis with the charge-type balancing topology is performed from the perspective of balancing speed and round-trip energy efficiency. The proposed topology and the balancing performance are confirmed by experimental results. Keywords: super capacitor balancing topology; cascaded converter; maximum power discharge; fast balancing speed; high round-trip energy efficiency
1. Introduction The super capacitor energy storage system (SCESS) with the advantages of a high-power density, long life, and widely operating temperature, is widely used in industrial applications. The super capacitors (SCs) are low voltage devices, the rated voltage of which with organic electrolytes is uaverage > uSC2. The higher voltage SCs C1 and C3 should be 1discharged and the extra satisfy > uSC3 > uaverage > uSC2capacitors . The higher C1 the andlower C3 should be SC discharged and SC1 energyuis transferred to the filter Co1 voltage and Co3,SCs while voltage C2 should notthe be extra energy is transferred to the filter capacitors C and C , while the lower voltage SC C should 2 o1 o3 discharged, and the corresponding cascaded converter module acts as wires. The block diagram of not discharged, and theiscorresponding cascaded acts as wires. The block diagram thebe balancing principle shown in Figure 3. Theconverter outputs module of the cascaded converter modules are of the balancing principle is shown in Figure 3. The outputs of the cascaded converter modules connected in series to form a cascaded converter and the cascaded output voltage is uo1 + uo3. The are connected infeedbacks series to form a cascaded and the cascaded output is uo1 + uo3 . Co3 tovoltage the SCESS. boost converter the energy storedconverter in the filter capacitors Co1 and The boost converter feedbacks the energy stored in the filter capacitors C and C to the SCESS. by o1 CSi, which o3 The cascaded converter modules are controlled by the control signal is generated the balancing controller. For the higher voltage SCs, the control signal is CSi = 1, while for the lower voltage SCs, it is CSi = 0. When CSi = 1, the fly-back converter of the ith cascaded converter module starts working to discharge the higher voltage SC and transfer the excess energy to the filter capacitor Coi. When CSi = 0, the fly-back converter does not work, and the switch Ssi is turned on, so that the
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output of the cascaded converter module acts as wires. The drives of the cascaded converter modules and the main waveforms of the boost converter are shown in Figure 4, and the currents of the boost Energies 2018, 11, 1438 5 of 24 converter are shown in Figure 5.
C
Cascaded Converter Module1
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Co1
+ u - o1
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output of the cascaded converter module acts as wires. The drives of the cascaded converter modules output the cascaded converter module acts as wires. The drives of the cascaded converter modules Cascaded and theofmain waveforms ofCthe boost converter are shown inBOOST Figure 4, and the currents of the boost 2 converter Converter Module2 and the main of the5.boost converter are shown in Figure 4, and the currents of the boost converter are waveforms shown in Figure converter are shown in Figure 5. Co3
Cascaded Converter Module3
C3
+u - o3
C1 C1
Cascaded + Discharge-type Modularized Balancing uo1 Topology Converter Module1 Cascaded +Converter Module1 Co1 - uo1 Figure 3. 3. The The balancing balancing principle principle block block diagram diagram of of the the proposed proposed topology. topology. Figure Co1 BOOST Cascaded C2 converter Converter Module2 BOOST signal CS , which is generated by Cascaded by the control 1 CS3 The cascaded converterCCS modules are controlled i 2 converter Converter Module2 the balancing controller. For the CS2higher voltage SCs, the control signal is CSi = 1, while for the lower Co3 T voltage SCs, it is CSi = 0. When CSi = 1, the fly-back converter +u of the ith cascaded converter module Cascaded C o3 C3 o3 Converter Module3 starts working to discharge the G higher voltage SC and transfer +-u the excess energy to the filter capacitor Cascaded C3 s o3 Converter Module3 D not 1− D Coi . When CSi = 0, the fly-back converter does work, and the switch Ssi is turned on, so that the Discharge-type Modularized Balancing Topology output of the cascaded converter module acts as wires. The drives of the cascaded converter modules Discharge-type Modularized Balancing Topology Figure 3. The balancing principle block diagram of the proposed topology. and the main waveforms of the iboost converter are shown in Figure 4, and the currents of the boost L Figure 3. The balancing principle block diagram of the proposed topology. converter are shown in Figure 5. Bs
B
B
CS1 cascaded CS3 Figure 4. The drive of the converter modules and the main waveforms of the boost CS1 CS3 converter. CS2 T CS2 Bs
C1
+
DR
TBs
L D
iL
B
DB
+ uo1 -
ic
1 − DB 1 − DB
C1
SS1
-
L
iL
+
+ uo1 -
Co1
Isolated by transformers
iL Co1 iL
Isolated by transformers
-
Gs ic Gs
DR
SS1
CC3 1
C1
-
ic ic CCo3 o1
Co1
DR
+ u+o3 --uo1 + uo1 -
(a)
iL
L
iL
L
SSS3 S1
CC3 1
C1
SS1 S
-
++ + --
DR
ic
DR
ic CCo3 o1
Isolated by by transformers Isolated transformers
Isolated by by transformers Isolated transformers
++ + --
DR
SCESS
SCESS
Figure 4. The drive of the cascaded converter modules and the main waveforms of the boost S S +the cascaded converter modules + and the main waveforms of the boost Figure Thedrive drive of Cand converter. 2 2 Figure 4.4.The ofCthe cascaded converter modules the main waveforms of the boost converter. u+o2 u+o2 Co2 Co2 SS2 SS2 converter. -
Co1
+ u+o3 --uo1 + uo1 -
(b)
iL
L
iL
L SSS3 S1
SS1 S
SCESS SCESS
SCESS SCESS
+ C2 + S S The switch S is turned Figure 5. The currents of the boost u+o2 u+o2 on;S(b) Co2 converter. SS2 (a) The switch + S isCturned o2 S2 C2 + C 2 + + off. uo2 uo2 Co2 Co2 SS2 SS2 As shown in Figure 4, the control signals CS1 = 1 and CS3 = 1, while CS2 = 0. The output of the C3 +to uo1 + uo3. The boost converter C3 + cascaded converter is equal is driven by the PWM signal Gs, and the + + Co3 Co3 uo3 uo3 + S SS3 S3 C3 C3 + current is shown in Figure 5. in Figure 5a, when the is high, the inductor current iL + + - As shown Co3 Co3 PWM uo3 uo3 SS3 SS3 increases. As shown in Figure 5b, when the PWM is -low, the inductor current decreases and the (a) (b) energy is fed back to the SCESS. C2
(a)
(b)
Figure 5. The currents of the boost converter. (a) The switch S is turned on; (b) The switch S is turned Figure 5. The currents of the boost converter. (a) The switch S is turned on; (b) The switch S is Figure 5. The currents of the boost converter. (a) The switch S is turned on; (b) The switch S is turned off. turned off. off.
As shown in Figure 4, the control signals CS1 = 1 and CS3 = 1, while CS2 = 0. The output of the As shown in Figure 4, the CS1converter = 1 and CS = 1, while CSPWM 2 = 0. The output of the cascaded converter is equal to ucontrol o1 + uo3. signals The boost is3driven by the signal Gs, and the cascaded equal 5. toAs uo1shown + uo3. The boost converter the PWM signal Gscurrent , and theiL current isconverter shown inisFigure in Figure 5a, when is thedriven PWMby is high, the inductor current is shown in Figure 5. As5b, shown in the Figure 5a, is when is high, the inductor current iL increases. As shown in Figure when PWM low,the thePWM inductor current decreases and the increases. As back shown energy is fed to in theFigure SCESS.5b, when the PWM is low, the inductor current decreases and the
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The energy transferred process of the proposed balancing topology is divided into two parts: one is the cascaded converter modules, which discharge the higher voltage SCs and transfer the extra energy the filter capacitors; the other is the converter, the energy Asto shown in Figure 4, theand control signals CS1boost = 1 and CS3 = 1,which while transfers CS2 = 0. The output stored of the in the filter capacitors to thetoSCESS. The energy simultaneously an cascaded converter is equal uo1 + uo3 . The boosttransferred converter isprocess driven works by the PWM signal Gs , with and the independent control sequence. Next, the working principle of the cascaded converter module current is shown in Figure 5. As shown in Figure 5a, when the PWM is high, the inductor current iis L discussed in11,detail. increases. As shown in Figure 5b, when the PWM is low, the inductor current decreases and the energy Energies 2018, x FOR PEER REVIEW 6 of 24 of the cascaded converter module is shown in Figure 6, which consists of a is fedThe backtopology to the SCESS. fly-back converter and a switch SSi paralleled with thebalancing output capacitor oi. divided The fly-back converter The energy transferred process of the the proposed proposed balancing topologyCis into two parts: The energy transferred process has the isolationmodules, and discharge. Compared to the voltage forwardSCs converter, the the fly-back one is is thefunction cascadedofconverter converter modules, which discharge discharge the higher higher voltage SCs and transfer transfer the extra one the cascaded which the and extra converter has the advantages of avoiding the use of output filter inductance, a freewheeling diode, energy to the filter capacitors; and the other is the boost converter, which transfers the energy stored energy to the filter capacitors; and the converter, which transfers the energy stored and a specialized transformer reset circuit, whichtransferred will make process the converter in size. Thewith switch in the the filter capacitors capacitors to the the SCESS. SCESS. The energy energy transferred process workssmall simultaneously with an in filter to The works simultaneously an Sindependent Si is used to make a short circuitNext, of thethe output capacitor Coi to of make cascaded converter module control sequence. working principle cascaded converter module is independent control sequence. Next, the the the cascaded converter module is act as wires. discussed in detail. discussed in detail. The topology drive of the cascaded converter module is is shown asinFigure control CSai topology the cascaded converter module is shown in 7, Figure 6,the which consists of The ofofthe cascaded converter module shown Figure 6,where which consists of signal a fly-back is used toconverter control theand working of the converter. The switch driven by the complementary fly-back aSiswitch SSi fly-back paralleled with thecapacitor output capacitor C oi. The fly-back converter converter and a switch S paralleled with the output CSoiSi. is The fly-back converter has the signals of CS i . If the voltage of ith SC is higher than the average voltage, CS i = 1, the corresponding has the function of isolation and discharge. Compared to the forward converter, the fly-back function of isolation and discharge. Compared to the forward converter, the fly-back converter has the cascaded module discharging SC. If the voltage of ith SC is lower than average converterconverter has advantages ofofavoiding thethe use of output inductance, a freewheeling diode, advantages of the avoiding the starts use output filter inductance, afilter freewheeling diode, and a the specialized voltage, the CS i is low, the fly-back converter does not work and the short circuit switch S Si is on, and and a specialized transformer reset circuit, which will make the converter small in size. The switch transformer reset circuit, which will make the converter small in size. The switch SSi is used to make a the cascaded converter module acts as wires. SSi is used toof make a shortcapacitor circuit ofCthe output capacitor C oi to make the cascaded converter module short circuit the output to make the cascaded converter module act as wires. oi act as wires. The drive of the cascaded converter module is shown as Figure 7, where the control signal CSi Ti Di i is used to control the working of the Lmi fly-back + * converter. The switch SSi is driven by the complementary C ioi + imi + signals of CSi. If the voltagei of+ith SC is voltage, CSi = 1, the corresponding V1ihigher than the average umi uSCi Coi uoi S Sith i cascaded converter module starts discharging the SC. If the voltage of SC is lower than the average Si * voltage, the CSi is low, the fly-back converter does not work and the short circuit switch SSi is on, and the cascaded converter module acts as wires. Figure 6. The cascaded converter module.
Ti
D Ci ioi + i + + fly-back used to control the working of the converter. The switch SSi ismi driven by the complementary V 1 i GSSi uSCi Coi uoi SSi umi - SC signals of CSi . If the voltage of ith than the average voltage, CSi = 1, the corresponding Si is higher * SC. If the voltage of ith -SC is lower than the average cascaded converter module starts discharging the GSi voltage, the CSi is low, the fly-back converter does not work and the short circuit switch SSi is on, and the cascaded converter module acts as wires. Figure 6. The cascaded converter module. Figure 7. The drives of the cascaded converter module. i iLmi +module CSi converter The drive of the cascaded is shown as Figure 7, where the control signal CSi is *
CSi To improve the discharging power of the modularized converter module, the fly-back converters are operated in continuousGcurrent mode (CCM) [29]. The switch Si is driven by high frequency PWM SSi Gsi. In the time interval 0~DTs, the switch Si is on, and the current iLmi increases linearly, which can be expressed as (2). In the Gtime interval DTs~Ts, the switch Si is off, and the energy stored in the Si magnetizing inductance is transferred to the filter capacitor. The peak current control strategy with the peak current ip is used to control the fly-back converter. The discharging power of the fly-back Figure 7. The The drives drives of the the cascaded cascaded converter module. Figure 7. of converter module. converter can be expressed as (3). To improve the discharging power of the modularized converter module, the fly-back converters uSCi To improve the discharging power of the modularized converter module, the fly-back converters (t ) =(CCM) [0 − DTS ]i is driven by high frequency PWM iLm0 + [29]. t The t ∈switch are operated in continuous currentimode (2) Lmi are operated in continuous current mode (CCM) [29]. Lm The switch Ss i is driven by high frequency PWM Gsi. In the time interval 0~DTs, the switch Si is on, and the current iLmi increases linearly, which can be Gsi . In the time interval 0~DTs , the switch Si is on, and the current iLmi increases linearly, which can expressed as (2). In the time interval DT1s~Ts, the switch Si is off, and the energy stored in the be expressed as (2). In the time interval s ~T s ,( ithe + iswitch − Δi ) Si is off, and the energy stored in the P =DTDu SCi p p magnetizing inductance is transferred fito the filter capacitor. The peak current control strategy with 2 magnetizing inductance is transferred to the filter capacitor. The peak current control strategy with (3) the peak current ip is used to control the fly-back converter. DuSCiTsThe discharging power of the fly-back 1 the peak current ip is used to control the=fly-back The DuSCi ( 2converter. ip − ) discharging power of the fly-back converter can be expressed as (3). 2 Lm converter can be expressed as (3). u i i (t ) = iLm0 + uSC t t ∈ [0 − DTs ] (2) iLmiLmi (t) = iLm0 + LSCi t t ∈ [0 − DT (2) s] Lm m
1 DuSCi (ip + ip − Δi ) 2 DuSCiTs 1 = DuSCi ( 2ip − ) 2 Lm
Pfi =
(3)
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= 12 DuSCi (ip + ip − ∆i )
Pf i
= 12 DuSCi (2ip −
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(3)
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where is affected by the load current; L m is is the where iiLm0 Lm0 is affected by the load current; Lm is the the magnetizing magnetizing inductance; inductance; 4 △ii is the increment increment of of current i during the time interval 0~DT ; D is the duty cycle of the PWM and T is the period; s s Lm current iLm during the time interval 0~DTs; D is the duty cycle of the PWM and Ts is the period; and and the voltage ith SC. usci isusci theisvoltage of ithofSC. The is controlled by the The output output voltage voltage of of the the cascaded cascaded converter converter module module is controlled by the control control signal signal CS CSii.. When CS = 1, G = 0, the output of the cascaded converter module is u . When CS = 0, G 1, i SSi oi i SSi When CSi = 1, GSSi = 0, the output of the cascaded converter module is uoi. When CSi = 0, GSSi = 1, =the the output of the cascaded converter module is zero. Thus, the output voltage of the cascaded converter output of the cascaded converter module is zero. Thus, the output voltage of the cascaded converter module can be expressed as (4). The outputs of the cascaded converter modules are connected in module uumi mi can be expressed as (4). The outputs of the cascaded converter modules are connected in series to form series to form aa cascaded cascaded converter, converter, thus, thus,the thecascaded cascadedoutput outputvoltage voltageU Uee can can be be expressed expressed as as (5). (5). (
mi umi== uuoi CS u CSii = =11 oi umi== 00 CS mi u CSii ==00
(4) (4)
n
U = CS i uoi Ue e= ∑ CSi uoi i =1 n
(5) (5)
i =1
is the the control controlsignal signalof ofith ithSC; SC;and anduuoi is is the where nn is is the the number number of of series-connected series-connectedSCs; SCs;CS CSiis where the voltage voltage i oi will be calculated in the next part. of ith ith filter filter capacitor capacitor C Coi,, which of oi which will be calculated in the next part. The boost boost converter converter can can be be simplified simplified as as shown shown in in Figure Figure 8, 8, where where the the input input voltage voltage of of the the boost boost The converter is is U Ue and and the the output output voltage voltage isisthe thevoltage voltageof ofSCESS SCESSUUSCESS.. The working principle of the converter e SCESS The working principle of the boost converter is very classic and familiar, and control of the boost converter be discussed in boost converter is very classic and familiar, and control of the boost converter willwill be discussed in the the next part. next part. DR
L
iC
+
Ue
S
-
+ U SCESS
iL
-
+ C -1 + C -2 + Cn -
Figure 8. 8. The simplified boost boost converter. converter. Figure The simplified
Through the above analysis, the voltage stress of switches can be ascertained. The voltage of SC Through the above analysis, the voltage stress of switches can be ascertained. The voltage of is usc, and the turn ratio of transformer is n. Then, the voltage stress of switch Si is (usc + uoi/n), and the SC is usc , and the turn ratio of transformer is n. Then, the voltage stress of switch Si is (usc + uoi /n), voltage stress of switch Ssi is uoi. Because the values of usc and uoi are small, the voltage stress of and the voltage stress of switch Ssi is uoi . Because the values of usc and uoi are small, the voltage stress switches inside the cascaded converter modules is low. The voltage stress of switch S in the boost of switches inside the cascaded converter modules is low. The voltage stress of switch S in the boost converter is USCESS, which is high. However, only one switch S is used in one balancing system and converter is USCESS , which is high. However, only one switch S is used in one balancing system and the current stress of switch S is low, so the price of switch S is acceptable. the current stress of switch S is low, so the price of switch S is acceptable. 3. Control and Analysis of The Proposed Balancing Topologies 3. Control and Analysis of The Proposed Balancing Topologies
3.1. Control Control and and Analysis Analysis of of the the Cascaded Cascaded Converter Converter Module Module 3.1. The cascaded cascaded converter converter module module is is controlled controlled by by the the control control signal signal CS. CS. The The peak peak current current control control The strategy with a 50% maximum duty cycle is used to control the fly-back converter, which can strategy with a 50% maximum duty cycle is used to control the fly-back converter, which can guarantee guarantee of the fly-backwithout converter needramp of current ramp compensation [30]. the stabilitythe of stability the fly-back converter thewithout need of the current compensation [30]. The control The control circuit of the cascaded converter module is shown in Figure 9. circuit of the cascaded converter module is shown in Figure 9.
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Ci C i
8 of 24 of 24 24 88 of
Lmi iiLmi
++ u SCi uSCi --
SSii
++ V V 1i
**
p
Di iioi D i oi
Coi C oi
1i
--
Current Current sampling sampling iip
TTii
-++
** PWM PWM
RS flip-flop flip-flop RS RR SS
TTss 50% PWM 50% PWM CS CS
R1 R 1
。
＆ ＆
mi
--
OP2 OP 2 OP1 OP 1
VCC VCC 11
++ uumi
++ SSSSii uuoioi --
R2 R 2 VCC VCC 22
..
Figure9. 9. Control Controlcircuit circuitof ofthe thecascaded cascadedconverter convertermodule. module. Figure Figure 9. Control circuit of the cascaded converter module.
The drive drive of of the the fly-back fly-back converter converter is is the the result result of of logical logical operations operations of of control control signal signal CS CS AND AND The The drive of the fly-back converter is the result of logical operations of control signal CS AND 50% duty cycle PWM AND the output of the RS flip-flop. The control signal CS is used to control the 50% duty duty cycle cycle PWM PWM AND AND the the output output of of the the RS RS flip-flop. flip-flop. The The control control signal signal CS CS is is used used to to control control the the 50% cascaded converter in terms of whether it works or not. The 50% duty cycle PWM is used to limit the cascaded converter converter in in terms terms of of whether whether itit works works or or not. not. The The 50% 50% duty duty cycle cycle PWM PWM is is used used to to limit limit the the cascaded max duty cycle of the PWM to ensure the stability of the converter. The output of the RS flip-flop is max duty duty cycle cycle of of the the PWM PWM to to ensure ensure the the stability stability of of the the converter. converter. The The output output of of the the RS RS flip-flop flip-flop is is max used to limit the peak current to i P to prevent over current. Figure 10 shows the main waveforms of used to to limit limit the the peak peak current current to to iiPP to to prevent prevent over over current. current. Figure Figure 10 10 shows shows the the main main waveforms waveforms of of used the cascaded cascaded converter converter module. module. Figure Figure 10a 10a aa is is the the waveforms waveforms with with aa small small load load current, current, where where the the the the cascaded converter module. Figure 10a a is the waveforms with a small load current, where the PWM duty duty cycle cycle is is limited limited to to 50% 50% and and the the current current iiLm Lm does not reach the peak current iP. Figure 10b PWM doesnot notreach reach the peak current P. Figure PWM duty cycle is limited to 50% and the current iLm does the peak current iP . iFigure 10b10b is is the waveforms with a big load current, where the current iiLm Lm reaches the peak value iP, the PWM is is the waveforms with a big load current, where the current reaches the peak value i P , the PWM is the waveforms with a big load current, where the current iLm reaches the peak value iP , the PWM is forced to low-level until the next cycle, and the converter is in cycle-by-cycle peak current limit mode. forced to to low-level low-level until until the the next next cycle, cycle, and and the forced the converter converter is is in in cycle-by-cycle cycle-by-cycle peak peak current current limit limit mode. mode. The turning turning on on of of the the short short circuit circuit switch switch SSi is decided decided by by optocouplers optocouplers OP OP1 and and OP OP2. Optocoupler Optocoupler The The turning on of the short circuit switch SSSiSiisisdecided by optocouplers OP11and OP22.. Optocoupler OP11 is is controlled controlled by by CS. CS. If If CS CS == 0, 0, one one condition condition to to turn turn on on SSSiSi is is ready. ready. Optocoupler Optocoupler OP OP22 is is used used to to OP OP 1 is controlled by CS. If CS = 0, one condition to turn on SSi is ready. Optocoupler OP2 is used to monitor the the output output capacitor capacitor voltage uuoioi to to avoid the the high voltage voltage before the the output capacitor capacitor Coioi is is monitor monitor the output capacitor voltage voltage uoi toavoid avoid thehigh high voltagebefore before theoutput output capacitorCC oi short circuited. The short circuit switch S Si will not turn on until CS = 0 and the output capacitor short circuited. the output output capacitor capacitor is short circuited.The Theshort shortcircuit circuitswitch switchSSiSSiwill willnot notturn turnon onuntil until CS CS == 00 and and the voltage uuoioi reaches reaches aa reasonably reasonably low low value. value. voltage voltage uoi reaches a reasonably low value.
CS CS 50%PWM 50%PWM
iipp Lm iiLm RR SS PWM PWM
(a) (a)
(b) (b)
Figure Figure10. 10. Main Main waveforms waveformsof ofthe thecascaded cascadedconverter convertermodule. module.(a) (a) With Withaaasmall smallload loadcurrent. current.(b) (b) With With Figure 10. Main waveforms of the cascaded converter module. (a) With small load current. (b) With aabig load current. big load current. a big load current.
Toensure ensurethat thatthe thedischarging dischargingpower powerisis isgreater greaterthan thanthe thedesigned designedvalue valuePPP000,,, the themagnetizing magnetizing To To ensure that the discharging power greater than the designed value the magnetizing inductance L m should should be bound. The discharging power of the fly-back converter can be expressed inductance L be bound. The discharging power of the fly-back converter can be inductance Lm m be expressed expressed as (3), and the maximum discharging power can be expressed as (6). Let P omax be bigger than o, which as and the themaximum maximumdischarging dischargingpower power can expressed as (6). Let be bigger Po , as (3), and can bebe expressed as (6). Let P omaxPbe bigger than PPthan o, which omax resultsresults in (7). (7). in (7). which results in 1 Dmax uSCmax Ts Pomax = D11max uSCmax (2ip − D (6) DmaxuuSCmaxTTs ) 2 Lm s )) max SCmax P = D u ( i − 2 (6) omax = maxu SCmax( 2i p − Pomax D (6) LLmm 22 max SCmax p
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2 2 9 of 24 Ts Dmax uSCmax (7) 2(ip Dmax uSCmax − Po ) Ts D2 u2SCmax Lm >voltage ofmax where Dmax = 0.5, uSCmax is the maximum ip is−the current, and Ts is the period. (7) 2(ip DmaxSC, uSCmax Popeak ) Next, the relationships between the output current and discharging power of the cascaded where Dmaxmodule = 0.5, uSCmax is the maximum voltage SC, iinterval current, and Ts isof theiLmperiod. p is the peak converter will be discussed. During theoftime 0~DT s, the rise rate can be Next, the relationships between the output current and discharging power of the cascaded iLm is expressed as (8) and the current iLm changing with time is shown in Figure 11. The current converter module will be discussed. During the time interval 0~DT , the rise rate of i can be s Lm limited to a rectangle which is made of ranges of time DmaxTs and peak current ip. The average value expressed as (8) and the current i changing with time is shown in Figure 11. The current i is Lm Lm of the current iLm can be expressed as (9). limited to a rectangle which is made of ranges of time Dmax Ts and peak current ip . The average value u of the current iLm can be expressed as (9). m = u sc (8) sc m = Lm (8) Lm
Lm >
1 i = iLm0 + 1 mD 22Ts iLmLm= iLm0 + 2 mD Ts 2
iLm ip '' Lm0
A
' Lm0
B
i
i
iLm0 C D
(9) (9)
I
H
m3 m2
iLm ↓
G
m1
iLm ↓ E
F Dmax Ts
t
Figure11. 11.The Thecurrent currentiLm iLm changing with time. Figure
The initial initialcurrent currentiiLm0 and duty cycle D vary with load current. Line segments CG, BH, and AI The Lm0 and duty cycle D vary with load current. Line segments CG, BH, and AI represent the the iiLm atataasmall current, ideal load current, andand large loadload current, respectively, and represent smallload load current, ideal load current, large current, respectively, Lm the line segments have the same rise rate m. When the current i Lm reaches the line segment BH, the and the line segments have the same rise rate m. When the current iLm reaches the line segment BH, average current of iLm the maximum value,value, whichwhich can becan expressed as (10).as When average the average current ofreaches iLm reaches the maximum be expressed (10).the When the discharging current is the maximum, the discharging power reaches the maximum, and the i Lm average discharging current iLm is the maximum, the discharging power reaches the maximum, and the correspondingaverage averageoutput outputcurrent currentcan canbe becalculated calculatedas as(11). (11). corresponding 1 iLm max =1 DBmax ( 2i p − mDBmaxTB ) iLmmax = 2DBmax (2i p − mDBmax TB ) 2 n(1 − DBmax )( 2ip − mDBmaxTB ) n(1 − DBmax )(2i p − mDBmax TB ) ioidealioideal = = 22
(10) (10) (11) (11)
where wherennisisthe thetransformer transformerratio. ratio. Define Definethe theaverage average output output current currentcalculated calculatedas as(11) (11) as as the the ideal ideal output output current, current, and and at at this this load load current, current, the the discharging discharging power power of ofthe thecascaded cascadedconverter converter module module reaches reachesthe themaximum. maximum. Due Due to to the the implementationofof cascaded converter module beingonbased on the analog devices, the implementation thethe cascaded converter module being based the analog devices, the magnetizing magnetizing Lm and the switching change innear a small nearvalue, the designed inductance Lminductance and the switching period Ts will period changeTins will a small range the range designed and the , Ts,three-dimensional and Lm. The three-dimensional graphoutput of the value,output and the ideal varies outputwith current with ideal current uSC varies , Ts , and Lmu. SC The graph of the ideal − 6 6 s, −6 −6 ideal output withDparameters D= max = 0.5, 1/3, uSC =V,1.5~3 s =10 15 ×~20 10 × ~2010×−10 current with current parameters 1/3, ip n==20 A,ipu=SC20=A, 1.5~3 Ts =V, 15T× max = 0.5, n − 6 − 6 −6 −6 = 15 is is shown asas Figure 12.12. Ls,mL=m 15 × ×1010 ~25 ××10 10 HH shown Figure
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3.3 3.28 3.3 3.28 3.25 3.27 3.25 3.27 3.26 3.2 3.26 3.2 3.25 i 3.25 oideal 3.15 i 3.15 oideal 3.24 (A) 3.24 3.1 3.23 (A) 3.1 3.23 3.05 3.22 3.05 3.22 3 3.21 31.5 3.21 1.5 1.6 1.6 1.7 1.7 1.8 1.9 2 −5 TsT(s ×(×111.8 00−5s)s) 1.9 2 2.1 2.1
3.28 3.28 3.26 3.26
1.5 1.5
2.5 (V) 2.5 22 uuSCSC(V)
33
(a) (a)
3.3 3.3 3.25 3.25 3.2 3.2
3.24 3.24 i ioideal 3.15 3.22 oideal (A) 3.15 3.22 (A) 3.1 3.1 3.2 3.2 3.05 3.05 3.18 3.18 333 3
2.5 2.5 2 (V) 2 uuSCSC(V)
1.5 1.5
2.6 2.4 2.6 2.2 2.4 1.8 22 2.2 -5 1.6 1.8 L (×10 H) -5 1.4 m Lm(×10 H) 1.4 1.6
(b) (b)
Figure12. 12.Ideal Idealoutput output current varies with s, and (a)(a) Ideal output current varies with and Figure 12. Ideal outputcurrent currentvaries varieswith withuuSC uSCSC ,s,T Ideal output current varies with u Figure , ,TT and LLmm.L.(a) output current varies with uuSCSCand s , and m . Ideal SC s. (b) Ideal output current varies with u SC and L m. L . T and T . (b) Ideal output current varies with u and Ts. (b) sIdeal output current varies with uSC andSCLm. m
As shownin in Figure12, 12, theideal ideal output outputcurrent currentdecreases decreaseswith withthe theincrease increaseof ofuuSCSCand and Ts,s,and and As As shown shown inFigure Figure 12,the the ideal output current decreases with the increase of uSC T and Ts , increases with with the the increase of of Lmm,, but but the the range range of of the the changes isis small. small. When uuSCSC == 33 V, V, increases and increases with increase the increase−6Lof Lm , but the range of thechanges changes is small. When When uSC = 3 V, −6 s, and Lm = 15 × 10−6 s = 20 × 10 H, the ideal output current reaches the minimum value of 3.17 A; T −6 −6 the and LmLm = 15 × 10 ideal output current reaches the T Tss ==20 20 ××1010−s,6 s, and = 15 × 10H, H, the ideal output current reaches theminimum minimumvalue valueof of3.17 3.17A; A; whenuuSCSC==1.5 1.5V, V,TTss==15 15××10 10−6−−66s,s,and andLLmm==25 25××10 10−6−6−H, H, theideal idealoutput outputcurrent currentreaches reachesthe themaximum maximum 6 when the when uSC = 1.5 V, Ts = 15 × 10 s, and Lm = 25 × 10 H, the ideal output current reaches the maximum value of 3.29 3.29 A. Trying Trying to make make the the parameters parameters of each each cascaded converter converter module consistent consistent can value value of of 3.29 A. A. Trying to to make the parameters of of each cascaded cascaded converter module module consistent can can further reduce the change. So, it can be assumed that the ideal output current remains constant further reduce the change. So, it can be assumed that the ideal output current remains constant further reduce the change. So, it can be assumed that the ideal output current remains constant throughout therange range ofuuSCSC.. throughout throughout the the range of of uSC . 3.2.The TheControl ControlStrategy Strategyof ofthe theBoost BoostConverter Converter 3.2. 3.2. The Control Strategy of the Boost Converter Thecascaded cascadedconverter convertermodules modulesshould shouldoutput outputthe theideal idealoutput outputcurrent currentto todischarge dischargethe thehigher higher The The cascaded converter modules should output the ideal output current to discharge the higher voltage SCs with the maximum discharging power to achieve a fast balancing speed. The ideal output voltage voltage SCs SCs with with the the maximum maximum discharging discharging power to achieve achieve a fast fast balancing balancing speed. speed. The The ideal idealoutput output currentof ofcascaded cascadedconverter convertermodules modulesis isrealized realizedby bycontrol controlof ofthe theboost boostconverter. converter.The Theinductance inductance current current of cascaded converter modules is realized by control of the boost The inductance current iiLiL isis is difficult difficult to to regulate regulate due due to to the the wide wide range range of ofthe theinput inputvoltage voltageU Uee.. So, So, the the hysteresis hysteresis current input voltage U current difficult to regulate due hysteresis e So, the L current control strategy which has self-stabilization characteristics [31,32] is used to control theboost boost current current control control strategy strategy which which has has self-stabilization self-stabilization characteristics characteristics [31,32] [31,32] is is used used to to control control the the boost converterand andthe thecontrol controlcircuit circuitdiagram, diagram,as asshown shownin inFigure Figure13. 13. converter converter and the control DDRR
LL
iLiL
SS
UUee
GGs s
UUSCESS SCESS
imim
CC
iLiL RR
iLp iLp
SS
iLmin iLmin
ofthe theboost boostconverter converterwith withhysteresis hysteresis current current control strategy. Figure13. 13.Control Controlcircuit circuitdiagram diagramof currentcontrol controlstrategy. strategy. Figure
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As shown shown in in Figure Figure 13, 13, the the hysteresis hysteresis current current control controlstrategy strategyisisrealized realizedby byan anRS RSFlip Flip Flop Flop and and As comparators, and the main waveforms of the boost converter are shown as Figure 14. The given comparators, and the main waveforms of the boost converter are shown as Figure 14. The given minimum inductance inductance current current iiLmin and maximum inductance current iLp are set by potentiometers. minimum Lmin and maximum inductance current iLp are set by potentiometers. L < iLmin, the Flip Flop is set, and the switch is turned on, so iL begins to increase. When iL > iLp, When i When iL < iLmin , the Flip Flop is set, and the switch is turned on, so iL begins to increase. When Flip Flop is reset, the switch is turned off, and iL begins to decrease. The average input current of ithe L > iLp , the Flip Flop is reset, the switch is turned off, and iL begins to decrease. The average input the boost is inwhich hysteresis control mode can be expressed (12). In order to current of converter the boost which converter is in current hysteresis current control mode can be as expressed as (12). make the cascaded converter output the ideal output current, Equation (13) should be satisfied. In order to make the cascaded converter output the ideal output current, Equation (13) should be According to Equation (12) and (12) Equation (13), (14)(13), is obtained. When iLmin ≈ 0 iand iLp satisfy Equation satisfied. According to Equation and Equation (14) is obtained. When Lmin ≈ 0 and iLp satisfy (14), the ideal output current of the cascaded converter is realized. Equation (14), the ideal output current of the cascaded converter is realized. iL = 0.5iLmin + 0.5iLp iL = 0.5iLmin + 0.5iLp
(12) (12)
i = ioideal iL L= ioideal
(13) (13)
ioideal − − iiLmin iLpiLp = =2i2oideal Lmin
(14) (14)
R S
Gs iLp iL
iLmin
Figure Figure 14. 14. The The main main waveforms waveforms of of the the boost boost converter. converter.
ThePWM PWMfrequency frequencyof ofthe theboost boostconverter converterchanges changeswith withU Ue and and the the maximum maximum frequency frequency should should The e be limited. limited. The The PWM PWM frequency frequency can can be be expressed expressed as as (15). (15). When When U Ue == 0.5 USCESS, the PWM frequency fB be 0.5U e SCESS , the PWM frequency reaches the maximum, and the maximum value can be expressed as (16). If the maximum PWM PWM f B reaches the maximum, and the maximum value can be expressed as (16). If the maximum frequency of the boost converter is limited to f Bmax（fBmax）, then the filter inductance L shall satisfy frequency of the boost converter is limited to f Bmax (f Bmax ), then the filter inductance L shall satisfy (17). (17). Ue Ue fB = (1 − U e ) (15) Ue L ( i − i ) U f B = Lp ) Lmin (1 − SCESS (15) L(iLp − iLmin ) USCESS USCESS f Bmax = (16) U − iLmin ) fBmax =4L(iLpSCESS (16) 4 L(iLp − iLmin ) USCESS (17) L> 4 f Bmax (UiLp − iLmin ) SCESS L> (17) where Ue is the output voltage of the cascaded 4 f Bmax (iconverter, − iLmin ) USCESS is the voltage of the SCESS, Lp and Ue < USCESS . Ue issmall the output voltage the cascaded USCESS is the voltage thecause SCESS, and where A too or too large Ueofvalue will lead converter, to a too low frequency, which of will failure < Ucontrol SCESS. Uethe of system. The low frequency caused by a too small and too large Ue value will be A too small or too large Ue value will lead to a too low frequency, which will cause failure of the discussed, respectively. control system. The lowthe frequency by aonly too small and too large SC Ue value discussed, When Ue is small, extreme caused case is that one higher voltage needs will to bebedischarged, respectively. and the cascaded output voltage is equal to the output voltage of one cascaded converter module. Ue is S small, the extreme case is thatLonly one higher voltageisSC needs toinbeparallel discharged, WhenWhen the switch is turned on, the inductance of the boost converter connected with and the cascaded output voltage is equal to the output voltage of one cascaded converter module. the output capacitance Co to form a resonant circuit. When the PWM frequency is less than two times When the resonant switch S is turned on, inductance L of the boost of converter is connected in parallel that of the frequency of the L and Co , the output voltage the cascaded converter module with will the output capacitance C o to form a resonant circuit. When the PWM frequency is less than two times reach zero (ignoring the line resistance). This will cause a short circuit of the cascaded converter that of the frequency and Cincrease, o, the output voltage of the cascaded converter module will module, theresonant inductance currentof iL Lcannot and the peak current value iLp will not be reached. reach zero (ignoring the line resistance). This will cause a short circuit of the cascaded converter module, the inductance current iL cannot increase, and the peak current value iLp will not be reached.
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The switch switch SS of of the the boost boost converter converter will will maintain maintain the the on on state state and and the the cascaded cascaded converter converter module module The maintains the short circuit state. Figure 15 illustrates the waveforms of the output voltage u of the the maintains the short circuit state. Figure 15 illustrates the waveforms of the output voltage uoo of cascadedconverter convertermodule module inductor current iL boost of theconverter, boost converter, with frequency the PWM cascaded andand the the inductor current iL of the with the PWM L and C o. frequency slightly higher than two times that of the resonant frequency of slightly higher than two times that of the resonant frequency of L and Co . uo (V)
iL (A)
uomax uo iL
Figure Figure 15. 15. Waveform Waveform of of uuoo and and iiLL with with the the PWM PWM frequency frequency slightly slightly higher higher than than two two times times of of the the resonant frequency of L and C . o resonant frequency of L and Co.
As As shown shown in in Figure Figure 15, 15, the the voltage voltage uuoo is near near zero zero at at the the end end of of each each PWM PWM cycle, cycle, so so once once the the voltage cascaded converter module will will lead lead to a short The discharging power voltagereaches reacheszero, zero,thethe cascaded converter module to a circuit. short circuit. The discharging will reach minimum and the and extrathe energy fed back to the ensure normal power willthe reach the minimum extra cannot energy be cannot be fed backSCESS. to the To SCESS. Tothe ensure the operation of the balancing system, the resonant frequency of L and of CoLshould normal operation of the balancing system, the resonant frequency and Cosatisfy should(18). satisfy (18).
U 2 2 UUee fB = ((11−− eU e) ) √ ≤ f B≤ = iLmin )) UU (iLp−−iLmin L(LiLp 2π 2LC π oLCo SCESS SCESS
(18) (18)
whereUUe eis is the average output voltage cascaded converter. the average output voltage ofof thethe cascaded converter. where The converter voltage UeUcan be be assumed to be when the The output outputvoltage voltageofofthe thecascaded cascaded converter voltage e can assumed to invariant be invariant when PWM frequency is high; Ue changes with thewith inductor current iLcurrent when the PWM frequency Ue changes the inductor iL when the PWM the PWM frequency is however, high; however, is low. So, the average voltage U e isvoltage used toUreplace Ue to calculate in Equation (18). frequency is low. So, the average replace Uthe e tofrequency calculate the frequency in e is √used Assume that the average voltage U = u / 2, u is the maximum output voltage of the e omax omax Equation (18). Assume that the average voltage U e = u omax / 2 , uomax is the maximum output cascaded converter. The inductance current iL increases from zero, and the output voltage and voltage of the cascaded converter. The inductance current iL increases from zero, and the output discharging power increase with the increase of iL . When the discharging power reaches the maximum, voltage and discharging power increase with the increase of iL. When the discharging power reaches the output voltage reaches the peak voltage uomax , and the output current is equal to the ideal output the maximum, the output voltage reaches the peak voltage uomax, and the output current is equal to current, so the peak voltage uomax can be calculated as (19). Combining (18) and (19) produces (20). the ideal output current, so the peak voltage uomax can be calculated as (19). Combining (18) and (19) produces (20). ηPomax uomax = (19) ηioideal Po max uomax = (19) i2oideal π 2 η 2 Pomax L≤ 2 Co (20) 2 2ioidealπ(2iηLp2 P− iLmin )2 o max L≤ 2 Co (20) ioideal ( iLp −module; iLmin )2 Pomax is the maximum discharge power, where η is the efficiency of the modularized 2converter which can be calculated as (6); and ioideal is the ideal output current, which can be calculated as (11). where η is the efficiency of the modularized converter module; Po max is the maximum discharge Once Ue > USCESS , the inductance current iL cannot decrease to the minimum value iLmin , and the the ideal which can be calculated power, can beincalculated as (6); switch Swhich will remain the off state. Theand diodeioideal DR isisturned on output and thecurrent, voltage U e is clamped to USCESS . asthis (11).case, the output current of the cascaded converter is uncontrollable, and the ideal output current In inductance current iL cannot decrease to the minimum value Lmin, gets and the the Once Ue > USCESS, the cannot be guaranteed. So, the voltage U be limited by (21). Combining (19) and i(21) e should R is turned on and the voltage U e is clamped to U SCESS switch S will remain in the off state. The diode D maximum number of discharged higher voltage SCs and the maximum number calculated as (22).. In this case, thevoltage output exceed currentthe of average the cascaded converter output Suppose N SCs’ voltage and needistouncontrollable, be discharged.and If Nthe > mideal SCs max , the e should be limited by (21). Combining (19) current cannot beaccording guaranteed. So, order the voltage need to be sorted to the of theU voltage from big to small in real-time, and theand SCs(21) at gets the maximum number of discharged higher voltage SCs and the maximum number is calculated the top mmax are allowed to be discharged. If N < mmax , N SCs are all allowed to be discharged. as (22). Suppose N SCs’ voltage exceed the average voltage and need to be discharged. If N > mmax, muomax i ioideal .. The discharging power and efficiency change with decreases with the increaseofofi iowhen decreases with the increase o o oideal The discharging power and efficiency change with are shown shown as as Figure Figure 21. 21. The The discharging discharging power power first first increases increases and and then then decreases decreases output current current iioo are output When iioo == 3.2 the maximum, maximum, with the the increase increaseof ofoutput outputcurrent currentioio.. When with 3.2 A, A, the the discharging discharging power power reaches reaches the which is consistent with the calculated ideal output current. The ideal output current hardly changes which is consistent with the calculated ideal output current. The ideal output current hardly changes SC and the discharging power increases with the increase of uSC. The efficiency with the changing of u with the changing of uSC and the discharging power increases with the increase of uSC . The efficiency of the the cascaded cascaded converter converter module module decreases decreases with with the the increase increase of of the the output output current current and and the the efficiency efficiency of S is decided by the control signal is 80% at the ideal output current. The drive of short circuit switch S is 80% at the ideal output current. The drive of short circuit switch SS is decided by the control signal . As shown Figure is the control signal, o is CS and andthe thevoltage voltageofofthe theoutput output capacitor CS capacitor uoiu. oiAs shown in in Figure 22,22, CS CS is the control signal, uo isuthe SS is the drive of the short circuit switch SS. The short circuit the voltage of the output capacitor, and G voltage of the output capacitor, and GSS is the drive of the short circuit switch SS . The short circuit will not not turn turn on on until until CS CS = = 00 and switch SSSS will switch and the the voltage voltage u uoo reaches reaches an an acceptable acceptable low low value. value.
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PWM PWM PWM
iiLm Lm iLm
iio PWM(5V/div) o PWM(5V/div) io PWM(5V/div)
PWM PWM PWM
PWM(5V/div) PWM(5V/div) PWM(5V/div)
iio o io
PWM PWM PWM
PWM(5V/div) PWM(5V/div) PWM(5V/div)
iiLm Lm iLm
iiLm Lm iLm
iiLm (4A/div) io (1A/div) 10μs/div Lm (4A/div) io (1A/div) 10μs/div iLm (4A/div) io (1A/div) 10μs/div
iio o io
iiLm (4A/div) io (1A/div) 10μs/div Lm (4A/div) io (1A/div) 10μs/div iLm (4A/div) io (1A/div) 10μs/div
iiLm (4A/div) io (1A/div) 10μs/div Lm (4A/div) io (1A/div) 10μs/div iLm (4A/div) io (1A/div) 10μs/div
(a) With A. Figure Figure 20. 20. Main Main waveforms waveforms of of the the modularized modularized converter converter module. module. (a) (a) With output output current current iiooo === 111 A. A. Figure 20. Main waveforms of the modularized converter module. (a) With output current i o = 1 A. (b) With output current i = i = 4 A. o 3.1 A. (c) With output current o = 4 A. With output current i (b) With output current ioo = 3.1 A. (c) With output current ioo = 4 A. (b) With output current io = 3.1 A. (c) With output current io = 4 A. Pd is-uSC=1.5V Pd is-uSC=1.5V P -uSC =2.0V Pddis =1.5V dis SC =2.0V is-uSC -uSC=2.0V =2.5V Pdis-u P Pdis dis-uSC SC =2.5V Pdis-uSC =2.5V
1.5 1.5 1.5
η-uSC =1.5V η-uSC =1.5V η-uSC =2.0V =2.0V η-uSCSC=1.5V η-u η-uSC =2.5V η-uSCSC=2.0V =2.5V η-u η-uSC =2.5V
× ×× × ××× × ×× ××× × ×× ××
2 2 2
2.5 2.5 2.5
3.5 3 3.2 3 3.2 3.5 Output current io（A） Output current i 3.5 3 3.2 o（A） Output current io（A）
4 4 4
4.5 4.5 4.5
100 100 90 90 100 80 80 90 70 70 80 60 60 70 50 50 60 40 40 50 30 30 40 20 20 30 10 10 20 0 0 5 10 5 0 5
efficiency η（%） efficiency η（%） efficiency η（%）
Discharge power Discharge power PP Discharge power Pd is（W） is（W） d isd（W）
24 24 22 22 24 20 20 22 18 18 20 16 16 18 14 14 16 12 12 14 10 10 12 8 8 10 6 846 642 402 20 11 0 1
Figure 21. The discharging power and efficiency change with output current. Figure change with with output output current. current. Figure 21. 21. The The discharging discharging power power and and efficiency efficiency change Figure 21. The discharging power and efficiency change with output current. uuo (2V/div) o (2V/div) uo (2V/div)
G (5V/div) GSS SS (5V/div) GSS (5V/div)
CS CS (2V/div) (2V/div) CS (2V/div)
25ms/div 25ms/div 25ms/div
Figure Figure 22. 22. The The drive drive of of short short circuit circuit switch switch S SSS.. Figure 22. The drive of short circuit switch SS. Figure 22. The drive of short circuit switch SS .
The = 2.6 V, uSC2 = 2.4 V, and uSC3 = 2.2 V. The main waveforms of the The voltages voltages of of the the SCs SCs are are u uSC1 SC1 = 2.6 V, uSC2 = 2.4 V, and uSC3 = 2.2 V. The main waveforms of the The voltages of the SCs are u SC1 = 2.6 V, uSC2as 2.4 V, and uSC3shown = 2.2 V. The main of the boost converter and balancing time are shown 23. in Figure 23, iiLL is is the the inductor inductor boostThe converter and balancing time are shown as==Figure Figure 23. As As shown in Figure 23,waveforms voltages of the SCs are u = 2.6 V, u 2.4 V, and u = 2.2 V. The main waveforms of the SC1 SC2 SC3 the inductor boost converter and balancing areis as Figure 23. shown in Figurecontrol 23, iL isstrategy, current of converter which controlled with the hysteresis current and current of the the boost boost converter time which isshown controlled with 23. the As hysteresis current control strategy, and boost converter and balancing time are shown as Figure As shown in Figure 23, i is the inductor L strategy, current of the boost converter which is controlled with hysteresis current control and ethe is the input voltage of the boost converter, the average value can be calculated as Equation (12). U e is the input voltage of the boost converter, the average value can be calculated as Equation (12). U current of the boost converter whichasisEquation controlled with hysteresis current strategy, and is the input voltage ofcontrol theof boost the average value can be calculated (12). Ue the e is converter, caused by and is also the output voltage of the cascaded converter. The periodic fluctuation U e is caused by and is also the output voltage of the cascaded converter. The periodic fluctuation of U the average value can voltage be calculated as Equation (12). Ue The is the input voltage of the boost converter, e iis caused by and is also the output of the cascaded converter. periodic fluctuation of U L, and the average value of U e remains unchanged at a certain L value. is the periodic variation of i fb is the periodic variation of iL, and the average value of Ue remains unchanged at a certain iL value. iifb and is also the output voltage of the cascaded converter. The periodic fluctuation of U is caused evalue. L , and the average value of U e remains unchanged at a certain i L i fb is the periodic variation of i fb the output output current current of of the the boost boost converter converter which which feeds feeds back back the the extra extra energy energy to to the the SCESS, SCESS, and and iifb by the periodic variation of iL , and the average value ofback Ue remains unchanged atthe a certain iLand value. fb the output current of the boost converter which feeds the extra energy to SCESS, i increases with the increasing of the discharging power of the cascaded converter. The PWM increases with the increasing of the discharging power of the cascaded converter. The PWM ifb is the output current of the boost converter which feeds back the energy to the SCESS, and ifb increases increasing of the discharging power the extra cascaded converter. The PWM waveform is drive of converter and duty of increases with the waveformwith is the thethe drive of the the boost boost converter and the the dutyofcycle cycle of the the PWM PWM increases with the increases with the increasing of the discharging power of the cascaded converter. The PWM waveform waveform drive of the boost converter and duty of cycle of the PWM increases while the decreases with the increase iiLL.. The initial voltages of SCs are increase iiLL,, the while the frequency frequency decreases with thethe increase of The initial voltages of the thewith SCs the are increase of of is is the drive of the boost converter and the duty cycle of the PWM increases with the increase ofare iL , Lu , while the frequency with increase of i L. The initial voltages of the SCs increase i SC1 = 2.6of V, SC2 = 2.4 V, and u SC3 = decreases 2.2 V, and E sci (ithe = 1,2,3) represents the errors between the voltages u uSC1 = 2.6 V, uSC2 = 2.4 V, and uSC3 = 2.2 V, and Esci (i = 1,2,3) represents the errors between the voltages while the frequency decreases with the increase of i . The initial voltages of the SCs are u = 2.6 V, L1,2,3) represents = 2.6 V, uthe SC2 average = 2.4 V, and uSC3 =When 2.2 V, the andSCESS Esci (i = reaches the errors voltages uof =0 (ithe =SC1 1,2,3). As and voltage. the state, E sci =0 (i = 1,2,3). As ofSC1SCs SCs and the average voltage. When the SCESS reaches the balanced balanced state,between Esci uSC2 = 2.4 V,the andaverage uSC3 = 2.2 V, and Esci (ithe = 1,2,3) representsthe thebalanced errors between voltages of SCs sci =0 (i i= 1,2,3). of SCs and voltage. When state, current Ethe shown in 23d, balancing time 300 with As shown in Figure Figure 23d, the the balancing time is isSCESS 300 ss reaches with the the average average inductor inductor current iLL = = 2A 2A .. As and the average voltage. When the SCESS reaches the balanced state, E =0 (i = 1,2,3). As shown sci .. As shown in Figure 23d, the the balancing balancing time time isis 220 300 ss with with the theaverage averageinductor inductorcurrent current i iL==3.1A 2A As shown in Figure 23e, L . As shown in Figure 23e, the balancing time is 220 s with the average inductor current iL =shown 3.1A in in Figure 23d, the balancing time is 300 s with the average inductor current iL = 2A. As As shown in Figure 23e, the the balancing balancing time time isis 320 220 ss with with the theaverage averageinductor inductorcurrent current i iL==3.6A 3.1A. .The shown in Figure 23f, L . The shown in Figure 23f, the balancing time is 320 s with the average inductor current i = 3.6A Figure 23e, the balancing time is 220 s with the average inductor current iL = 3.1A. LAs shown in shown in Figure 23f, speed the balancing time is the 320 s with the average inductor current iL = 3.6A .ifThe maximum maximum balancing balancing speed is is reached reached near near the ideal ideal output output current current of of the the cascaded cascaded converter; converter; if the the maximum balancing is reached near the ideal output current ofspeed. the cascaded if the output is large too it reduce the So, control output current current is too toospeed large or or too small, small, it will will reduce the balancing balancing speed. So, the the converter; control strategy strategy output current is too large or too small, it will reduce the balancing speed. So, the control strategy
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Figure 23f, the balancing time is 320 s with the average inductor current iL = 3.6A. The maximum balancing is PEER reached near the ideal output current of the cascaded converter; if the output Energies 2018,speed 11, x FOR REVIEW 19 of 24 current is too large or too small, it will reduce the balancing speed. So, the control strategy based on based on the discharging maximum power discharging powerconverter of the boost converter will achieve the maximum the maximum of the boost will achieve the maximum balancing speed of balancing speed of the proposed topology. the proposed topology. iL
PWM(5V/div)
eSC1
eSC 2 eSC 3
i fb
Ue
U e (2V/div) iL (2A/div) i fb (1A/div) 5μs/div
eSC1 eSC 2 eSC 3 (67mV/div)
(a)
50s/div
(d) PWM(5V/div)
iL
eSC1
eSC 2 eSC 3
i fb
Ue
U e (2V/div) iL (2A/div) i fb (1A/div) 5μs/div
eSC1 eSC 2 eSC 3 (67mV/div)
(b)
50s/div
(e) PWM(5V/div)
eSC1
iL
i fb
eSC 2 eSC 3
Ue U e (2V/div) iL (2A/div) i fb (1A/div) 5μs/div
(c)
eSC1 eSC 2 eSC 3 (67mV/div)
50s/div
(f)
Figure 23. 23. The main waveforms of the boost boost converter converter and the the balancing balancing time. time. (a)–(c) are the main waveforms of of the theboost boostconverter converterwith with22A, A,3.1 3.1A, A,and and3.6 3.6AAaverage averageinput inputcurrent, current, respectively. (d)– waveforms respectively. (d)–(f) (f) are corresponding balancing time. are thethe corresponding balancing time.
A comparative comparative experiment experiment is is conducted conducted to to compare compare the the balancing balancing speed speed and and round-trip round-trip energy energy A efficiency. As As shown shown in in Figure Figure 24a 24a [18], [18], the the fly-back fly-back converters converters which which are are powered powered by by the the SCESS SCESS with with efficiency. 10 A output current to charge the lower voltage SCs are used as the charge-type balancing topology. 10 A output current to charge the lower voltage SCs are used as the charge-type balancing topology. As shown shownin inFigure Figure24b 24b[22], [22],the the0.25 0.25ΩΩ5050 resistor is used to discharge higher voltage SCthe in As WW resistor is used to discharge thethe higher voltage SC in the switched resistance balancing topology. The SCESS consists of three SCs with the voltages uSC1 = switched resistance balancing topology. The SCESS consists of three SCs with the voltages uSC1 = 2.6 V, 2.6 V, uSC2 = 2.3 V, and uSC3 = 2.3 V. The balancing time is shown in Figure 25 and the experimental uSC2 = 2.3 V, and uSC3 = 2.3 V. The balancing time is shown in Figure 25 and the experimental results results are shown in Table 2. are shown in Table 2.
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TT11 **
RR11
D11 D ++
SC11 SC
SS11
**
TT22 **
**
SS33
SS11
--
RR22 ++
SC22 SC
--
**
TT33
++
D22 D SC22 SC
SS22
SC11 SC
--
++
SS22
--
RR33 D33 D ++ --
SC33 SC
SC33 SC
SS33
++ --
**
(a) (a)
(b) (b)
Figure 24. Chargeand anddischarge discharge type balancing topology used in comparative experiment. Figure 24. 24. Charge Charge and discharge type balancing topology used in the thethe comparative experiment. (a) Figure type balancing topology used in comparative experiment. (a) (a) Charge type in [18]. Discharge type in [22]. Charge type in [18]. [18]. (b)(b) Discharge type in [22]. [22]. Charge type in (b) Discharge type in
eeSCSC11
eeSCSC11
eeSCSC11
eeSCSC22 eeSCSC33
eeSCSC22 eeSCSC33
eeSCSC22
(0.1V/div) 100s/div eeSCSC11 eeSCSC22 eeSCSC33(0.1V/div) 100s/div
eeSCSC33
(0.1V/div) eeSCSC11 eeSCSC22 eeSCSC33 (0.1V/div)
(a) (a)
100s/div 100s/div
(0.1V/div) 100s/div eeSCSC11 eeSCSC22 eeSCSC33 (0.1V/div) 100s/div
(c) (c)
(b) (b)
Figure 25. 25. The Thebalancing balancingtime timeofof of the comparative experiment. (a) Proposed modularized dischargeFigure 25. The balancing time the comparative experiment. Proposed modularized dischargeFigure the comparative experiment. (a)(a) Proposed modularized discharge-type type topology. (b) Charge-type balancing topology. (c) Switched resistor method. type topology. (b) Charge-type balancing topology. (c) Switched resistor method. topology. (b) Charge-type balancing topology. (c) Switched resistor method. Table 2. 2. The The experiment experiment results. results. Table Table 2. The experiment results. Voltage after after Balancing Balancing Voltage
Balancing Time Time Balancing
Methods Methods Methods
Voltage afteruuBalancing uend end end
Balancing ttbbTime tb
Proposedmethod method Proposed method Proposed Charge-type method Charge-type method Charge-type method Switched resistor method Switched resistor method Switched resistor method
2.38 2.38V V 2.38 V 2.36 V 2.36 V 2.36 V 2.30 V 2.30 V V 2.30
200 200sss 200 340 340 340 sss 220 s
220 ss 220
Round-Trip Energy Energy Efficiency Efficiency Round-Trip
Round-Trip Energy ηη Efficiency η 68.15% 68.15% 68.15% 39.12% 39.12% 39.12% 0
00
shown in Table 2. The time of charge-type topology is 340 s, The experiment experimentresults resultsare are shown in Table Table 2. balancing The balancing balancing time of charge-type charge-type topology The experiment results are shown in 2. The time of topology while the balancing time is 200 s of the proposed topology and 220 s of the switched resistor method. is 340 s, while the balancing time is 200 s of the proposed topology and 220 s of the switched resistor is 340 s, while the balancing time is 200 s of the proposed topology and 220 s of the switched resistor The proposed modularized discharge-type topology has the fastest balancing speed andspeed the balancing method. The proposed proposed modularized discharge-type topology has the the fastest balancing balancing speed and the the method. The modularized discharge-type topology has fastest and speed of the switched resistor method is close to theis However, the 0.25 Ω 50 W balancing speed of the the switched resistor method isproposed close to totopology. the proposed proposed topology. However, balancing speed of switched resistor method close the topology. However, resistor has size and energy efficiency is efficiency zero because thebecause extra energy is the 0.25 0.25 Ω Ω 50 50aW Wbig resistor has aathe biground-trip size and and the the round-trip energy efficiency is zero zero because the extra extra the resistor has big size round-trip energy is the dissipated in the form heat. round-trip energy efficiency of the charge-type method ismethod higher energy is is dissipated dissipated inof the formThe of heat. heat. The round-trip round-trip energy efficiency efficiency of the the charge-type charge-type method energy in the form of The energy of than the switched resistor method lower than thethan proposed topology. This experiment proved is higher higher than the the switched switched resistorbut method but lower than the proposed proposed topology. This experiment experiment is than resistor method but lower the topology. This that the that proposed modularized discharge-type topology has an excellent discharging proved that the the proposed proposed modularized discharge-type topology has an an excellent excellentperformance. discharging proved modularized discharge-type topology has discharging The balancingThe speed is fasterspeed and the round-trip energy efficiency is higher than charge-type performance. The balancing speed is faster faster and the the round-trip energy efficiency is the higher than the the performance. balancing is and round-trip energy efficiency is higher than balancing topology and the switched resistor method when the voltage of an SC is much higher than charge-type balancing topology and the switched resistor method when the voltage of an SC is much charge-type balancing topology and the switched resistor method when the voltage of an SC is much the average voltage. higher than the the average average voltage. voltage. higher than There are excellent balancing topologies; however, however, most most of of them them are designed for are many many other other excellent excellent balancing balancing topologies; are designed designed for There the BESS with a small balancing current. Few papers discussed the round-trip energy efficiency BESS with a small balancing current. the BESS Few papers discussed the round-trip energy efficiency of the equalizer equalizer for for BESS, BESS, because because the the round-trip round-trip energy energy efficiency efficiency for for BESS BESS is is difficult difficult to to calculate calculate or or the measure. Fortunately, Fortunately, the the efficiency efficiency of of many many topologies topologies is is given. given. ItIt will will be be interesting interesting to to compare compare the the measure.
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the equalizer for BESS, because the round-trip energy efficiency for BESS is difficult to calculate or measure. Fortunately, the efficiency of many topologies is given. It will be interesting to compare the proposed balancing topology with the conventional ones and the comparison results are summed as Table 3. In Table 3, five index parameters are employed to evaluate the balancing performances, which are the discharging current (P1 ), average efficiency of converter (P2 ), voltage stress (P3 ), number of circuit components (P4 ), and control degree of freedom (P5 ). The discharging current (P1 ) refers to the balancing speed and the desired balancing speed of SCESS is described in (1). The average efficiency of the converter (P2 ) reflects the round-trip energy efficiency; generally, high efficiency of a converter will result in a high round-trip energy efficiency. The voltage stress (P3 ) refers to the voltage stress of the switches or diodes which have the largest number in the balancing system. The number of circuit components (P4 ) represents the hardware cost. The control degree of freedom (P5 ) refers to the control ability of SC’s voltage or state of charge (SOC), which is evaluated by “high (refer to each SC’s voltage can be controlled)” and “low (refer to the voltages of SCs are automatic balanced which can’t be controlled)”. Table 3. Comparison of the proposed balancing topology with the conventional ones. Topologies
Type
P1
P2
P3
P4
P5
Bidirectional DC/DC converters [11]
Ideal
0.9 A
η
24 V
≥4N + 1
high
Multi-winding transformer [7] Multi-winding transformer [9] Buck/boost converter [13] Switched capacitor [14] Switched capacitor [15]
Quasi ideal
0.5 A
