A New CMOS Switch Linearization Technique For Multi-Site Measurement Applications Sara Catal˜ao1 , Tiago Costa2 , Mois´es S. Piedade3 , Jorge R. Fernandes4 Electrical and Computer Engineering Department Instituto Superior T´ecnico 1049 Lisboa, Portugal Email: 1
[email protected], 2
[email protected], {3 msp, 4 jorge.fernandes}@inesc-id.pt
Abstract—This paper proposes a new linearization technique for high-performance switches, by actively controlling the switch voltage drop. This technique is suited for multi-site measurement applications which require a constant current for resistive sensor variation measurement, where other techniques such as bulkswitching or clock-bootstrapping are not the best choice. For NMOS, PMOS and CMOS switches, the proposed technique can achieve a reduction factor of the on-resistance variation of 15.8, 1.8 and 7.2, while supporting wide range input signals, and with minor area and power penalization if a multi-site measurement system is considered. The system is designed using AMS 0.35 µm 3.3 V technology.
I. I NTRODUCTION Nanotechnology advances are enabling the fabrication of a great variety of nanosensors that can be used for biological detection and environmental applications [1], [2], [3]. In order to extract the measurement data from the sensors one needs to implement a SoC measurement circuit that successfully converts the sensor’s feature variation to a voltage or current variation. Typical architectures for the measurement system are often organized in a matrix form [1], [2], where the sensors are addressed by switches. If the sensor is resistive, the measurement is made by means of a constant current flowing through the switch and the sensor in order to read the sensor’s voltage difference. Therefore, it is of most importance that the switch on-resistance (RSW ) stays constant so not to interfere with the measurements. Since switches are typically implemented by MOS transistors, its conductance varies with the switch input signal, which highly degrades the measurement accuracy. It is therefore necessary to linearize the MOS switch input-output characteristic so that its on resistance variation is minimized. Several techniques have been proposed to successfully address the switches non-linearity problem, such as bulk-switching [4] and clock-bootstrapping [5]. These techniques aim to preserve voltage difference across the switch, and are commonly used in sampled data systems, such as switched-capacitor analogto-digital converters (ADC) and analog filters. However, the aforementioned techniques are not suited to deal with resistive sensors continuous measurement requirements. This work was partially financed by the Portuguese Foundation for Science and Technology - FCT Project PTDC/EEA-ELC/108555/2008 and FCT Project PTDC/EEA-ELC/68972/2006
Fig. 1.
multi-site measurement system
This paper addresses the switch non-linearity issue by proposing a new technique for switch linearization that is suited for applications with continuous measurements of resistive sensors. This paper is organized as follows: Section II describes the relevant existing switch linearization methods. Section III presents the proposed technique. Section IV describes the system analog design and in Section V simulation results are addressed. Section VI draws the main conclusions. II. OVERVIEW OF R ELEVANT L INEARIZATION T ECHNIQUES A. Standard CMOS Switches Standard switches are commonly implemented by transmission gates, which consist of a parallel connection between an NMOS and a PMOS transistor. CMOS switches are normally preferred to single NMOS or PMOS switches, since they allow full input signal swing, which is not possible in the NMOS or PMOS case. Although being more linear, when used in lowvoltage applications CMOS switches exhibit a highly variable resistance, which causes a high harmonic distortion in sampled
signals, and an inaccurate measurement when to address a sensor. B. Techniques for switch linearization The two most common techniques in sampled data applications to reduce the switch on-resistance variation are the bulk-switching and the clock-bootstrapping techniques. The bulk-switching technique is used to limit and reduce the variation of the switch RSW , by controlling its bulk voltage. When it is ON, the PMOS bulk is connected to its source with the purpose of reducing the body effect and improving its conductance. In the OFF state the PMOS bulk is connected to VDD, increasing the threshold voltage and consequently the off-resistance [4]. The main problem of this technique is related to low level of the linearity improvement, and the degradation of its performance with high-frequency input signals [6]. For the clock-bootstrapping technique, the procedure is different: for the NMOS switch, in the OFF state a bootstrap capacitor is charged to VDD. Then, in the ON state, this capacitor will act as a floating source in series with the input signal making the gate voltage of the switch equal to VDD+Vin. For the PMOS switch, the complementary situation happens: the gate voltage is reduced to Vin-VDD when the input voltage is near VSS [5]. Despite improving the switch linearity, this technique has the disadvantage of exposing the switches to an overstress of its gate capacitances which causes potential long-term oxide reliability problems [6]. Although the described techniques successfully achieve an improvement in the linearity of switches in sampled data systems, by decreasing the variation of its RSW for the input signal full-range, they are not suitable for applications which require continuous measurements of addressable resistive sensors (Fig. 1). In this type of applications, there is typically a constant current flowing through the sensor, which is addressed by a switch in series. If the clock-bootstrapping technique is used, some portion of the current will be lost during the charge of the bootstrap capacitor, and subsequently, the sensor’s current will be unreliable. Considering the bulkswitching technique, and depending on the desired resolution of the measurement system, the level of linearity improvement can still be insufficient in order to obtain an accurate result from the sensor. III.
PROPOSED SWITCH LINEARIZATION TECHNIQUE
A. Architecture The proposed switch linearization architecture is presented in Fig. 2, where the switch is implemented by an NMOS transistor. In order to decrease the variation of the switch RSW , an opamp with an induced offset voltage (VOS ) is purposely added to the switch terminals. The VOS of the opamp is the voltage that when applied to the opamp input terminals generate a 0 V output voltage, and its generation is explained in chapter IV. The inverting (Vin ) and non-inverting (Vip ) inputs of the opamp connect to the source and drain of the switch, respectively, and the opamp output is connected to
Fig. 2.
Proposed switch linearization technique
switch’s gate. The output voltage of the opamp (VO ) is then given by (1). VO = (Vip − Vin + VOS ).G
(1)
where G is the opamp gain. The negative feedback performed by the amplifier has the purpose of finding a point in its inputoutput characteristic, in which, for the same current (ISens ), the drain-source voltage (VSW ) of the switch is equal to the VOS of the opamp, leading to a RSW given by (2). For the condition in (2), if the current that is flowing through the sensor is constant, and the VOS of the opamp is well defined (even if not completely predictable), one can assure that, theoretically, RSW is constant, and consequently, only the sensor’s resistance variation will be read. In practice, there is a minor RSW variation due to circuit non-idealities, as will be shown in section V. The previous analysis can also be made for a PMOS or a CMOS switch. RSW =
Vin − Vip VOS = ISens ISens
(2)
B. Block Diagram For a better understanding of this technique, the block diagram of the circuit on Fig. 2, is present on Fig. 3. In this figure, it can be observed that the opamp compares the actual value of the drop switch voltage (VSW actual ) with the desired drop voltage (VSW desired - which is the VOS of the opamp) and, then, the difference obtained is multiplied by G: VG = (VSW desired − VSW actual ).G
(3)
Afterwards, the opamp output voltage is applied to the switch’s gate. Assuming a constant ISens , the switch converts
Fig. 3.
Proposed technique block diagram
Fig. 4.
Proposed technique within a resistive sensor measurement application
1 ISens + | Vtn | + VSW (8) W 2 KN VSW L Where KN is the NMOS gain factor, VSW is the switch drop voltage (the NMOS drain to source voltage) and Vtn its threshold voltage. In order to intersect both characteristics, it is necessary to make the opamp characteristic dependent on the switch VGS : VGS =
VGS = (VO − Vin ) = G.(VSW + VOS ) − Vin
Fig. 5.
Relation between the switch and the opamp characteristics
the voltage applied to its gate into a variation in its RSW , which implies a variation in the VSW actual , in order to get it closer to the desired value. This dependence can be written in terms of G∗ (this parameter includes the gain introduced by the opamp and the voltage to resistance converter gain): VSW actual = (VSW desired − VSW actual ).G∗
(4)
Equation (4) can also be written as: RSW actual = (RSW desired − RSW actual ).G∗
(5)
From (5) it can be seen that greater G* means less error (6). ∆RSW |G∗ →∝ =
RSW actual =0 ∝
(6)
C. Transistor Level Analysis After the general study about this feedback topology, the combination of the opamp input-output characteristic and the switch current-voltage characteristic is discussed. The characteristics of the opamp and switch (in triode region) are given by (7) and (8), respectively. VO = (VSW − VOS ).G
(7)
(9)
The VSW in (8) and (9) is swept and the VGS values obtained from the two expressions are compared through Fig. 5, which shows the results obtained for a switch composed by a NMOS with W/L= 200 and an opamp with the following characteristics: Vin = 1 V and VOS = 89 mV. Analysing Fig. 5, it can be observed that, for a constant VSW , if ISens increases, a greater VGS will be necessary to enable the switch to remain at the same VSW . Furthermore, it can also be seen that the variation of the VSW , i.e., the RSW variation, depends on G (for a greater G, the RSW will be lower), which is in accordance with 6. D. Switch Linearization Technique in a Multi-Site Measurement System The proposed switch linearization technique is to be used in multi-site measurement systems. Since the switch is used to address sensors, one needs to understand how is the switch turned on and off. That procedure is present in Fig. 4, where, for simplicity, only the column switches of the sensor matrix of Fig. 1 are present, along with the proposed linearization technique. In Fig 4 the column switches are implemented with NMOS transistors since they are close to the GND levels. For the same criteria, the row switches are implemented with PMOS transistors. Although CMOS switches could also be used, that would depend on the expected sensor resistance variation. The columns addressing works as follows: assuming that column 1 is addressed, the signal C1 is high. This way, M 1c1 is cutoff and the opamp output is connected to the gate of the NMOS switch SWc1 through M 2c1 , so that the opamp can control SWc1 ’s drop voltage. If column 1 is not addressed, then signal C1 is low. Therefore, M 1c1 pulls the gate voltage of SWc1 to ground in order to turn it off. Another valuable feature of this topology is that, since the
Fig. 7. Fig. 6.
VOS variation with differential pair transistors width ratio
Two-stage opamp
sensors are read one by one by addressing all cells of the matrix with column and row decoders, one opamp can be shared for all rows and another opamp for all columns, leading to power and area savings. For the columns, this is accomplished by means of transistors M 3c1...n , as present on Fig. 4. This transistors guarantee that when a column is selected, the opamp’s noninverting input is only connected to the corresponding column switch so that it can control its drop voltage. For the rows, the equivalent procedure is performed.
matched differential pair. The theoretical relationship between the input offset voltage and W/L dimensions of the differential pair transistors can be obtained through (10) and (11). (10) shows the relation between the opamp’s input terminals and the switch drop voltage VSW , while (11) simply represents the characteristic of a PMOS in the saturation region. By combining (10) and (11), the equation relating VSW and the differential pair transistors dimensions is obtained in (12). VSW = Vip − Vin = VSG2 − VSG3 ID1,2 =
IV. O PAMP A NALOG D ESIGN The proposed architecture uses an opamp with and induced offset voltage in order to control de variation of the switch’s RSW . In order to determine the best opamp topology that suits this application, it is necessary to establish the opamp requirements. Firstly, it should have a high output voltage swing in order to support large VSW variations. It should also have high gain since, as it was shown by (6), the greater the opamp gain, the less RSW varies. It should also have low noise in order to minimize the opamp interference with the sensor measurement. In terms of bandwidth, since biological and environmental sensors typically have only low frequency content, the opamp does not need to support high frequency operation. With this requirements, the topology chosen for the opamp was the Two-Stage topology, because it has high output voltage swing, high gain, and only a few transistors that contribute to the total opamp noise. The two-stage opamp is present on Fig. 6. The choice for the type of MOS transistors used in the input differential pair is related to the commom mode voltage levels that the switch sees in its terminals. If the switch is closed to VDD , the opamp input transistors should be NMOS. On the contrary, if the switch is closed to GND, the opamp input transistors should be PMOS. The design of the input transistors is performed by taking in consideration the input offset voltage. The natural input offset voltage of a differential pair results from mistmatches. Therefore, the first stage of the opamp is composed of a mis-
KP 2
(
W L
)
(
VSG1,2 − Vtp
(10) )2
(11)
1,2
v v u u 2 u ID2 ID5 − ID2 −u VSW = VOS = (12) t W KP t W L2 L3 From (12) it can be concluded that for a given bias current ID5 , by unbalancing the W/L ratios of the differential pair transistors, the VOS will be non-zero and can be tuned to have a specific value. The variation of the opamp VOS with the unbalancing ratio of the differential pair input transistors can be seen in Fig. 7. The current ID5 is 20µA and the L of both the differential pair input transistors is 1 µm. From Fig 7 it is observed that the slope of the differential pair graph with higher Wmin is lower. This means that for the same change in the relation W1 /W2 , an higher variation in the VOS will be observed in the differential pair with the lower Wmin . Thus, it is better to choose the differential pair with higher Wmin . The remaining transistor’s dimension are chosen in order to guarantee an high gain and low noise ([4]) for a given bias current, without compromising the output excursion. √
V. S IMULATION R ESULTS A. Opamp simulation Results In this section the opamp simulation results are depicted. Firstly, in order to assess the induced VOS behaviour, a Monte Carlo analysis is performed to allow the observation of the VOS variation with the technology process and mismatch
TABLE I O PAMP SIMULATION RESULTS Parameter DC Gain Unity Gain Frequency Phase Margin PSRR (10 Hz - 1 kHz) Noise (1 kHz) THD (10 mV input) Input offset voltage Output Voltage Swing Total Bias Current Supply Voltage
Simulation Result 69.5 dB 3.3 MHz 85.2 deg. ≥ 40dB √ 18nV / Hz 0.97% ≈ 85mV 1.7 mV to 3.3 V 174 µA 3.3 V
variation. The results are present on Fig. 8, where the VOS is the opamp differential input voltage when the opamp output is at mid supply (1.65 V). As it can be observed, there is a variation of about 10 mV in the VOS of the opamp. However, the specific value of VOS is not relevant for this technique to work properly, since the requirement is that the VOS stays constant throughout the sensor measurement in order to guarantee that the voltage that is read is only due to the sensor’s resistance variation, and not switch RSW variation. In Tab. I are present the simulated characteristics of the opamp of Fig. 6. B. Proposed Technique Simulation Results In order to evaluate the proposed technique, the test circuit of Fig. 9 is used, for NMOS, PMOS and CMOS switches (the opamp used in the feedback topology has been designed to have a VOS of about 85 mV for the NMOS switch and 100 mV for the PMOS and CMOS switch, and the current ISens is equal to 1 mA). The Vin is swept, in order to analyse the RSW variation. In order to compare the proposed technique with the switches without feedback, the opamp was designed to have an enable port, which, when low, the opamp applies VDD or GND at the gate of NMOS or PMOS switches, respectively. The results for an NMOS switch are presented on Fig. 10
Fig. 8.
VOS variation in Monte Carlo analysis
Fig. 9.
Test circuit for the proposed topology
(similar results can be obtained for a PMOS switch). In Fig. 10 can be observed that the feedback topology introduced into the switch is advantageous. However, the switches being in the linear region is not the only condition for the opamp to control the switch RSW . The opamp starts compensating the switch RSW variation only after its value is near VOS /ISens . This is, before this point, the RSW variation is similar to the one without feedback. For this reason, the switch size should ensure a minimum RSW (when analysed without feedback) lower than the RSW value guaranteed by the feedback system (VOS /ISens ). Despite the switch with the feedback topology still shows a little variation, the results are improved compared with the ones obtained without feedback (as shown on Tab.II). Furthermore, it can be concluded that the input voltage range in which the RSW variation can be compensated is directly proportional to the W/L dimension of the switch. An analysis is also performed in order to study the variation of the RSW of the switch with its current (Fig. 11, for a PMOS switch). For a ten times smaller current, the RSW will be ten times greater, because the VOS of the opamp remains the same (about 100 mV) and RSW = VOS /ISens . Another conclusion that can be drawn is the fact that, for a lower current, the input voltage
Fig. 10.
NMOS switch RSW variation with input signal
TABLE II RSW
VARIATION FOR
Single NMOS 200 150 100 50
NMOS, PMOS
AND
CMOS
Width [µm] (L = 1 µm) Single PMOS CMOS - NMOS 400 94.5 200 81 150 67 125 54
SWITCHES , WITH AND WITHOUT THE PROPOSED TECHNIQUE
CMOS - PMOS 350 300 250 200
Rsw Variation [%] (with / without technique) Single NMOS Single PMOS CMOS 4.1 / 136.8 7.3 / 108.7 6.9 / 45.3 3.9 / 119.9 6.7 / 51.3 6.7 / 44.9 3.4 / 89.8 5.7 / 24.1 6.5 / 45.6 1.8 / 28.7 4.0 / 7.3 6.2 / 44.8
are considered, the RSW variation reduction factor, when compared to the switch without the proposed technique, is 15.9 for the single NMOS switch, 1.8 for the single PMOS switch and 7.2 for the CMOS switch. If the proposed topology is used in a matrix system, in which the switches are used to select matrix cells, the amplifier can be shared for all the rows or columns. Therefore, the area penalization for using this technique is minimum. VI. C ONCLUSION
Fig. 11.
PMOS switch RSW variation dependence of the switch current
range in which the RSW variation can be compensated is bigger, which is advantageous for low power applications. The RSW variation with the input signal for a CMOS switch was also simulated, and the results can be found on Fig. 12. It can be seen that the CMOS switch supports a greater input signal swing when compared to the single NMOS or single PMOS switch, as expected. In Tab.II, it is present the RSW variation with and without the proposed technique, listed for different switch widths (fixed length of 1µm). For the results in Tab.II it was only considered the input voltage switch range in which the opamp is able to controls the switch’s VSW . It can be seen that the proposed technique highly enhances the linearity of the switches: If only the best results for each type of switch
Fig. 12.
RSW variation with the input signal for the CMOS switch
This paper presented a linearization technique for switches used in systems which require continuous measurements of addressable constant current resistive sensors where other existing techniques are not suitable, such as multi-site measurement systems for biomedical and environmental applications. It has been shown that, with the proposed topology, an NMOS, a PMOS and a CMOS switch can have a RSW variation reduction factor of 15.9, 1.8 and 7.2 respectively, when compared to the same switches without the proposed technique. While CMOS switches support a much greater input signal range, the single transistor switches input signal range can be configured by changing the current passing through the switch. The proposed technique area and power penalization is minor since in a multi-site measurement system organized in a matrix form, only two opamps are needed to control the RSW variation of all the rows and column switches, which makes the proposed technique suitable for multi-site measurement systems with a large number of resistive sensors. R EFERENCES [1] P. Lopes, J. Germano, T. de Almeida, L. Sousa, M. Piedade, F. Cardoso, H. Ferreira, and P. Freitas, “Measuring and extraction of biological information on new handheld biochip-based microsystem,” Instrumentation and Measurement, IEEE Transactions on, vol. 59, no. 1, pp. 56 –62, jan. 2010. [2] O. Geschke, H. Klank, and P. Telleman, Microsystems Engineering of Lab-on-a-Chip Devices. Wiley-VCH, 2004. [3] J. Germano, M. S. Piedade, L. Sousa, T. M. Almeida, P. Lopes, F. A. Cardoso, H. A. Ferreira, and P. P. Freitas, “Microsystem for biological analysis based on magnetoresistive sensing,” XVIII IMEKO WORLD CONGRESS, September 2006. [4] R. Geiger, P. Allen, and N. Strader, VLSI design techniques for analog and digital circuits, I. Edition, Ed. McGraw-Hill, 1990. [5] C.-Y. Yang and C.-C. Hung, “A low-voltage low-distortion mos sampling switch,” in Proc. IEEE International Symposium on Circuits and Systems ISCAS 2005, May 23–26, 2005, pp. 3131–3134. [6] A. Galhardo, J. Goes, and N. Paulino, “Novel linearization technique for low-distortion high-swing cmos switches with improved reliability,” in Proc. IEEE International Symposium on Circuits and Systems ISCAS, 2006.
