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A New Linearization Technique for CMOS RF Mixer Using Third-Order Transconductance Cancellation Kung-Hao Liang, Student Member, IEEE, Chi-Hsein Lin, Student Member, IEEE, Hong-Yeh Chang, Member, IEEE, and Yi-Jen Chan, Senior Member, IEEE
Abstract—A new third-order transconductance ( 3 ) cancellation technique is proposed and applied to a conventional radio frequency (RF) mixer for improving circuit linearity. The bulk-tosource voltage is applied to adjust the peak value position of 3. The cancellation of 3 is utilized by a negative peak 3 transistor combined in parallel with a positive peak 3 transistor. For a single device, the measured adjacent channel power ratio (ACPR) and third-order intermodulation (IMD3) distortion are both improved over 15 dB. A Gilbert-cell mixer in commercial 0.18- m CMOS process was designed using the proposed method to further evaluate the linearity. The compensated 3 device is placed in the input RF gm-stage and then reducing the principle nonlinearity source of the mixer. From the experiment results, the ACPR and IMD3 of the mixer are improved about 10 and 15 dB, respectively. Index Terms—CMOS, harmonic, third-order intermodulation (IMD3), intermodulation, linearization, mixer, third-order transconductance.
can be further adjusted to enhance the linearity of the device. are combined to The transistors with negative and positive region, and the overall of the parallel conget a flat nection of transistors will be close to zero. In the operation recan be cancelled, and gion, the nonlinear characteristics of the intermodulation distortion of the device will also be further reduced without additional dc power consumption due to the proposed topology. To evaluate the linearization technique, a Gilbert-cell mixer based on the proposed method has been successfully demonstrated. Also, the proposed mixer is very suitable for the applications of the high linearity transceivers due to its superior linearity, conversion gain and bandwidth. II. LINEARIZATION METHOD AND MIXER DESIGN The drain current of a common-source MOSFET can be expressed by using a Taylor series expansion as follows: (1)
I. INTRODUCTION IGH linearity transceivers are essential for high data rate communication systems due to the requirement of signal-to-noise ratio (SNR), especially for high-level modulation schemes, such as orthogonal frequency division multiplexing signals. In general, the linearity of the transceiver is dominated by mixers and power amplifiers [1]. Therefore, a mixer with good linearity is desired to further enhance the SNR of the RF output signal. Gilbert-cell mixers are widely used as the down-converter in CMOS transceivers, since they are broadband with good conversion gain [2]. So far, few linearization techniques have been proposed using CMOS processes for the RF mixer applications [3]–[6]. The linearity was improved to various degrees by using these techniques, but they made the circuits more complex with additional dc power consumption and cost. In this letter, an innovative linearization method using a cancellation technique is proposed. A common-source transistor to adjust threshold is applied to bulk-to-source voltage of the device, and also the characteristic of voltage
H
Manuscript received October 1, 2007; revised January 29, 2008. This work was supported in part by the National Science Council of Taiwan, R.O.C., under Grants NSC 96-2221-E-008-117-MY3, NSC 96–2221–E-008–119–MY3, and NSC 96-2628-E-008-073-MY3 and by the Taiwan Semiconductor Manufacturing Company through the Chip Implementation Center (CIC) of Taiwan. The authors are with the Department of Electrical Engineering, National Central University, Jhongli 32001, Taiwan, R.O.C. (e-mail:
[email protected]. tw). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LMWC.2008.922129
is gate-to-source voltage, and represents the where -order transconductance. The third-order coefficient performs an important role in the third-order intermodulation distortion of an amplifier [7]. Assuming the drain is shorted at the signal frequency, the third-order intercept point (IP3) of gate voltage amplitude can be given as follows [8] (2) As can be observed, the IP3 of the device can be improved effectively. A TSMC 0.18- m 1P6M CMOS by reducing technology is used to evaluate the characteristic. Fig. 1 shows , 2 and characteristics versus gate-tothe measured source voltage with a fixed drain-to-source voltage of 1.8 V. The gate width of the NMOS device is 2.5 m with 35 fingers. The has a positive peak value at the gate voltage of 0.45 V, and it will be close to zero near the threshold voltage. The amplifier is usually operated in the range of 0.6 and 0.8 V for high voltage usually has a negative peak value in or power gain, but the this bias region, and also the linearity of the circuit is degraded. is the third-order derivative of the drain current Since the can be adjusted by versus gate bias, the characteristic of of 2.5 m varying the threshold voltage. The measured gate-width 15 and 20 finger transistors is shown in Fig. 2. The bulk-to-source voltage is 1 V applied to 37.5- m gate-width device; the bulk-to-source voltage of the 50- m gate-width device is 0 V. The solid circle-symbol curve shows the compensawith a total gate-width of 87.5 m. Because tion result of are not symmetrical, the the positive and negative values of different sizes of the two transistors are selected to obtain a flat
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LIANG et al.: NEW LINEARIZATION TECHNIQUE FOR CMOS RF MIXER
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Fig. 1. Measured g , g and g characteristics of two transistors of 15 and 20 fingers in parallel with a unit gate width of 2.5 m. Fig. 3. Schematics of the proposed highly linear RF mixer.
Fig. 2. Measured g sistors.
compensation results of two connected in parallel tran-
region with approximately equal to zero. By canceling the , the linearity of device can be nonlinear characteristics of further enhanced. The proposed method is applied to a Gilbert-cell mixer as shown in Fig. 3. The mixer consists of four major parts: and ), switching stage transconductance stage ( , output load ( and ) and output buffers and ). The transconductance stage performs as a ( voltage-to-current converter, and the device is essentially biased in the active region to achieve high conversion gain with low noise figure. Most of the distortion in a mixer comes from the transconductance stage [9], and therefore the linearity of the mixer can be enhanced using a good linearity device for cancellation is the transconductance stage. The proposed applied to this circuit, and the gate widths of the parallel transistors are 2.5 m with 15 and 20 fingers, respectively. As shown region in Fig. 2, the transconductance stage can have a flat by supplying a bulk-to-source voltage to one of the transistors. The linearization method does not require additional power consumption, because the total gate width of the paralleled pair is equal to the original device size of transconductance stage are biased at near (i.e., 35 fingers). The transistors pinch-off region to act as switches and are controlled by the and are used to transfer LO signals. The output resistors intermediate frequency (IF) from current signals to voltage and perform signals. The common-source transistors as output buffers to achieve the impedance match for driving
Fig. 4. IIP3 comparison of the transistors with and without g V and V are biased at 1.8 and 0.65 V, respectively.
cancellation;
a 50- load [10]. An on-chip bypass capacitor is included and ground for the in-band bypass. between the III. EXPERIMENTAL RESULTS OF DEVICE AND MIXER Fig. 4 shows the measured fundamental output power and and ), and the IMD3 of the transconductance stage ( and the gate-to-source voltage drain-to-source voltage of the stage are 1.8 and 0.65 V, respectively. The measured IMD3 is improved about 18 dB from 48 to 66 dBc, and the input IP3 is also improved by 8 dB. The improvement of the IP3 is also evaluated using a third-order intermodulation formula, and the calculation is also close to the IP3 extracted result. A digital modulation (NADC) signal measured is also used to evaluate the linearity, and the measured result is shown in Fig. 5. Assuming channel bandwidth and spacing are both 48.6 kHz, the measured ACPR is enhanced by 15 dB with the proposal cancellation technique. The output signal is also demodulated using a HP 89441A vector signal analyzer at a center frequency of 2.4 GHz. Fig. 6 shows the chip photograph of the proposed mixer with a chip size of 0.72 0.93 mm , where the core area of the mixer is 0.2 0.26 mm . The chip was measured via on-wafer probing in the RF and LO input ports. The differential IF output signals are connected with an off-chip broadband balun via
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Fig. 5. Measured ACPR results of the transistors with and without cellation.
g
can-
Fig. 8. Measured ACPR results of the mixer at an IF frequency of 100 MHz.
are both improved by 10 dB. With and without the proposed cancellation, the measured conversion gain and noise figure are degraded by only 1.8 and 1.3 dB, respectively, and the dc power consumption is almost same for both conditions. IV. CONCLUSION
Fig. 6. Chip micrograph of the highly linear mixer with a chip size of 0.72 0.93 mm , and a core area of 0.2 0.26 mm .
2
Fig. 7 Comparison of measured IIP3 between with and without g tion for the mixer.
2
cancellation method is proposed in this letter, and A new it was also successfully demonstrated in a Gilbert-cell mixer. The proposed method is easily applied to RF and microwave circuit designs, and the linearity of the circuits can be highly improved without consuming extra dc power consumption and cost. In the future works, this technique will be utilized for the other RF building blocks, such as LNA and PA, in the transceiver to further enhance the linearity. REFERENCES
cancella-
bonding wires. For a fixed IF frequency of 100 MHz, the measured maximum conversion gain and noise figure are 11.2 dB and 13.8 dB, respectively. The port-to-port isolations (RF-IF, LO-IF and LO-RF) are better than 35 dB at 2.4 GHz. The dc is 2 V with a 7.4-mA drain current, and supply voltage of the stage is also 0.65 V. the gate-to-source voltage The measured input IP3 and ACPR of mixer are plotted in Fig. 7 and Fig. 8, respectively. The measured IIP3 and ACPR
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