Design of an LC filter for the PWM based inverter is very important issue. This filter should reduce the high frequency distortion of output voltage and control the.
2010 3rd International Conference on Power Electronics and Intelligent Transportation System
A New Design Procedure for Output LC Filter of Single Phase Inverters Ahmad Ale Ahmad, Student Member, IEEE, Adib Abrishamifar, Member, IEEE, Mohammad Farzi, IRIEE. switching frequency and its relation to the cut off frequency of filter is not well considered. Also, none of them were presented a straight forward method or relation to calculate the L and C values. This paper analyses the characteristics of the output LC filter for PWM inverter. The cut off frequency of filter and its relation to the modulation factor and switching frequency are determined to meet the IEEE Std. 1547 requirements for attenuating the harmonics distortion. Considering the switches current ripple, the inductance and capacitance value are calculated. The specifications and design criteria’s are illustrated in this paper. This procedure is verified with simulation results.
Abstract- This paper presents a new design procedure for output LC filter of single phase inverter. Two main goals of the procedure are to meet the IEEE Std. 1547 requirements for attenuating of harmonics distortion and to limit the high frequency current of switches in acceptable value. The design steps and their considerations are discussed comprehensively. This procedure is verified with simulation results for a 220V, 5KVA inverter. The simulations run either linear or nonlinear full loads. Keyword- Inverter, LC filter, cut off frequency, THD, inductor current ripple,
I. INTRODUCTION
II. LC FILTER ANALYSIS
Today, inverter with an output LC filter has an especial application such as distributed generation, active filter, stand-alone application based on renewable energy, uninterruptible power supply (UPS) and dynamic voltage restorers [1-3]. Two main duties of the output LC filter are to attenuate the output voltage ripple and to limit the high frequency ripple current of inverter switches. The attenuation of switching frequency voltage at the output node is depended on the cut off frequency of filter. Also, bandwidth of inverter controller is limited by the cut off frequency of the filter [3]. The cut off frequency of the filter have to be selected small for perfect voltage ripple attenuation, and the bandwidth of the controller have to be wide for fast response to step or nonlinear load. So, there is a trade off between the bandwidth of the controller and filter attenuation. After selecting the cut off frequency of filter, determining the L and C values is very important issue, because they affect on ripple current of inverter switches, the inverter output impedance [4], efficiency [4-5], transient response [3] and also the cost of the inverter. In [4-6], the cut off frequency of LC filter is designed based on the Fourier series of the inverter output voltage. Then by using the relation between the filter capacitor and the system time constant, the capacitor and inductor value are designed [4]. In [5], the L and C are selected to minimize the filter reactive power. Authors of [6] defined a cost function based on reactive power where the reactive power of inductor is weighted two times higher than the reactive power of capacitor, then calculating the L and C value to minimize this cost function. Other ones used the same method too, but the ripple current of inductor,
Design of an LC filter for the PWM based inverter is very important issue. This filter should reduce the high frequency distortion of output voltage and control the switching current. The switching devices generate this distortion. The IEEE Std. 1547 requirement for maximum harmonic voltage distortion is shown in table 1. For the medium power inverters whose PWM frequency is higher than 3 KHz, the low frequency harmonics (2nd, 3rd, 5th , and 7th) are usually rejected by controller perfectly. So, the high frequency distortion is only included switching or PWM frequency. According to the standard this distortion should be limited under 0.3%. TABLE 1. IEEE STD. 1547 REQUIREMENTS FOR MAXIMUM HARMONIC VOLTAGE DISTORTION
Individual Harmonic order
h
