A Novel FPGA Implementation of a Model Predictive Controller for SiC-Based Quasi-Z-Source Inverters Mostafa Mosa1,2, Gamal M. Dousoky2,3, and Haitham Abu-Rub2 1
2
Dept. of Electrical & Machine Engineering, Aswan University, Aswan, Egypt Dept. of Electrical & Computer Engineering, Texas A&M University at Qatar, Doha, Qatar 3 Electrical Engineering Department, Minia University, Egypt Email:
[email protected],
[email protected],
[email protected]
Abstract—This paper proposes a novel implementation of an FPGA-Based Model Predictive Control (MPC) for a SiC Quasi-ZSource inverter. To speed-up computations, to satisfy the control requirements and to increase the switching frequency, an MPC algorithm is designed for parallel processing and is implemented on an FPGA. This is suitable for high-sampling/switching frequency operation that enables the use of MPC in fast systems as SiC-based converters. Proposed concepts are simulated by MATLAB Simulink and are experimentally validated using a three-phase SiC-based Quasi-Z-Source inverter. Both of simulation and experimental results show that the proposed FPGAbased controller attains a good performance at a very small calculation time, comparable to that consumed by conventional MPC sequential implementations. Keywords—Parallel processing, FPGA implementation, Model predictive control; Quasi-Z-Source Inverter (qZSI).
I. INTRODUCTION Generally, increasing the switching frequency is preferred to have a high dynamic performance, to decrease filtering burdens and, accordingly, to increase the power density of switching power converters [1]-[3]. However, higher switching frequency is accompanied with higher switching losses, i.e. lower efficiency. Hence, a compromise is usually held to determine the optimum switching frequency; which depends on the used switch capabilities and characteristics. Nowadays, SiC switches provide an excellent performance and can afford rapid switching at low switching losses; which in turn motivates both industry and academia to do much effort in developing fast controllers to gain the benefits of such promising technology [4]-[6]. Model predictive controller (MPC) has emerged as a very powerful method for the control of electrical energy [8]-[10]. MPC is very intuitive, provides better performance than traditional modulation control techniques attain, and makes it easy to apply nonlinearity and constraints even in multivariable systems [11]-[13]. A considerable challenge of implementing MPCs is that the calculation time must be smaller than the sampling time to avoid overrun problems. Such constraint limits the use of MPC in fast systems as SiC-based converters and/or embedded systems. Traditionally, the implementation of MPCs has been accomplished using digital sequential processors; where the processes are calculated in a chronological order [13]-[14]. However, the parallel processing capability of FPGAs, along with its substantial improvements in price and performance, has made the application of many sophisticated control algorithms possible in power electronics field [14]-[17]. To accelerate the computation of MPC and to fulfill most of such control
978-1-4799-2325-0/14/$31.00 ©2014 IEEE
Figure 1: A Quasi-Z-Source inverter controlled by an FPGA.
requirements, an MPC algorithm has been designed for parallel computing and implemented inside an FPGA [18]-[20]. Moreover, a breadboard has been built-up for testing the effect of using the proposed FPGA-based MPC for driving an SiC-based three-phase quasi-z-source inverter as shown in Fig.1. II. MPC ALGORITHM FOR QZSI This section describes the model predictive control technique that optimizes the switching states of the qZSI. First of all, the control strategy depends on the reference power, and the reference capacitor voltage. The controller calculates the reference inductor current and the three phase reference output current from the reference power. In addition, inductor current, capacitor voltage and three phase output current are measured to regulate them through the control operation. The controller predict the behavior of the measured variables for the next step depending on the model of the qZSI and the load. The model of the qZSI is explained in details in [21]-[23] and is described in brief in this section. In qZSI, there are two states, active state and shoot through state. The discrete inductor current and capacitor voltage at active state are obtained by:
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iL1 (t Ts )
L1iL1 (t ) Ts (Vin Vc1 (t )) L1 RL1Ts
(1)
Vc1 (t Ts ) Vc1 (t )
Ts (iL (t Ts ) iinv (t Ts )) C1 1
(2)
In addition, the future discrete inductor current and capacitor voltage at a shoot through state are calculated as follows:
iL1 (t Ts )
L1iL1 (t ) TsVc1 (t )
(3)
L1 RL1Ts
Vc1 (t Ts ) Vc1 (t )
Ts i L (t Ts ) C1 1
(4)
Moreover, the future output load current is obtained by:
iout (t Ts )
Liout (t ) Ts Vi (t Ts ) L RTs
(5)
where is the load inductance, iout is the αβ of the three phase output current, R is the load resistance, and Vi is the inverter voltage. The proposed cost function includes prediction of the inductor current, capacitor voltage and three phase output current. The proposed cost function to fulfill the requirements of the presented model is expressed as:
g i* (t Ts ) i (t Ts ) i* (t Ts ) i (t Ts )
vc vc*1 (t Ts ) vc1 (t Ts ) iL iL*1 (t Ts ) iL1 (t Ts )
(6)
where vc and i L are the capacitor voltage weighting factor and inductor current weighting factor respectively. The target of the optimization is to choose the best state for the switches as shown in Fig. 2 by predicting the future value of the measured parameters [24]-[26]. As shown, point t is the current time when the control starts its observation. In the top of Fig. 2, assume ix is i , from t to t Ts there are eight future states for this current (ip1 (1)ip1 (8)) which can be calculated by (5) and the distance between any state and the reference is called cost function for the output current with unity weighting factor ( g xp ). The nearest future state current to the reference is ip1 (3) . In addition, the middle of Fig. 2 shows the behavior of the capacitor voltage and the prediction points of it. Same like previous, there are eight points (vcp1 (1)vcp1 (8)) which can be calculated from (2) and (4). The distance between any point and the reference is called cost function for the capacitor voltage with unity weighting factor ( g cp ). The bottom of Fig. 2 shows the inductor current and the prediction points. As shown, there are two prediction points only for the inductor current (one in active state and one in shoot through state which can be calculated from (1) and (3) respectively). Moreover, the distance between the prediction point and the reference is g Lp1 . The optimizer will choose the optimal state according to the summation of the cost function outputs in each round.
Figure 2: Schematic illustrating prediction observation for the output current, capacitor voltage and inductor current respectivelly.
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The selection process of the optimal switching states in each sampling period is presented in Fig. 3. First, the three phase output currents are measured at instance t . Then the reference inductor current is calculated. After that, the three phase load currents are transformed into αβ vectors. Furthermore, the three phase reference current are transformed into αβ vectors as well. Moreover, the controller generates the eight vectors, which depend on the capacitor reference voltage. Accordingly, prediction of the output current is calculated by (5). The next inductor current and capacitor voltage are calculated in each vector using (1)-(4). Finally, the selector choose the optimal switching state as explained in the previous section. The main drawback of this method is the sequential processing, where the MPC algorithm optimization is computed in a consecutive way; which takes long time. Accordingly, the sample time is not less than 30µS (with a 1 GHz computing clock), which produces a noticeable ripple in the load current. III. PROPOSED PARALLEL-PROCESSED FPGA IMPLEMENTATION To overcome the above addressed drawback, the MPC algorithm is configured for parallel processing with a fixedpoint 16-bit arithmetic. Figure 4 shows the proposed FPGAbased controller’s drive synthesis flowchart. As shown, all the sequential processes are converted into parallel ones and the state selector updates the optimal state every 1µS (with a 100 MHz computing clock), which gives the ability for the controller to operate at a sampling time of 1µS. The proposed implementation is developed in MATLAB Simulink environment using System Generator ISE 13.4. Then the target Xilinx Virtex-5 LX50T-1C FPGA is programmed using ControlDesk Next Generation 4.3 Software. As shown in Figs.1 and 4, the inductor current, the capacitor voltage and the three phase output current are sensed and sampled through a set of Analog to Digital Converters (ADCs). The generation of voltage vectors, the conversion of ABC to αβ form of the three phase output current and the three phase reference current, and calculation of the inductor reference current are computed in parallel. The next step is calculating the future value of the three phase output currents. Instead of the sequential calculation of the αβ vector, the proposed method calculates them in parallel as shown in Fig. 4. Future inductor current and capacitor voltage are calculated according to (1)-(4) then the cost function for each vector is weighted. Furthermore, the output current cost function evaluates the error using the predictive αβ value of the three phase output current and the αβ values of the three phase reference currents according to the first and second term in (6). Additionally, the capacitor voltage cost function evaluates the error between the predictive value of the capacitor voltage and the reference capacitor voltage, which is the third term in (6). Moreover, the inductor current cost function calculates the difference between the future value of the inductor current and the calculated reference value according to the last term in (6). All of the terms in (6) are calculated in parallel. The minimum of the cost functional vector reflects which switching vector must be applied to the inverter. To obtain inductor current, capacitor voltage and three phase output current for the next sampling step, the algorithm is executed again. Figure 3: Flowchart of the sequential-processed MPC algorithm.
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i out ( a ) ( t ), iout ( b ) ( t ) iout ( c ) (t ), iL1 (t ), vc1 (t )
iL _ ref (t )
i _ out (t )
i _ out (t )
i _ ref(out) (t) i _ ref(out) (t)
i (K1)
i (K 1)
iL1 ( K 1)
iL1 ( K 1)
iL1 ( K 1)
iL1 ( K 1)
Vc1 ( K 1)
Vc1 ( K 1)
Vc1 ( K 1)
Vc1 ( K 1)
Figure 4: proposed parallel-processed drive synthesis flowchart of the MPC algorithm for FPGA implementation.
IV. SIMULATION AND EXPERIMENTAL RESULTS To validate the proposed concepts, a simulation model is developed and an experimental prototype of qZSI is built. The capacitors type is EPCOS-B43501A9477M 470µF 400V aluminum electrolytic and the core of the inductors is AMCC 250 Metaglas UU core. GA35XCP12-247 SiC switch is used in the three phase qZSI. The overall system parameters are addressed in Table I. The three-phase output currents, capacitor voltage and inductor current are sensed and are sent to the controller as shown in Fig. 1. Then, they are converted into 12bit digital signals by means of ADC inside the controller. The MPC optimizing computations are implemented and are executed in parallel inside the FPGA board; as described in the previous sections. In the studied case, the three phase AC output reference current peak is 4.3A and the reference inductor current is 6A. Eight Space Vector Modulation (SVM) states are generated inside the FPGA board then one state is chosen and fed to the driver circuit to drive the inverter’s switches. The value of the capacitor voltage is 100V and the input voltage is 50V. The qZSI tries to boost the input voltage to 100V by changing the shoot through value. Figure 5 shows the simulation results of the input voltage and of the capacitor voltage. It is clear that the capacitor voltage is constant and equal the reference voltage. Moreover, Fig. 6 shows the DC-Link
voltage, which has a pulsated shape. Figure 7 shows that the inductor current is continuous and stable. Furthermore, Fig. 8 shows the three phase output current which is AC and pure sinusoidal. For the experimental results, Fig. 9 shows the input voltage (50V dc), the capacitor voltage (about 100V), the DC link, and the DC inductor current. As shown in Fig. 10 the DC-link voltage has a pulsated shape; it becomes zero at the shoot through time while the inductor current is charging. Figure 11 shows the input voltage, the capacitor voltage, the output current, and the inductor current. Figure 12 shows the three phase output currents and the capacitor voltage.
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TABLE I: THE OVERALL SYSTEM PARAMETERS
Symbol Vin L1, L2 C1, C2 Fsw L R Ts
Description Input DC voltage qZSI inductance qZSI capacitance Switching frequency Load inductance Load resistance Sampling time
Value 50 V 500 µH 470 µF ≤ 500 kHz 12 mH 10 Ω 1 µS
Capac itor V oltage & DC S ourc e V oltage [V ]
120 100 80 60 40 20 0 0.15
0.155
0.16
0.165
0.17
0.175 Time [S]
0.18
0.185
0.19
0.195
0.2
Figure 5: Simulation results for the input voltage (lower waveform) and controlled capacitor voltage (upper waveform) . Figure 9: Input voltage, capacitor voltage and DC-link inverter voltage.
160
DC-Link V oltage [V ]
140 120 100 80 60 40 20 0 0.15
0.155
0.16
0.165
0.17
0.175 Time [S]
0.18
0.185
0.19
0.195
0.2
Figure 6: Simulaton results for the DC-Link voltage. 10
Inductor Current [A]
8
Figure 10: Input voltage, input inductor current, capacitor voltage and DC-link voltage.
6
4
2
0 0.15
0.155
0.16
0.165
0.17
0.175 Time [S]
0.18
0.185
0.19
0.195
0.2
Figure 7: Simulation results for the inductor current. 5 4
Three Phase Current [A]
3 2 1 0 -1 -2
Figure 11: Input voltage, capacitor voltage and DC-link inverter voltage (zoom).
-3 -4 -5 0.15
0.155
0.16
0.165
0.17
0.175 Time [S]
0.18
0.185
0.19
0.195
0.2
Figure 8: Simulation results for the three phase output currents.
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[8]
[9] [10]
[11]
[12] Figure 12: Capacitor voltage and three phase AC output currents. [13]
CONCLUSIONS This paper deals with an FPGA-Based MPC for a SiC-qZSI feeding an RL load. The main aim of this work is to take the advantages of the SiC switches by increasing the switching frequency of the MPC controller. The novelty of the proposed contribution lies in parallel processing of the MPC algorithm and its implementation of FPGA. Accordingly, the size and the ripple of qZSI are effectively reduced by increasing the switching frequency of the system. The obtained experimental results show that this controller can ensure a constant capacitor voltage, continuous inductor current and sinusoidal AC load current as well. ACKNOWLEDGMENT
[14]
[15] [16] [17]
[18]
[19]
This work was supported by NPRP Grant NPRP 4-077-2-028 (section II) and NPRP-EP X-033-2-007 (sections III and IV) from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.
[20]
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