A pipelined semi-parallel LDPC Decoder

A pipelined semi-parallel LDPC Decoder architecture for DVB-S2 Denise C. Alves, Eduardo R. Lima, Jose E. Bertuzzo {denise.alves, eduardo.lima, jose.bertuzzo}@eldorado.org.br Instituto de Pesquisas Eldorado Campinas, S˜ao Paulo, Brazil

Abstract—The implementation of an LDPC Decoder for the DVB-S2 standard is a challenging task, specially because of 1) the large parity-check matrices and 2) the iterative decoding algorithm, which may represent a bottleneck within the receiver data flow. This paper presents a pipelined architecture for LDPC decoding based on a semi-parallel implementation of the Minimum-Sum algorithm, a simplification of the BeliefPropagation decoding algorithm, and the results of a model simulation and an early synthesis for FPGA prototyping.

I.

The remaining sections are organized as following: Section II reviews the basic concepts on LDPC codes and introduces the Minimum-Sum algorithm used to decode them; Section III presents the structure of the parity-check matrices defined by the DVB-S2 standard and how the decoding algorithm can be parallelized in this application; Section IV presents the proposed LDPC Decoder architecture; Section V presents the result of a simulation run with the LDPC Decoder model; Section VI presents the results of an early synthesis for FPGA prototyping; and finally Section VII concludes the paper.

I NTRODUCTION

DVB-S2 is the state-of-the-art ETSI standard for satellite broadcasting [1]. It was developed by the Digital Video Broadcasting (DVB) project and it is the evolution of DVB-S. Its main characteristics are: 1) the flexibility to operate with different input formats, modulations and channel coding modes; 2) the Adaptive Coding and Modulation (ACM) functionality, which allows optimization on a frame-by-frame basis; 3) and a powerful Forward Error Correction (FEC) system based on the concatenation of Low Density Parity Check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) codes, allowing QuasiError-Free operation at about 0.7 to 1 dB from the Shannon limit. The standard defines a sequence of functional blocks that process and generate different frame formats within the transmitter. The FEC encoding system shall receive a Baseband Frame (BBFRAME) coming from the Stream Adaptation module and encode it by adding two blocks of parity bits, the BCHFEC and the LDPCFEC. The concatenation of the BBFRAME with the two parity bit blocks constitute a FECFRAME. The standard also defines two FEC frame lengths (normal with 64800 bits, short with 16200 bits) and eleven code rates (1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10). For each combination of frame length and code rate (they are 21, since the 9/10 code rate is not used with short frames), a different LDPC coding scheme is applied, which makes the LDPC feature account for the most complex part of a DVB-S2 FEC system [2]. In a fully compliant receiver, the complexity increases because of the need to implement an iterative decoding algorithm that requires a large amount of memory and a reasonable level of parallelism. In this paper, we present a pipelined architecture for LDPC decoding that implements the Mininum-Sum algorithm and takes advantage of the parallelism and turbo message passing benefits offered by the layered decoding method [2] [3].

II.

A REVIEW ON LDPC CODES AND DECODING ALGORITHM

The LDPC codes [4] consist of linear block codes with a sparse M × N parity-check matrix, where each block of K information bits (the payload BBFRAME+BCHFEC in DVBS2), are encoded to a codeword of size N (the FECFRAME), by adding a set of M = N − K parity bits (the LDPCFEC). Both the encoding and decoding processes are executed based on a parity-check matrix H, and the codeword c (composed by the payload and the LDPCFEC) is built so that H × c = 0. For decoding LDPC codes in the DVB-S2 receiver, the Minimum-Sum algorithm, a simplification of the BeliefPropagation (BP) based on Log Likelihood Ratio (LLR) [5], was implemented with a layered decoding [3] approach. The basic idea of this iterative algorithm is exchanging messages between Variable Nodes (VNs), corresponding to the received bits/symbols, and Check Nodes (CNs), corresponding to the parity-check equations, in order to calculate new probabilities of a given received bit being ‘0’ or ‘1’. The messages are signed integers corresponding to the quantized LLRs of the reP (xn =0|yn ) ceived bits, which are defined as LLR(xn ) = log P (xn =1|yn ) ∈