A Practical Space-Code Correlator Receiver for DSP Based Software

Wireless Pers Commun (2009) 49:245–261 DOI 10.1007/s11277-008-9570-6

A Practical Space-Code Correlator Receiver for DSP Based Software Radio Implementation in CDMA2000 Kerem Kucuk · Adnan Kavak · Mustafa Karakoc · Halil Yiˇgit · Caner Ozdemir

Published online: 22 August 2008 © Springer Science+Business Media, LLC. 2008

Abstract Development of practical algorithms for beamforming in 3G CDMA systems and their software radio implementations are still a challenging task, which will facilitate upgrading of traditional base stations into smart antenna capable 3G base stations. In this paper, we propose a practical space-code correlator (SCC) receiver structure for its software radio implementation a DSP. SCC’s advantage comes from the fact that it doesn’t require any training sequence or learning parameter as in other algorithms (LMS or CM). DSP implementations of the SCC are performed using Texas Instruments C67xx family platforms. In the simulations, reverse link base band signal format of CDMA2000 is used and the effects of different array topologies (uniform linear array-ULA or uniform circular array-UCA) are considered. The implementation results regarding beamforming accuracy, weight vector computation time (execution time), search resolution effect on DOA estimation accuracy, DSP resource utilization, and received SINR are presented. The results show that DSP based SCC beamformer can estimate weight vectors within less than 10 ms with DOA search resolution of 2◦ especially when C6713 DSP is used. With faster DSPs and

K. Kucuk · H. Yiˇgit Department of Electronic and Computer Education, Kocaeli University, Izmit, Kocaeli 41380, Turkey e-mail: [email protected] H. Yiˇgit e-mail: [email protected] A. Kavak (B) Wireless Communications and Information Systems Research Centre, Department of Computer Engineering, Kocaeli University, Izmit, Kocaeli 41040, Turkey e-mail: [email protected] M. Karakoc Turkcell Telecommunication Services, Kartal, Istanbul 34880, Turkey e-mail: [email protected] C. Ozdemir Department of Electrical and Electronics Engineering, Mersin University, Mersin 33343, Turkey e-mail: [email protected]

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larger search resolutions, execution time could be significantly reduced as well. It provides comparable SINR performance with LMS and CM algorithms. Keywords Adaptive arrays · CDMA2000 · Digital signal processor (DSP) · Direction of arrival (DOA) estimation · Field programmable gate array(FPGA) · Smart antenna systems (SAS) · Software radio · 3G Systems

1 Introduction Mobile communication systems have been growing exponentially and used widely all around the world. Third-generation (3G) systems based on wideband code division multiple access (WCDMA) technique are aimed to provide worldwide communication capability with wide range of services (voice, data, video, message) at high speed rates. However, there exist problems such as transmission of mixed traffic signals through wireless propagation medium at high rates, limited system capacity, and low coverage range of base stations. In solving these problems, researches have focused on software and cognitive radio, smart antenna and MIMO systems and advanced signal processing techniques. Software defined radio (SDR) is often described as a radio whose functionality can be defined in the software [1]. SDR requires programmable processors to perform the signal processing necessary to transmit and receive base band information at radio frequencies [2]. This technology offers greater flexibility and potentially longer product life, since the radio functionalities can be updated very cost effectively by software. A Smart Antenna System (SAS) that employs an antenna array and advanced signal processing techniques at the base station performs spatial-filtering on signals received from multiple users at distinct locations, adaptively adjust their beam patterns according to propagation dynamics [3]. It has been shown that SAS improves system capacity and spectral efficiency, expands coverage, and provides transfer of high data rate by efficiently utilizing the given bandwidth [4]. It employs beamforming algorithms to track the desired user and suppress the possible interference [5]. It requires both the software (beamforming algorithm in base band) and the hardware (RF transceiver, multiple antennas) associated with the additional processing capability. One of the major challenges integrating a SAS into 3G CDMA base stations is the development of beamforming algorithms that can provide the desired performance as well as having small computational load for the SDR implementation [6]. SDR implementation of beamforming algorithms on programmable processors such as digital signal processors (DSPs), field programmable gate array (FPGAs), or special type of ASICs facilitates upgrading of existing 3G base stations into smart antenna processing capable base stations. DSPs can be viewed as special purpose CPUs providing fast instruction sequences, such as shift, add, and multiply, and therefore they are widely used in math-intensive signal processing applications [7]. FPGAs with their re-programmable logic gates and functions are more hardware oriented devices but preferred for more time critical applications requiring high processing speed when compared to DSPs [8]. 1.1 Related Works The array processing algorithms used in wireless communications are usually designed to operate in a particular air interface. Various wireless standards in 2G and 3G systems with different access techniques (FDMA, TDMA, CDMA, WCDMA, and CDMA2000)

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and modulation schemes motivate the investigation of array processing schemes that can be software-implement able and adaptable for programmable processors. The code filtering approach (CFA) proposed by Naguib [9] was the pioneering work in the field of beamforming for CDMA systems. In CFA, traditional RAKE receiver for CDMA is replaced by a beamformer-RAKE receiver in which beamforming is applied to each finger, and then the outputs of from each finger is summed up. Since then, many research efforts have been put in the development of beamforming algorithms for CDMA systems with the emergence of 3G wireless systems [10–17]. In [18], a normalized constant modulus algorithm (NCMA) was implemented using SPARTAN II FPGA from Xilinx to demonstrate digital beamforming capability of an FPGA. A smart antenna base station transceiver (BTS) using TI’s C6711 DSP in beamformer weight vector estimation for CDMA2000 1X was introduced in [19]. The beamformer was installed in each channel card controlled by MPC860 based controller. The optimal weight vector in C6711 was computed in such a way to maximize the signal to interference plus noise ratio (SINR) by using Lagrange’s formula for generalized eigenvector solution. Wu et al. [20] has implemented a smart antenna testbed utilizing a beamformer module that included 4 TI C6701 DSPs on the same board, where a digital beamforming with phase compensation technique was used. That testbed was, however, unable to support CDMA signal due to the high chip rate required. Im and Choi [21] demonstrated a smart antenna implementation where C6701 based beamformer can compute weight vectors of 16 users in Korean CDMA Wireless Local Loop (WLL) system by using Lagrange’s formula for generalized eigenvector solution. In his very earlier work [22], Choi used the linearized conjugate gradient method (LCGM) to implement beamforming on a general-purpose DSP with a clock frequency of 30 MHz. Introduction of the SUNBEAM project built on the work of the Advanced Communications Technologies and Services (ACTS) program in TSUNAMI II project was given in [23], which proposed algorithms and analyzed the feasibility of implementation of array processing architectures in multi standard UMTS/GSM base stations. Two different types of beamforming algorithm were considered for the software radio implementation, which are suitable for the uplink of UTRA-FDD: Vector RAKE [24] and MDIR [25]. Vector RAKE receiver is based on the idea of code filtering approach proposed by Naguib [9]. The optimum beamformer weights in Vector RAKE are given by the Wiener solution [26]. MDIR performs spatial cancellation followed by a RAKE receiver. MDIR was shown to outperform Vector-RAKE receiver in both pedestrian and vehicular scenarios due to severe nature of the radio channel. However, when two receivers were compared from the processing requirements perspective, which were expressed in terms of floating point operations on a DSP, Vector-RAKE was shown to be less complex than MDIR in terms of implementation with TI’s C6203 DSP. A DSP based implementation of reverse link beamformers for a WCDMA using Least Mean Squares (LMS) and Recursive Least Squares (RLS) algorithms was presented in [27] Implementations were performed using fixed-point arithmetic on TI’s C6211 DSP processor that has maximum clock rate of 167 MHz. Compared to RLS, LMS resulted in a low convergence rate requiring more than one radio frame (dedicated control channel—DPCCH). The performance of the algorithms was not tested for dynamic channel conditions in which multipath fading coefficients and DOAs change randomly. Implementation of a setup module using TI’s C6203 DSP for possible plug-and-play operation of a smart antenna with Node B of UTRA-UMTS system was presented in [28]. In the setup module, two TI C6203 DSPs were used; one for the implementation of physical layer, and the other for the implementation of MAC, RLC and RRC layers. The weight vectors were

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computed for each user by using the normalized least mean squares (NLMS) algorithm. The pilot bits in the uplink dedicated physical control channel DPCCH were used as temporal reference for the adaptive algorithm. The execution time of MAC, RLC, RRC layers were shown to be much less than 5 ms. However, no result regarding the execution time of NLMS algorithm in physical layer was mentioned. For real time operation most of the implementation effort will be given to estimate beamformer weight vector, which needs to be carried out in physical layer. 1.2 Contribution of this Work In this paper, we propose a practical space-code correlator receiver for 3G CDMA and evaluate the feasibility of its SDR implementation using DSPs for CDMA2000 reverse link channel [29]. We use TI’s high performance C67x family floating-point DSPs (C6701, C6711, and C6713) for the implementation. Rather than building the whole hardware testbed which requires antenna array, RF/IF transceiver, ADC/DAC units, we only focus on the key part of the system, which is the software radio beamformer. We evaluate the performance of SDR implementation of SCC receiver in terms of beamforming accuracy, weight vector computation time (execution time), DSP resource utilization, and received SINR. Our proposed SCC algorithm can be considered as the practical version of Vector RAKE receiver. Unlike nonblind type LMS [5] and blind type CM [5,30] algorithms, SCC algorithm does not require any training sequence or learning parameter and its weight vector computation time is not affected by the array topology and multipath fading conditions [31]. The remainder of the paper is organized as follows. In the following section, base band signal model used in the simulations is given. In Sect. 3, the structure and mathematical model of SCC beamforming receiver are presented. Section 4 explains the implementation setups and parameters. Section 5 presents results of DSP based software radio implementation including beamforming accuracy, DSP resource utilization, convergence time, and received SINR. Finally, the concluding remarks and discussions regarding the performance of the proposed SCC are given in Sect. 6.

2 Baseband Signal Model We consider the reverse link signal format of CDMA2000 [29,32] as shown in Fig. 1. For the ith mobile user, bi (l) is the zero mean, independent identically distributed (i.i.d.) bit sequence with unit variance taking values {+1, −1}, which corresponds to traffic channel transmitted thru the Q channel and h i (l) is the bit sequence composed of all “1”s, which corresponds to pilot channel transmitted thru the I channel. The index l denotes the symbol index. After scaling with gains G 1 and G 2 , the bit sequences in the I and Q channels for the ith user can be written as, (I )

di (l) = G1 · h(l), (Q) di (l)

= G2 · b(l),

(1) (2)

and their complex representation is given by Q

di (l) = diI (l) + jdi (l). (I ) (Q) Let us define ci (l; m) and ci (l; m) be the L-chip spreading codes of I

(3)

and Q-channels, respectively, for the lth symbol of this user, where m is the chip index with m = 0 . . . L − 1.

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Convolutional Coding R = 1/3 , K = 9

Vocoder 9.6 Kbps

BPSK modulation 0 → 1,1→ -1

Interleaving ( 576 Symbol )

28.8 Kbps

b(t) x CIPN b(t) x CQPN

_ +

Σ

Σ +

b(t)

Walsh matrix with size 64

G2 = 0.7

h(t) x CIPN

+

pilot channel

G1 = 1

h(t) x CQPN

h(t)

Pilot (t) =1

Tc/2 ½ chip delay cIPN

CQPN Long PN

Σ

s(t)

GS

CDMA2000 RC1 format signal

s(t) = s(t) / ⏐s(t) ⏐ Fig. 1 The block diagram for base band signal model transmitted from a mobile in CDMA2000 format

These code sequences are identically distributed, random binary numbers taken from the set {+1, −1} with equal probability of unit variance. And the complex spreading code sequence ci (l; m) is (I )

(Q)

ci (l; m) = ci (l; m) + jci

(l; m).

(4)

The corresponding continuous time spreading signal can be written as ci (l; t) =

L−1


ci (l; m) · p (t − [(l − 1)L + m]Tc )

(5)

m=0

where, p(t) is the waveform for the pulse shaping filter and Tc is the chip period which is the ratio of symbol period Tw over processing gain Nc (i.e.,Tc = Tw /L). Thus, the base band form of then transmitted signal from [9] user i is si (t) =

∞


di (l) · ci (l; t)

(6)

l=1

3 Space-Code Correlator (SCC) Receiver It consists of two stages: code correlator and space correlator parts, and therefore named as space-code correlator (SCC) [30] receiver as depicted in Fig. 2. From another perspective in this structure, each finger of traditional RAKE receiver in CDMA systems is followed by space correlator stage which utilizes predefined spatial correlation vectors (array response vectors). In the code correlator stage, multipath components of received signal vector are

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τ2

X1

Code M Correlator #1

X2

Code M Correlator #2

XM

Code M Correlator #F

τ1

Space Correlator #1

M

θˆ1

Z2

))

τF

Space Correlator #2

M

θˆ =

θˆ2

1 F

F

∑ θˆ

p

p =1

ZF Wireless Propagation Channel

M

Space Correlator #F

M

a(θ 1) a(θ 2) a(θ 3)

θˆF

M WU

a(θK)

M

Reverse Link Beamformer

Reverse Link search table Fig. 2 Space-code correlator receiver architecture for the implementation on a DSP

despread by the code of the desired user to obtain post correlation signal vector (Z’s in Fig. 2). In the space correlator stage, post-correlation signal vector is correlated with the predefined array response vectors that are stored in “Reverse Link Search Table” to yield direction of arrival (DOA) estimations (θ ’s in Fig. 2). Let f and F denote the multipath index and number of multipath, respectively, from the desired mobile to the base station as depicted in Fig. 2. The multipath channel induces complex path attenuation, αi, f = βi, f e jφi, f and time delay τi, f on the transmitted signal given by (6). Hence, signal received by M element antenna array at the base station can be expressed as, X (t) =

Fi NI



    αi, f · si t − τi, f · a θi, f + n (t) ,

(7)

i=1 f =1

where N I is the number of interference users, Fi is the multipath number for the ith user, θi, f is the direction-of-arrival (DOA) of f th multipath signal of the ith user, and n(t) is Additive White Gaussian Noise vector. Without loss of generality let i = 1 denote index for the desired user. The desired, interference, and noise components are separated as following X (t) =

F1
f =1



Fi NI
   
    α1, f · s1 t − τ1, f · a θ1, f + αi, f · si t − τi, f · a θi, f +n (t) ,

 desired

i=2 f =1

 



(8)



interference

The received signal vector X(t) is first passed through code correlator blocks in which it is despread with its code c I . For simplicity, we drop the term l in c1 (l; t) and the post-correlation output vector of the pth finger can be written as,

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1 Z p (t) = Tw

Z p (l) =

L−1


c1∗ (l; m).

m=0

1 · Tw

251

lTw+τ1, p

  X (t) · c1∗ t − τ1, p dt

(9)

(l−1)Tw +τ1, p

(m+1)T  c +τ1, p

X(t) · p(t− [(l−1)L + m] · Tc −τ1, p )dt

(10)

mTc +τ1, p

Assuming that the base band signal is sampled at Tc instants and the pulse shaping waveform is chosen as rectangular function with unit amplitude, and then the above equation is simplified to Z p (l) =

L−1 1
∗ c1 (l; m) · X(mTc + τ1, p ) p = 1, 2, . . . , F. L

(11)

m=0

It is assumed that each multipath time delay (τl, p ) required for despreading process is computed by a time delay search algorithm, which is beyond the scope of this work. After code correlation process, spatial correlation between Z p (l) and array response vectors a(θ ) is carried out. For this purpose, the range [0◦ 180◦ ] is divided into K DOAs, which have angular resolution of θ ◦ = 180◦ /(K − 1). Hence, we need to store K complex-valued array response vectors a(θ ) with dimension Mx1 in the reverse link search table. The output of space correlator for each multipath tries to find the maximum DOA as given by 2 θˆ p = arg max a (θ ) H · Z p (l) . (12) Then, the mean DOA angle obtained as the average of F paths is given by [33] θˆ =

F 1
θˆ p . F

(13)

p=1

This estimated DOA can be used for both uplink and downlink beamforming provided that the user position changes very slowly during several symbol periods. The complexity and accuracy of the SCC receiver depends on number of multipath (F), SNR level of multipath, number of antenna elements (M), and angular resolution of the DOA range to be scanned (θ ◦ ). For small multipath level and small DOA resolution, the algorithm is expected to find the desired user’s DOA much accurately.

4 DSP Implementation 4.1 Implementation Setup The hardware setup for the implementation of SCC receiver consists of a PC and DSP boards. In order to test the performances of various processor configurations, we prefer using three different DSPs (Texas Instruments’ C6701, C6711 and C6713). The C6701 EVM supports four clock rates up to 133 MHz and includes a peripheral component interconnect (PCI) interface that enables host access to the onboard joint test action group (JTAG) controller, DSP host port interface (HPI), and board control/status registers [34]. The C6711 DSK has clock rate of 150 MHz and communicates a PC via parallel port interface [35]. The C6713 DSP

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operates at 225 MHz and delivers up to 1350 MFLOPS/1800 MIPS with dual floating/fixedpoint multipliers up to 450 million multiply accumulate operations per second (MMACS). The 6713 DSK uses universal serial bus (USB) communications for connections to the host [36]. Having higher operating frequency for a processor does not necessarily mean that this processor provides better performance. Internal memory architecture of a processor, width of data paths, and configurations of external memory also affect the performance of a processor [37]. The algorithms are directly coded in assembly language using TI’s Code Composer Studio (CCS) version 3.01 [38] and loaded into the DSP memory. Each DSP board’s performance is tested separately, i.e., one of the DSP boards is connected to the host PC at a time. We utilized Matlab’s tool for CCS utility [39] for the loading of received signal vector defined in (7) into the DSP memory and post processing of the obtained weight vector. The execution time of the algorithm for computing weight vector is obtained by counting the clock cycles for the execution of the desired part of our assembly code (given in Table 1 below), which is achieved by setting break points in relevant part of the code via CCS. The assembly code is compiled using CCS and its optimization is made by running the code in single steps. 4.2 Coding of the Algorithm in Assembly The SCC algorithm whose architecture was given previously in Fig. 2 is based on performing code correlation with the desired user’s code as given by (11) and then spatial correlation of this post-correlation signal with the predetermined array response vectors as given by (12). Table 1 IEEE 32-Bit floating point assembly code of SCC algorithm implemented on TI C67x DSPs SCC_Main_Entry MVK .S2 48,B13 || MVK .S2 12,B0 SCC_Code_Corr_Entry MVK .S2 5,B1 Subroutine_1 || MVK .S2 64,B2 Subroutine_2 LDW .D1 *A4++[5],A8

Subroutine_4 ADDSP || SUB [B2]B STW || STW

.L2X .S2 .S2 .D1 .D2

A10,B11,B11 B2,1,B2 Subroutine_4 A11,*A15++[1] B11,*B15++[1]

SUB [B1]B || ADDK

.S2 .S2 .S2

B1,1,B1 Subroutine_3 20,B5

|| SUB [B2]B

.S2 B2,1,B2 .S2 Subroutine_2

Subroutine_5

|| STW SUB

.D2 B10,*B6++[1] .S1 A4,A0,A4

|| MPYSP ADDSP

|| SUB [B1]B

.S2 B1,1,B1 .S2 Subroutine_1

[B2]B

.S2

Subroutine_5

|| ADD SUB [B0]B

.S2X B4,A1,B4 .S2 B0,1,B0 .S2 SCC_Code_Corr_Entry

|| SUB [B0]B

.L2 .S2

B0,1,B0 SCC_Space_Corr_Entry

MVK .S2 90,B0 SCC_Space_Corr_Entry MVK .S2 12,B1 Subroutine_3 || MVK .S2 5,B2 NOP hasn’t shown in this code

123

.M2 B8,B8,B9 .L1X A9,B9,A10

|| MVK .S2 90,B1 SCC_Peak_Find_Entry LDW .D2X *B7++[1],A14 CMPLTSP .S2X A14,B14,B0 [B0]B .S2 MV .S Subroutine_6 [B1]B .S2

Subroutine_6 A14,B14 SCC_Peak_Find_Entry SCC_Main_Entry

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253

Table 1 describes SCC algorithm’s implementation, which is directly coded in assembly using CCS Tool for TI’s C67x DSPs. The code considers parallel operation of some instructions, and it is tried to be made as optimized as possible. It has four main blocks which are desired part of the assembly code for profiling code performance: SCC_Main_Entry: This routine performs some initialization steps such as determination of path number, size of the data to be processed, and controlling of other routines. SCC_Code_Corr_Entry: This routine performs code correlation of the received signal vector with the desired user’s code as given by (11). Mathematically, it implements matrix multiplication to yield post-correlation signal vector by using two subroutines. SCC_Space_Corr_Entry: It computes the inner product of post-correlation signal vector with predetermined spatial correlation vectors as given by (12), which is stored as KxM matrix. Hence, the output of this routine is K complex-valued numbers stored in data memory to be sent out to next routine. This routine includes three subroutines. SCC_Peak_Find_Entry: By taking the output of previous routine as input, this routine searches the index (which is desired user’s DOA) for the maximum value of squared amplitudes of K numbers. 4.3 Input Signal Parameters The receiving antenna topology is a five-element antenna array with either uniform linear array (ULA) or uniform circular array (UCA) configuration. In the signal modeling, wireless channel that has one direct path and one multipath component of the desired signal, and an interference signal is considered. Relevant parameters in each simulation run are set as follows: For desired signal component, direction-of-arrival (DOA) of the direct path (θ1,1 ) is fixed at 32◦ , while DOA of the multipath (θ1,2 ) and the interference signal (θ2,1 ) is generated randomly in the form of uniform distribution. The amplitude (β) and phase (φ) components of multipath fading parameters are represented by Rayleigh and uniform random variables, respectively. Multipath signal power is set to −5 dB, −10 dB, and −15 dB levels for testing the performance of the algorithm. Interference signal is −10 dB below the direct path of desired signal. 5 Results 5.1 Beamforming Accuracy First we check the DSP implemented beamformers’ ability to track the desired user’s direction-of-arrival (DOA). Figure 3 shows a representative beamforming spectrum plotted using a weight vectors that is obtained as a result of DSP implementation of the SCC beamformer on C6713 DSK. Here, we note that we performed repeated simulations on C6713 DSK and other DSPs (C6711 and C6701). We observed very similar beamforming plots all showing peak in the direction of desired users’ direct path as long as direct path is spatially well separated from the multipath and interference. As seen from the Fig. 3, SCC beamformer implemented on a DSP successfully pinpoints the desired user direction at 32◦ . 5.2 Weight Vector Computation (Execution) Time Weight vector computation time which is referred as DSP execution time of the algorithm is the time elapsed until a stopping criterion is attained while computing the beamforming

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Fig. 3 A representative beamforming spectrum of the SCC beamformer implemented on C6713 DSP Table 2 Execution time of SCC algorithm for ULA configuration with 5-elements DOA resolution (θ )

SCC_Code_Corr_Entry SCC_Space_Corr_Entry SCC_Peak_Find_Entry Total cycle Total time (ms)

C6701

C6711

C6713

0.5◦

2◦

0.5◦

2◦

0.5◦

2◦

1737303 3976001 6472 5740317 43.16

434304 993330 1620 1430002 10.75

2261011 5010804 12220 7286045 48.57

565404 1252710 3060 1823262 12.15

2613504 5727960 9023 8359327 37.15

653364 1431990 2250 2090147 9.28

weight vector using the code in Table 1. Execution time is determined using CCS profiler menu by counting the clock cycles. The profiler analyzes program execution and shows where the program spends its time. Several factors such as CPU clock speed, speed and width of external memory can affect execution time. In order to assess the performance of the SCC algorithm under varying multipath channel conditions with random DOA and fading coefficient, code is run repeatedly many times. The results regarding clock cycles and corresponding execution times for each DSP type with DOA resolutions of 0.5◦ and 2◦ are summarized in Table 2. To determine the clock cycles for each entry, we used toggle breakpoints in our assembly code. Most of the clock cycle is wasted in the space correlator part while the least of the clock cycle is wasted in the peak finder part. Smallest execution time can be achieved by using C6713 DSP. For θ = 2◦ , it is below 10 ms. However, largest execution time is obtained by using C6711 DSP. The reason for this is the different hardware architectures and speeds of DSPs. 5.3 Effect of DOA Search Resolution SCC algorithm’s execution time is not affected by the change in multipath DOA (θi, f ) fading level (αi, f ) and antenna array topology. However, the sensitivity of its execution time depends

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Fig. 4 DOA estimation errors of SCC algorithm implementation for θ = 0.5◦ and ULA topology

on number of multipath (F) and DOA search resolution (θ ). In order to demonstrate the sensitivity of SCC algorithm, simulations were run using DOA resolutions of θ = 0.5◦ and θ = 2◦ . Using DOA search resolution of θ = 2◦ reduces execution time approximately by four times when compared to using DOA search resolution of θ = 0.5◦ as seen from Table 2. Here, we note that smaller execution time could be obtained with larger DOA resolutions at the expense of performance degradation in DOA estimation and SINR. For this reason, we also examine the effect of DOA search resolution on the DOA estimation error under varying multipath SNR level and array topology. Histograms for the DOA estimation errors obtained from 1000 repeated simulation runs are given in Figs. 4 and 5 for θ = 0.5◦ and θ = 2◦ , respectively. In each simulation run, multipath DOAs and fading coefficients change randomly. Obviously, SCC algorithm performs poor for low SNR case. As observed from top subplots of Figs. 4 and 5, DOA estimation error is noticeably spread over large angle range (implying large standard deviation) for low SNR case, i.e., SNR = 5 dB . For both θ = 0.5◦ and θ = 2◦ cases, it varies between 0◦ and 11◦ . However, DOA estimation error is squeezed into low angle range (implying small standard deviation) for high SNR case, i.e., SNR = 15 dB. In this case, it is limited between 0◦ and 6◦ for both DOA resolutions. Mean values of DOA estimation errors which are derived from the histograms are given in Table 3 for both ULA and UCA topology. DOA resolution of θ = 0.5◦ leads to slightly smaller DOA estimation errors as compared to θ = 2◦ case for all multipath conditions. For example, while mean value of DOA estimation error is 1.44◦ for θ = 0.5◦ , it is found as 2.21◦ for θ = 2◦ when SNR is 15 dB and ULA is used. Another remarkable observation about DOA estimations errors is that SCC performs better when UCA topology is employed as evident from Table 3. Execution time for θ = 0.5◦ is significantly larger than 10 ms duplexing internal of CDMA2000 system (see Table 2), hence, it is feasible to consider θ = 2◦ for SCC implementations.

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Fig. 5 DOA estimation errors of SCC algorithm implementation for θ = 2◦ for ULA topology Table 3 Mean and standard deviation of DOA estimation errors with different DOA search resolutions (θ = 0.5◦ and θ = 2◦ ) in SCC beamformer implementation using TI C6713 DSP SNR 5 dB

θ

2◦ 0.5◦

Mean Std. Mean Std.

10 dB

15 dB

UCA

ULA

UCA

ULA

UCA

ULA

3.57 1.97 3.36 1.86

3.83 2.55 3.38 2.03

2.25 1.36 2.25 1.23

2.74 1.97 2.26 1.42

1.41 0.91 1.38 0.75

2.21 1.57 1.44 1.02

5.4 DSP Resource Utilization We evaluate the implementation of the SCC algorithm in terms of DSP resource utilization, i.e., memory occupancy and compare it with other algorithms such as LMS and CM. Results are summarized in Table 4. When implementations are examined from the program memory usage perspective, in which the assembly code is placed, we see that C6701 EVM requires the smallest memory space. On the other hand, when examined from floating point instruction execution and data memory occupancy perspectives, C6713 DSK requires the smallest memory space. 5.5 Signal-to-Interference Plus Noise Ratio (SINR) One of the measures that need to be studied for evaluation DSP based beamformer is how much SINR can be obtained via the computed weight vectors. SINR values for each

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Table 4 DSP resource utilization for the implementation of various beamforming algorithms DSP device

C6701 EVM C6711 DSK C6713 DSK

MIPS

MFLOPS

1064 at 133 MHz 1200 at 150 MHz 1800 at 225 MHz

Using internal program memory

798 at 133 MHz 900 at 150 MHz 1350 at 225 MHz

Using external data memory

LMS

CM

SCC

0.88% 14% 14%

0.93% 14.8% 14.8%

0.98% 15.6% 15.6%

61% 57.4% 15%

Table 5 Mean and standard deviation for SINR performance of the software radio beamformers LMS

Received SINR (dB)

Mean

DSP

Std.

DSP

C6701 C6711 C6713 C6701 C6711 C6713

CM

SCC

UCA

ULA

UCA

ULA

UCA

ULA

16.86 16.83 16.86 0.019 0.019 0.019

12.46 12.59 13.85 5.59 5.28 5.01

16.02 16.02 16.02 0.028 0.028 0.028

15.94 16.47 16.24 1.16 2.30 2.13

15.58 13.96 13.96 6.26 6.87 6.55

14.11 13.93 13.96 6.80 6.95 5.98

computed weight vector are calculated as described in [40] and cumulative distributions of the SINR values are obtained. Mean and standard deviation derived from these cumulative distributions are given in Table 5. For the comparison, we also provide results of our previous study [30] obtained for non-blind type LMS and blind-type CM beamformers. Although CM beamformer’s SINR performance is slightly better than LMS and SCC, all three beamformers provide nearly the same SINR values. SINR values for SCC are obtained under multipath SNR level 5 dB (which is our worst case). One important observation on the results is that standard deviation in SINR values obtained by SCC is larger when compared to LMS and CM for both ULA and UCA topologies. This is because we have evaluated SCC’s performance under strong multipath condition (which is −5 dB below direct path). When multipath and direct path DOAs do not fall apart, SCC is unable to precisely estimate both DOAs and that provides a weight vector different than the actual weight vector. However, we expect better results with SCC when weak multipath signal is considered. When compared from the DSP processor perspective, SINR performance of the beamformers is almost unaffected by their implementation on different processors considered here.

6 Conclusions In this paper, we have proposed a practical space-code correlator (SCC) beamformer receiver for CDMA2000 system and demonstrated its software radio implementation using TI’s C67x family floating point DSPs (C6701, C6711, C6713). At the base station receiver, a five-element ULA and UCA antenna configurations are considered. A simple wireless channel model that has one direct and one multipath component for the desired signal and an interference signal is used in generating the received signal vector at the antenna array. The input signal generation, initialization of the DSP memory, loading of the implemented codes onto the DSP memory, and finally post processing of processed data from the DSP are all handled via Matlab link for CCS.

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The performance evaluation of the implemented beamformer is accomplished in terms of various measures: Accuracy of beamforming spectrum, execution time (weight vector computation time), DSP resource utilization, and receive SINR. Also, the effect of DOA search resolution on its performance is examined. Our assembly code for SCC is run repeatedly many times to assess the performance under dynamic multipath channel conditions in which DOA and fading coefficient of the multipath changes randomly from one simulation run to another. Based on the results obtained from implementation of our SCC algorithm on TI’s C6701, C6711, and C6713 DSP platforms, following conclusions can be made: • •

•

In general, SCC software radio beamformer can approximately point in the desired user direction with a certain DOA error. Multipath SNR level and DOA search resolution affect the beamforming accuracy of SCC algorithm. Only C6713 results in the smallest execution time less than 10 ms (for θ = 2◦ ), duplexing time in CDMA2000. However, implementations on C6701 and C6711 can compute weight vectors within the time period slightly greater than 10 ms. With faster DSPs and other programmable devices (such as FPGA) and optimization of the assembly codes, it is possible to reduce this execution time. SINR performance of the SCC is expected to improve better when desired signal component becomes stronger than the multipath signals. The advantage of our proposed SCC algorithm is that unlike LMS and CM algorithms it does not require any learning parameter or training sequence. Also, its convergence (weight vector computation) time is not affected by the array topology and multipath fading coefficients.

Acknowledgements This work was supported by following: (1) DSP equipment and software donation from Texas Instrument’s European University Program, (2) Kocaeli University Scientific Research Projects Unit under grant 2005/58. The author’s would like to thank anonymous reviewers who helped to improve the quality of this paper by their careful reading.

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Author Biographies Kerem Kucuk was born in Izmit, Turkey, in 1979. He received the B.Sc. and M.Sc. degrees from the Electronics and Computer Education Department, Kocaeli University, Kocaeli, Turkey, in 2002 and 2005, respectively. He is currently pursuing his Ph.D. degree at Kocaeli University. Currently, he is a research assistant with the Department of Electronics and Computer Education, and a member of Wireless Communications and Information Systems (WINS) Research Center, University of Kocaeli, Turkey. Kucuk was awarded “Excellence in Signal Processing Award” by Texas Instruments, in May 2006. His current research interests include wireless communication, wireless sensor networks, MIMO systems, software radio, smart antenna implementation, digital signal processor. His URL is http://wins.kocaeli.edu.tr/kkucuk/.

Adnan Kavak was born in Usak, Turkey, in 1970. He received the B.S. degree from the Electrical and Electronics Engineering Department, Middle East Technical University, Ankara, Turkey, in 1992. He received the MS and PhD. degrees from the Electrical and Computer Engineering Department, The University of Texas at Austin, TX, USA, in 1996 and 2000, respectively. He was a satellite control engineer with Turksat Satellite Control Center, Ankara, Turkey, from December 1992 to May 1994. He worked as a Senior Research Engineer at Wireless Systems Laboratory, Samsung Telecommunications America in Richardson, TX, USA, from January 2000 to July 2001. He then joined Kocaeli University, Turkey, in August 2001 and worked as an Assistant Professor there until May 2005. Currently, he is the director of Wireless Communications and Information Systems (WINS) Research Center, and an Associate Professor with the Computer Engineering Department, Kocaeli University, Turkey. His current research interests include 3G and beyond wireless networks, software and cognitive radios, smart antenna systems, resource allocation in wireless networks, and wireless sensor networks.

Mustafa Karakoc was born on July 13, 1978, in Kutahya, Turkey. He received the B.S. and M.S. in Electronics and Computer Education Department from the Kocaeli University, Kocaeli, Turkey, in 2002 and 2004 respectively. He is currently pursuing his Ph.D. degree at Kocaeli University. Also, he was a research assistant with the Department of Electronics and Computer Education, University of Kocaeli, Turkey. He is currently working as a radio network engineer at Turkcell Telecommunication Services, Istanbul, Turkey. His research interests include smart antenna implementation for CDMA cellular networks, digital signal processors, array signal processing, and resource allocation in wireless networks.

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Halil Yiˇgit was born on August 15, 1977, in Kocaeli, Turkey. He received the B.S. and M.S. in Electronics and Computer Education Department from the Kocaeli University, Kocaeli, Turkey, in 2002 and 2005, respectively. He is currently pursuing his Ph.D. degree at Kocaeli University. Also, he has been working as a research assistant at the Department of Electronics and Computer Education, Kocaeli University, Turkey since 2003. He is interested in smart antennas, MIMO systems, array signal processing, and channel prediction.

Caner Ozdemir was born in Edremit, Turkey on March 29, 1971. He received the B.S.E.E. degree in 1992 from the Middle East Technical University (METU), Ankara, Turkey, and the M.S.E. and Ph.D. degrees in Electrical & Computer Engineering from the University of Texas at Austin in 1995 and 1998, respectively. From 1992 to 1993, he worked as a project engineer at the Electronic Warfare Programs Directorate of ASELSAN Electronic Industries Inc., Ankara, Turkey. From 1998 to 2000, he worked as a research scientist at Electronic & Avionics Systems (ASTG) group of Allied Signal Inc., Columbia, Maryland. He joined the faculty of Mersin University in 2000 and is currently an Associate Professor in the department of Electrical & Electronics Engineering, Mersin, Turkey. Dr. Ozdemir is a recipient of URSI EMT-S Young Scientist Award in the 2004 International Symposium on Electromagnetic Theory in Pisa, Italy. He is the co-author of the encyclopedia titled “The Wiley Encyclopedia of RF and Microwave Engineering”. Dr. Ozdemir’s research interests are radar imaging and radar signal processing, timefrequency transforms and antenna design.

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