A Real Time Implementation on FPGA of a Clutter Map CFAR Detector Mansouri Houria
Hamadouche M’hamed
Image Processing and Radar Laboratory University of Sciences and Technologies Houari Boumediene Algiers, Algeria
[email protected]
Infotronic Laboratory Boumerdes University Boumerdes, Algeria
Youcef Ettoumi Fatiha Image processing and Radar Laboratory University of Sciences and Technologies Houari Boumediene Algiers, Algeria
Abstract—In this paper we present the results of performance analysis in terms of real time implementation of CMAP-CFAR detector for radar targets of Swerling I type embedded in white Gaussian noise. So we expose the algorithm considered for its implementation on SPARTAN 3E XC3S500E FPGA card and the results obtained. Index Terms—CFAR; FPGA; Implementation; Radar
I. INTRODUCTION One of the most important problems in radar systems is to automate the detection of the target in a non homogenous environment with a minimum of false alarm, in particular for radar intended for airspace surveillance. The classic detection is based on a fixed threshold and need an experimented operator to take the adapted decision. The non stationary of environment makes the performances of the detector to be much degraded with a small variation of the level of the noise. The searchers think then about a new technique with an adapted threshold to the level of the noise and clutter maintaining a constant false alarm rate. This technique called Constant False Alarm Rate( CFAR) has been introduced first by Finn&Johnson[1].
In the present work, we have wanted to complete those studies with the implement ability of the detector on SPARTAN 3E XC3S500E FPGA processor[4], with respect to real time and requirements.
II. PROBLEM FORMULATION The architecture of CMAP CFAR detector is given in figure 1. It uses a first order recursive filter. A fraction α (between 0 and one) of the present sample is added to (1- α) of the previous estimate to form the new estimate. By using exponential smoothing instead of a moving window averaging, we store only the last previous estimate of the average of that cell instead of the last m inputs from one cell. The background estimate is formed from previous scans and for mth scan the output of the recursive filter is given by: m
y m (k ) =
∑
α .( 1 - α ) l . q m - l ( k )
l=0
Where qi is the output of the kth resolution cell.
In the most of those detectors, utilizes present inputs from neighboring cells to obtain the average background. The estimated value is used to set the threshold to which the present input from the cell under test is compared. A different approach to obtain CFAR based on clutter map exploits the intrinsic local homogeneity of the radar environment in which the detector output of each range resolution cell is averaged over several scans in order to obtain an estimate of the background level. Various literature references [2-3] have studied and showed the performances of the CMAP CFAR detector for different clutter or target models.
Figure 1. Diagram block of CMAP-CFAR detector
(1)
III. IMPLEMENTATION OF CMAP CFAR DETECTOR In most applications, the real time processing is very critical. Appropriate chooses must be made for the FPGA able to execute the work in real time. For our application we have choose to satisfy the requirements of classical pulsed radar with a pulse repetition frequency of 1200hz, 1µss pulse width. The period of the coherent processing interval is the critical time for the implementation of the proposal system. The radar video signal undergoes oes an analog to digital conversion of 16 bits.la sampling frequency is around ar 955 kHz, corresponding to the duration of a pulse. It is generated from the master clock of the FPGA. The proposed oposed architecture for the CMAP CFAR processor implementation is given in the figure 2.
Figure 3: Result of simulated process for α= 0.1
The SPARTAN 3E XC3S500E development kit provides a complete solution for developing designs and applications based on the Xilinx Spartan3 family. family An USB connector allows to connect it to the PC which contains the VHDL program which describes d the CMAP CFAR fonctionment. In figure 4, the FPGA kit used is presented.
Figure 4: Board with FPGA used for processing. processing Figure 2: Architecture of the implemented structure
As shown in figure 2, the implementation requires three multipliers, an adder,, one comparator and a RAM memory.
After the performed processing, the constraints for real time were defined.The total synthesis estimation parameters are presented in table 1.
Before implementation on FPGA card, we have done the work on modelsim 6.3f simulator[5]. We present in next section some results.
IV. RESULTS AND DISCUSSION DISCUSSIO Figure 3 shows one of results obtained by simulation: Those graphs have been deducted for a data set of 500 samples. They represents respectively from top to bottom, the generated signal with targets, the adaptive ive threshold, and the decision. We can see that all targets are detected.
Table 1: Synthesis summary for the CMAP CFAR processor targeted for a SPARTAN 3E XC3S500E FPGA device.
The obtained results show that the required resources are less or equal compared to available FPGA resources. We give in figure 5 the occupied area by all modules used.
Figure 5: result of the placement and routing
V. CONCLUSION In this paper, we have presented a real time implementation of a CMAP CFAR R detector.Based detector. on the reported synthesis result of the Modelsim simulator, and the FPGA board, we can conclude thatt the processor SPARTAN 3 is suitable for such signal processing.
REFERENCES [1]
[2]
[3]
[4] [5]
H.M Finn, R.S Johnson,"Adaptative detection mode with threshold control as a function of spacially sampled clutter level estimates,” RCA Review, Vol.29,September 1968,pp.414 -464. M.Hamadouche « Détection Adaptative CA-CFAR CFAR et CMAP-CFAR CMAP DE CIBLES Radar dans des Clutter Gaussien et Weibull distribués ». Thèse de Doctorat en traitement du signal 2001 (Université de Constantine) R.Nigberg « Clutter map CFAR analyse » IEEE Transactions on Aerospace and Electronic Systems, AES-22, 22, N°. 4, 4 pp. 419-421, July 1986. DS312 (v3.8) « SPARTAN 3E FPGA Family Data Sheet » www.Xilinx.com « ISE In-Depth Tutorial » www.Xilinx.com
