An FPGA implementation of real-time QRS detection - Semantic Scholar

International Conference on Computer & Communication Technology (ICCCT)-2011

An FPGA implementation of real-time QRS detection

H.K.Chatterjee

R.Gupta, J.N.Bera, M.Mitra

Dept. of ECE Camellia School of Engineering & Technology Kolkata India [email protected]

Dept. of Applied Physics University Of Calcutta Kolkata India [email protected], [email protected], [email protected] these equipments provide a continuous online display of heart rate for the physicians and medical staffs. FPGA is an integrated circuit designed to be configured by the user or designer after manufacturing—hence "fieldprogrammable". The FPGA configuration is generally specified using a hardware description language (HDL). The fast growing speed and circuit density of FPGAs have made them a significant player in domains earlier dominated by Application Specific Integrated Circuits (ASIC). Today’s FPGAs are fabricated using the latest 90-nm VLSI technology and chips are available with complexity as high as 5 million gates operating at speed of up to 500 MHz. Besides being used for general purpose logic design, modern FPGAs are equipped with building blocks for specialized applications such as DSP and embedded system design. FPGA architecture consists of an array of logic blocks called Configurable Logic Block, CLB. A logic block (CLB or LAB) consists of a few logical cells. A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a Dtype flip-flop. Logic blocks can be configured to perform complex combinational functions also include memory elements, which may be simple flip-flops or more complete blocks of memory. FPGAs implement static RAM based configurable logic blocks to perform configuration. Thus, to realize an overall function a large no of CLBs are interconnected. In recent years there has been considerable use of FPGA based system for ECG denoising [12], QRS detection [13] and feature extraction. In [14] a QRS detection algorithm is described which calculates the threshold of the next peak detection cycles from the median of eight previously detected peaks. This paper illustrates a real time QRS detection algorithm using an FPGA based embedded system. From the first 1500 samples, a slope threshold based rule is learned which are used for detection of the following peaks in the incoming data. At first, the algorithm is validated on MATLAB platform using synthetic ECG from Massachusetts Institute of Technology- Beth Israel Hospital (MIT-BIH) arrhythmia database (mit-db) and Physikalisch-TechnischeBundesanstalt (PTB) database under Physionet. Thereafter it is implemented on Xilinx Spartan2 FPGA where the synthetic ECG data is delivered to the FPGA using parallel bus of a personal computer (PC) using LPT1 port. The QRS

Abstract—This paper illustrates a simple algorithm for real time QRS detection from ECG data. The algorithm is implemented on Xilinx field programmable gate array using very small number of memory cells. Single lead Synthetic ECG using ptb-db database (from Physionet) is generated from a personal computer using the parallel port (LPT1) at 1 ms sampling interval and delivered to the FPGA (Field Programmable Gate Array) board. At first, from the first 1500 samples, the QRS detection algorithm calculates some characteristic amplitude and slope based signatures which are used to form a rule base. These rules are used for detecting the next incoming QRS regions accurately. The index points of Rpeaks are determined and shown in the LEDs using switchbased commands. Keywords-ECG, FPGA, QRs detection.

I.

INTRODUCTION

An electrocardiogram (ECG) represents cardiac signals generated by cardiac muscles. It is so far the most common method used by cardiologists for determining the cardiac functions. A typical ECG beat contains wave segments P, QRS and T which represents periodic depolarization and repolarization of atria and ventricles in a sequential manner. QRS, being the most striking segment of the wave form assumes special significance for cardiac signal interpretation. QRS duration represents the total ventricular depolarization time. In the domain of computerized ECG processing, QRS detection is one of the important and primary job and very often used for heart rate computation. Many of the popular ECG feature-extraction algorithms utilize QRS determination as their starting point. Till date, numerous QRS detection algorithms have been developed and successfully implemented. Initial approached involved digital filters and derivative based algorithms [1]–[4]. A morphological operator based peak value extractor is used for QRS detector [5]. Soft computational techniques like Hidden Markov model, Artificial neural Networks, genetic Algorithms, Support Vector Machines and many more have been used for more accurate QRS detections [6] –[9]. Some other approaches include zero crossing counts, syntactic methods [10]–[11]. For the last two decades, there is an increasing trend in the use of microcomputer based systems for biomedical equipments for heart rate computation. More and more portable devices are in use for ambulation analysis and bedside monitors in Intensive Care Units (ICU). Most of

978-1-4577-1386-611$26.00©2011 IEEE

274


Data Port Status Port Control Port

Trigger pulse train

8 Switches 8 LEDs Interfacing Unit

Start Capture

Parallel port ptb-db data file

Display Section

Data Capture & Analysis Section FPGA Xilinx Spartan 2

PC Figure 1: Block diagram of the system

regions (R-peak indexes) are stored in internal memory and displayed in on-board LEDs by used commands generated by switches. II.

Data send from PC parallel port (D0-D7)

MATERIALS AND METHODS

The real-time QRS detection algorithm is implemented on synthetic ECG data from Physionet. Block diagram of the developed system is shown in Figure1. To simulate the real time computing environment, a PC based system is developed where the digitized ECG samples are delivered at 1 ms interval to the FPGA board, using parallel bus. Single lead ECG is generated in digitized form PC and delivered to the FPGA development kit (Xilinx Spartan 2). The QRS detection algorithm embedded in the FPGA board detects the R-peaks and stores their indexes in internal memory. The Rpeak indexes are displayed in the display interfacing unit using switch based commands. The entire work is divided into two parts. First, generation of digitized ECG from ptbdb file. Second, development and testing of the algorithm in FPGA platform. These are discussed as follows:

Data accepted by FPGA (P108-111, P113-115, P119) Pulse train generated by FPGA (P121), & accepted by PC parallel port (S7)

“Start Capture” pulse generated by PC parallel port (C0) & accepted by FPGA (P120) Figure 2: Generation of ECG data by PC

B. Real time QRS detection from the ECG samples The first 1500 samples of the incoming data are used to form a rule base based on extracted signatures from the QRS zone. Also a characterization of QRS polarization, i.e., positive R peak or QS peak is performed, based on 20 point slope (actually, inter-sample difference), which is illustrated in Figure 3. ECG samples are stored in a group of memory cells (one cell captures 8 bit information) sequentially such that it holds the last 42 samples at any instant. This stack of 42 samples constitutes one of data. For each frame, the processing starts at 42nd sample, which is considered as current index point, and the 20th sample is considered as current point of reference. Then, 20 point slope is computed by calculating differences R42 – R21 and R20-R1, where Ri indicates ith sample. During the training zone (sample 11500), two group of slopes (i.e., positive going and negative going towards the current point of reference) are separately computed and a comparison in done to check out which one is dominant by a set of empirical formulae and the nature of QRS is ascertained. For determining the QRS rule set, 20-point average slope is computed continuously by calculating successive differences like R20-R19, R19-R18, R18-R17,….R2-R1 etc. and then using the following formula:

A. Generation of synthetic ECG from PC The synthetic ECG is generated from ptb-db file and delivered to the FPGA development board using parallel port. The ptb-db files contain ECG samples in mV range with 1 ms sampling interval. A single lead data is first normalized and converted to digital values with 8-bit resolution. A separate program is developed to store these quantized values in a separate data file. Now, to deliver these samples one-by-one to the FPGA board, a synchronous data transfer scheme is devised. The FPGA board generates a real time clock at 1 kHz frequency (by dividing the clock frequency of the SDK board). The data transfer scheme is illustrated in Figure 2. The transfer of data is initiated by a ‘Start Capture’ command generated from the PC at C0 pin (the 0 to 1 transition). On sensing this falling edge on C0 pin of PC parallel port (connected to P120 of FPGA), the FPGA board starts to transmit a pulse train through the status pin S7 of the LPT1(connected to the P121 of FPGA). On each rising edge of this pulse train, the PC delivers a sample on the parallel bus D0-D7). Each sample is accepted by the FPGA on the falling edge of the same pulse. This parallel transfer of digitized ECG perfectly simulates a real hardware-based ECG acquisition board consisting of amplifiers and analog to digital converter.

275


R42

R1

Current point of reference

Current index point

R20

R20

Current point of reference

Current index point

R1R42

Group II: Left side 20 pt. slope: R42-R21< 0 & Right side 20 pt. slope: R20-R1 > 0

Group I: Left side 20 pt. slope: R42-R21 > 0 & Right side 20 pt. slope: R20-R1 < 0

Average of both side slope: ( | R20-R40| + | R21-R0| )/2 Figure 3: Illustration of characterization of QRS complex

Slp =

∑R 20

i +1

20

−R

i

considered to be due to high frequency noise in that region. However, if this index difference is less than 30, it may be a case of RR’ peak. In such a case, the index of the preceding R-peak is replaced by the current R peak index. Each R-peak indexes are stored sequentially in two consecutive memory cells, in high order bye and low order byte. Due to memory limitation of the FPGA module, in the present work, each ECG dataset with 7000 samples is tested. The initial training is completed with first 1500 samples, and R-peak detection is performed with following 5500 samples. Nominally, 7 to 8 R-peaks are encountered in the total dataset. The algorithm flowchart for implementing QRS detection is shown in Fig.4. After the analysis is complete, the R-peak locations are indicated in the LED panel of the interfacing unit of the FPGA development board with the help of sliding type DIP switches. The FPGA development board has 8 LEDs and 8 dip switches. To indicate R-peak index, which requires a minimum of 13 bits, the group of 8 LEDs are used to show the higher and lower bytes separately. For example, DIP switch combination “00000000” shows the least Significant byte of time plane index of first detected R- wave peak in the LED panel, whereas dip switch combination “10000000” shows the most Significant byte of time plane index of first detected R- wave peak. Similarly DIP switch combination “00000001” shows the least Significant byte of time plane index of second detected R- wave peak and so on.

… (1)

The objective is to capture the rising edge of R-peak (or QS peak). If for two consecutive samples (Ri+1 – Ri) < 0, which indicates falling edge of a peak, the operation is discontinued for current frame of samples, and initiated for next frame. This approach saves computational burden. The average slope computation is carried out continuously for 21st to 1500th incoming samples and the highest value is retained both for positive and negative values. From this a slope threshold value is calculated, which is 75% of the maximum 20-point average slope. The rule base is formed by combining 20 point average slope with QRS character at the end of the learning zone. To be a probable QRS zone the slope at index i should match the following criteria: (a) Current 20 point average slope is greater than absolute value of R slope threshold (for positive as well as negative QRS) (b) 20 point slope at this point is positive going, i.e. towards the current index value (for positive QRS) or, negative going for negative QRS). (c) Current sample magnitude greater than the preceding one (for positive QRS); or less than the same of preceding one (for negative QRS). From 1501 samples onwards for each sample again last 20 point average slope is computed and the above conditions are verified. If all conditions are satisfied for a particular instant, it is concluded that a probable QRS zone is detected. These criteria are checked until the optimum (maximum value for positive QRS and minimum for negative QRS) amplitude of a sample is obtained, i.e., after the current index point a violation of condition (c) is achieved. The local maximum (for positive QRS) or the local minimum (for negative QRS) is taken as probable R peak. To confirm its candidature as a valid R-peak, it is checked whether the last detected R-peak index is 400 samples apart from the current index. If this condition is satisfied, the current R-peak index is taken as a valid Rpeak. Otherwise, the peak is ignored as valid R-peak and

III.

TESTING AND RESULTS

The QRS detection algorithm developed is tested using normal and abnormal data in MIT-PTB database and MITBIH arrhythmia database under Physionet. Validation of the developed algorithm is initially performed in the MATLAB platform. Here, single lead data consisting of 30000 samples from a standard ptb-db or mit-db file is taken in an array and normalized in 8-bit resolution, i.e., 0-255 range. To simulate the real time performance, at a time, only 40 ECG data are handled and for this, 40 variables are used to form a stack on first-in-first-out’ (FIFO) basis in the MATLAB platform.

276


start Initialize trg_flag =0; trg_ctr = 1500 Accept first 20 samples and store in cells R1,…R20; Compute avg. slope= slp1= Σ(Ri-Ri-1)/ 20 Initialize slpm = slp1

Accept next sample and compute slpi= Σ(Ri-Ri-1)/ 20 Is slpi > slpth ?

Is trg_flg= 1 ?

Y

N

Is slpi > slpm ?

Y

slpm = slpi

N

Compute 20 point abs slope R20a = R20-R1

Decrement trg ctr Is trg_ctr = 0?

Is (Slp20a> 0) & (sample)i> (sample)i-1 ?

N

Y

trg_flg = 1 slpth = 0.75* slpm Initialize data ctr = 5500

Y

Store index as probable R peak (ri) Is ri-ri-1 > 400 ?

Y

N

Is ri-ri-1