A Robust Phase-Locked Loop Algorithm to Synchronize ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 5, MAY 2008

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A Robust Phase-Locked Loop Algorithm to Synchronize Static-Power Converters With Polluted AC Systems Marcelo A. Pérez, José R. Espinoza, Member, IEEE, Luis A. Morán, Fellow, IEEE, Miguel A. Torres, and Ernesto A. Araya

Abstract—In this paper, a phase-locked loop algorithm appropriated for digital-signal-processor-based control implementations, where the operation of a static-power converter needs to be synchronized with an ac network, is presented. The proposed algorithm includes a multiplier, a filter, a feedback closed loop, and a numerically controlled oscillator stage. As a result, a discrete sine (and cosine) signal is generated in synchronism with the fundamental component of an external-reference (ER) signal. Moreover, the sampling period of the algorithm is adjusted at each sampling instant such that an integer number of sampling periods per period of the ER signal is ensured. This is the main feature, and it is achieved by using a discrete rectangular window filter and a discrete controller. The proposed algorithm code is simple, stable, and presents high noise rejection. A comprehensive theoretical justification and various rigorous experimental tests are included. Index Terms—Discrete-time systems, phase-locked loops, pulsewidth-modulated power converters.

I. I NTRODUCTION

P

ULSEWIDTH-MODULATED static-power converters that operate directly connected to an ac grid need to be synchronized with it. In other words, the gating pattern needs to be applied in synchronism with the periodic ac-supply voltages. This issue could become a tedious practical problem if the frequency of the ac grid changes even very little and slowly [1]. This is the case of most ac networks, where static-power converters are controlled by means of digital-based systems such as digital-signal processors. For instance, Fig. 1 shows a standard six-switch converter topology used in rectifiers, ac drives, unified power-quality conditioners [2], among others, where synchronization must be accurate and robust even under polluted ac voltages. An analog phase-locked loop could be used to generate an analog signal that is synchronized with a three-phase voltage

Manuscript received April 17, 2007; revised December 31, 2007. This work was supported by the Chilean Government under Project FONDECYT 105-0958. M. A. Pérez is with the Department of Electronic Engineering, Universidad Técnica Federico Santa Maria, Valparaíso, 110-V Chile (e-mail: [email protected]). J. R. Espinoza, L. A. Morán, M. A. Torres, and E. A. Araya are with the Department of Electrical Engineering, Universidad de Concepción, Concepción, 160-C Chile (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2008.918638

Fig. 1. Synchronization scheme of a three-phase boost rectifier.

supply [3], [4], a single-phase voltage supply such as an electronic ballast [5], or single-phase converters [6]. In addition, it is required to connect a distributed energy generator, such as a photovoltaic system, to the network [7]. Besides, phaselocked loops are used embedded into the control system [8] or in the power system [9]. A typical analog implementation is presented in [10]. Alternatives based in digital integrated-circuit approaches are reported in [11] and [12]. Efforts have also been done in order to improve the dynamic response to step changes in the frequency of the input signal [13]. However, when a digital-signal processor is used to implement the modulation and control algorithms, synchronization is usually achieved in software using techniques such as zerocrossing detection or the abc to dq transform. The first alternative is very sensitive to noise and pollution in general. The abc to dq transform [14], [15] is preferred in three-phase systems, in induction [16], and in permanent-magnet [17], [18] motor control, where the phase and amplitude of the input signal is required [19]. In some cases, such three-phase phaselocked loop approaches require more computation throughput and high sampling frequencies [20]. In addition, the sampling period is fixed, and it is not adjusted to have an integer number of sampling periods per cycle of the external-reference (ER) signal. This approach leads to jittering that is reduced by using a very small sampling period [21], which restricts the amount of code that could be run in every sampling routine. This undesired effect in digital phase-locked loop implementations is also produced by electrical noise in the synchronizing clock

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Fig. 2. Block diagram of an analog phase-locked loop.

[22]. This method has been adapted to unbalanced systems [23], [24]. Unlike other alternatives that are based on dq theory using software or custom hardware [25], which needs to implement adaptive approaches to deal with unbalances, this paper presents a single-phase phase-locked loop algorithm that is simple to implement. In fact, the controller used in the phaselocked loop becomes a single line of code, where the sampling period is adjusted such that we have the following: 1) an internal discrete sinusoidal signal is generated and synchronized with a sampled ER signal and 2) an integer number of sampling periods is achieved per each cycle of the ER signal. This last feature allows the modulation and control of staticpower converters at very low switching frequencies with welldefined voltage and current waveforms, an important feature in medium- and high-power applications where power quality is a big concern. Different from other approaches [23], the proposed algorithm uses a low-pass filter (LPF) that is actually a rectangular window filter (RWF) and uses a proportional integral controller, which simplifies its analysis and design without any penalties in the overall static and dynamic behavior. An exhaustive mathematical analysis shows the stability of the resulting system. As expected by its single-phase structure, the proposed phase-locked loop approach is not intended to operate under severe voltage networks failures. One application for this scheme is in single-phase converters, e.g., in railway traction. However, most of the converter topologies are not expected to operate under such conditions. Nevertheless, in power converters designed to operate under, for instance, single-phase faults or severe voltage unbalances, a robust type of three-phase phase-locked loop approach should be used [15]. Finally, the robustness of the proposed algorithm to face highly polluted ac voltages is tested using different rigorous experimental tests. Additionally, a three-phase boost rectifier is modulated using the proposed phase-locked loop algorithm under step changes in the ac-supply-voltage frequency.

Fig. 3.

Linearized model of an analog phase-locked loop.

Fig. 4.

Block diagram of the proposed phase-locked loop algorithm.

order to ensure perfect synchronization between the positions of θi (t) and θe (t). Because the ER signal is a ramp for a perfect sinusoidal waveform ue (t), such as in static-powerconverter applications, a proportional-integral controller such as c(s) = kp (1 + ki /s) is required. The proposed phase-locked-loop-algorithm scheme is shown in Fig. 4 and, basically, operates like the analog phase-locked loop; however, the sampling period T is modified in order to achieve synchronism. The algorithm samples the ER signal ue (t) providing the discrete ER signal ue (k). This is multiplied by the discrete IR signal ui (k) resulting in the signal u(k) and, then, filtered out using an RWF providing the output y(k) used to generate the error signal e(k). The controller provides the sampling-period signal T (k) used to define the sampling period of the next sampling. This approach ensures that the discrete IR signal ui (k) is synchronized with the ER signal ue (t), and therefore, the period of the ER signal ue (t) becomes an integer multiple of the sampling period T (k). The features and detailed operation of the approach are described as follows. A. Dynamic Model Considering the continuous ER signal ue (t) with a position θe (t) as ue (t) = Ue cos (θe (t))

II. P ROPOSED S OFTWARE -B ASED P HASE -L OCKED L OOP A LGORITHM The classic analog phase-locked loop is shown in Fig. 2, where the periodic ER signal ue (t) leads by 90◦ , the periodic internal-reference (IR) signal ui (t), and both feature identical frequencies in steady state. This is achieved by the combined operation of an LPF, a controller with impulse response c(t), and a voltage-controlled oscillator. The model can be linearized, and the resulting block diagram is shown in Fig. 3, where hLPF (s) and c(s) represent the transfer functions of the LPF and controller, respectively. Similarly, Ue and Ui are the amplitudes of the signals ue (t) and ui (t), respectively. Fig. 3 also shows that the condition y(s) = 0 must be guaranteed in

(1)

the sampled ER signal becomes ue (k) = Ue cos (θe (kT )) .

(2)

Similarly, the discrete IR signal with an arbitrary θi (kT ) position is defined as ui (k) = Ui sin (θi (kT ))

(3)

hence, the product u(k) is u(k) =

Ui Ue {sin [θe (kT )+θi (kT )]−sin [θe (kT )−θi (kT )]} . 2 (4)

Pérez et al.: ROBUST PHASE-LOCKED LOOP ALGORITHM TO SYNCHRONIZE STATIC-POWER CONVERTERS

Fig. 5.

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Linearized model of the proposed phase-locked loop algorithm.

Similar to the analog case and considering that the RWF eliminates the higher frequency components and behaves like a unitary gain at low-frequency components, the filtered signal is Ui Ue sin [θe (kT ) − θi (kT )] y(k) = − 2

Ui Ue [θi (kT ) − θe (kT )] . 2

(6)

The previous expression is linear, and therefore, the Z-transform can be used y(z) =

Ui Ue [θi (z) − θe (z)] . 2

(7)

On the other hand, the position of the IR signal is generated as θi (k) = 2πfo

k


T (i)

(8)

i=−∞

where fo is the rated frequency. In the Z-plane, the internal angle is 1 θi (z) = 2πfo T (z). 1 − z −1

or as a transfer function hRWF (z) =

(5)

and considering a very small difference in the positions, y(k) can be expressed as y(k) =

Fig. 6. Frequency response of the RWF.

1 1 − z −N y(z) = . u(z) N 1 − z −1

The gain of this filter is unitary for components in u(z), featuring zero frequency (hRWF (z) → 1 when z → 1) and is zero for harmonics in u(z) featuring frequencies 1/(N T ), 2/(N T ), . . . (Fig. 6). This becomes an outstanding feature, since the unwanted harmonics in the signal u(z) are located precisely at these frequencies. Such a feature ensures the total cancellation of such components and that only the dc component of u(z) is found in y(z). This validates the assumption of the ideal behavior of the discrete LPF. On the other hand, the implementation of the RWF [(11)] is simple, which minimizes the computational effort. C. Controller Analysis The ideal objective is to have y(z) = 0 for a ramp signal in θe (t) or θe (z) = T z −1 /(1 − z −1 )2 . From Fig. 5, this objective becomes y(z) =

−Ui Ue hRWF (z)(1 − z −1 ) 2(1 − z −1 ) + Ui Ue hRWF (z)2πfo z −1 c(z) ×

(9)

The simplified model of the proposed discrete phase-locked loop is shown in Fig. 5, where z −1 stands for the computation delay, and the expression of the transfer function of the RWF hRWF (z) is also included in order to be considered at the moment of the controller design and stability analysis.

(12)

T z −1 =0 (1 − z −1 )2

(13)

which imposes unrealistic constraints on the controller (c(z) → ∞, ∀z). An alternative goal is to obtain zero steady-state error. This is lim y(k) = lim (1 − z −1 )y(z) =

k→∞

z→1

1 −T =0 2πfo lim c(z)

(14)

z→1

B. Analysis of the RWF The LPF should filter out all the harmonic components. Due to the periodic characteristic of the signal to be filtered out, an RWF is proposed. The input–output relation for the RWF is y(k) =

1 N

k


u(i)

(10)

which requires limz→1 c(z) = ∞ that is achieved by an integral action in c(z). If c(z) = kp /(z − 1) is chosen, the characteristic equation of the transfer function y(z)/θe (z) is 1 + l(z) = 1 +

kp −1 2πfo Ui Ue 1 1 − z −N z z−1 1 − z −1 2 N 1 − z −1

where l(z) is the loop transfer function and can be simplified to

i=k−N +1

where the width of the window is N samples. We can also write (10) as y(k) = y(k − 1) + (u(k) − u(k − N )) /N

(11)

(15)

1 + l(z) = 1 + kp

zN − 1 Ui Ue πfo N (z − 1)3 z N −1

(16)

where, independent of N , at least one root of the closed-loop transfer function lies outside of the unitary circle (unstable root)

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Fig. 7. Root locus of the characteristic equation for the controller c(z) = kp /(z − 1). (a) kp > 0. (b) kp < 0.

Fig. 8. Root locus of the characteristic equation for the controller c(z) = kp (z − a)/(z − 1) for a = 0.75. (a) kp > 0. (b) kp < 0.

∀kp , as illustrated by the root locus shown in Fig. 7 for N = 4 due to the presence of a double pole in z = 1 (the third pole in z = 1 is cancelled by the zero in z = 1, provided by z N − 1 = 0). This result motivates the use of an integrator with a zero in the controller, such as c(z) = kp (z − a)/(z − 1), as discussed as follows. D. Controller and Stability Analysis The controller needs the integral part in order to ensure that the IR signal presents a position θi (t) identical to the position of the ER signal θr (t). We use the controller   z−a c(z) = kp (17) z−1

Fig. 9.

Key waveforms in the variable sampling-period algorithm.

and the corresponding discrete equation, considering e(z) = −y(z), is T (k) = T (k − 1) − kp y(k) + akp y(k − 1).

(18)

Finally, the characteristic equation of the transfer function y(z)/θe (z) becomes 1 + l(z) = 1 + kp

Ui Ue πfo (z − a)(z N − 1) . N (z − 1)3 z N −1

(19)

The root locus is shown in Fig. 8 for N = 4 and a = 0.75. Clearly, stable poles can be achieved for gains 0 < kp < kp max for 0 < amin < a < 1. Unfortunately, the values of both kp max and amin depend upon N , and their closed-form expressions cannot be obtained symbolically. In practice, a is fixed, and then, kp is chosen such that the step response of the block diagram in Fig. 5 provides an acceptable response for the sampling-time variable T (k). Note that Fig. 8(a) ensures the existence of a gain kp for a stable operation but also shows complex dominant roots in closed-loop leading to overshoots. E. Model Restrictions Both analyses are done with the assumption that small variations of the frequency are present in the ER signal. Additionally, the Z-transform requires a constant sampling period, which is not the case as the sampling period is adjusted, as shown in Fig. 9, in order to match an integer number of samplings per cycle of the ER signal. This restricts the validity of the

Fig. 10.

Simplified time diagram of the proposed algorithm.

analysis to slow variations of the frequency. This is a fairly valid assumption in ac networks. III. E XPERIMENTAL R ESULTS A. Setup The algorithm is implemented in a digital-signal-processor system based on the TMS320C30 using a timer-controlled interrupt. The tasks of the algorithm upon each interrupt are as follows: 1) sampling the ER signal; 2) updating the internal index; 3) multiplying signals; 4) applying the RWF filter [(11)]; 5) computing the controller function [(18)]; and 6) setting the new sampling period. The sample period T (k) computed at the instant k is used to set the value of the next sampling period, as shown in

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Fig. 11. Key waveforms of the phase-locked loop algorithm for 20 samples per period and an ER signal of (a) 45, (b) 50, (c) 55, and (d) 65 Hz.

Fig. 12. Key waveforms of the phase-locked loop algorithm for a 50-Hz ER signal and (a) ten samples per period and (N = 10) and (b) 40 samples per period (N = 40).

Fig. 10. This online change in the sampling period produces the adjustment in the frequency of the IR signal, reducing the frequency error between the ER and the IR signals to zero, and, moreover, results in an integer number of samples per period of the ER signal. As in analog implementations, the controller requires an initial operating sampling period close to the rated value, which is set to 1/50 Hz = 20 ms in this case.

The phase-locked loop algorithm sets the sampling period T (k) that becomes the timer’s interrupt period in the digitalsignal processor; however, the value stored in the timer presents a fixed resolution, introducing in the case of the TMS320C30 a jittering error of about 120 ns. Nevertheless, this can be further reduced since it depends exclusively of the hardware being used.

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Fig. 13. Key waveforms of the phase-locked loop algorithm for 20 samples per period and different ER signals. (a) 1 kHz added to the 50-Hz component. (b) Random noise added to the 50-Hz component. (c) 50-Hz component with fifth and seventh harmonics. (d) 12-pulse-type waveform.

B. Tests Figs. 11–13 show key steady-state waveforms of the phaselocked loop algorithm operation for different experimental tests. The ER signal ue (t) and the IR signal ui (t) are shown in all cases. This last signal is time-continuous, since it is taken at the D/A of the digital-signal processor and is generated in parallel with the IR signal ui (k) but using the cosine function. Therefore, under perfect tracking conditions, both the ER signal ue (t) and the IR signal ui (t) are in phase, which is easy to verify in the figures. The ER signal ue (t) is generated by a multifunctional programmable ac power supply that allows us to emulate most of the typical polluted ac supply voltages. Particularly, Fig. 11 shows the performance for various frequencies of the ER signal while keeping 20 samples per period (N = 20). The results show that the IR signal remains synchronized, and the number of samples is effectively 20. Fig. 12 shows the waveforms for a fixed-frequency ER signal but with a different number of samples per period. Clearly, the algorithm allows synchronization with very low sampling frequencies as well as high sampling frequencies. Fig. 13(a) and (b) shows that the proposed algorithm operates properly for ER signals that present multiple zero-crossings. This is due to the ideal filtering characteristic of the RWF; this is zero gain at the harmonic frequencies. Fig. 13(c) shows synchronization with a waveform containing fifth and seventh

Fig. 14. Key waveforms of the phase-locked loop algorithm for a step change in the frequency of the ER signal.

harmonics. These harmonics are usually found in the ac voltage networks that feed static-power converters. Fig. 13(d) shows synchronization with a 12-pulse waveform, such as the ac current of a 12-pulse three-phase diode-based rectifier. In both cases, the synchronization is successfully achieved, which ensures the proper operation of the phase-locked loop algorithm under extreme conditions. Fig. 14 shows the dynamic response

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power supply is connected to the load through a power transformer (not shown in Fig. 1). The waveforms shown are the ac supply voltage vsa (t) (phase a of the secondary voltage of the power transformer), the ac rectifier voltage vab (t), the sampling-period variable T (k), which is measured using the D/A converter of the digital-signal processor, and the supply line current isa (t). The exact instant of the change in the ac-supply frequency is indicated using the ↑ symbol in Fig. 15(a). Due to the frequency change in the ac supply and the open-loop operating feature, the supply current presents an overshoot, which explains the acsupply-voltage transient as consequence of the poor regulation of the power transformer. The T (k) waveform also shows a reduction in order to keep the N = 9 sampling periods independently of the ac-supply frequency. This feature is confirmed in Fig. 15(b), where the ac-supply voltages are at 50 Hz, and Fig. 15(c), where the ac-supply voltages are at 60 Hz. In both cases, the ac rectifier voltage vab (t) remains with nine pulses per period. This ensures a perfectly defined harmonic spectrum of the electrical variables and better power quality, which is an important issue in high-power applications. IV. C ONCLUSION In this paper, a software-based phase-locked loop algorithm and its implementation on a digital-signal-processor-based system are described. The algorithm determines the frequency of the ER signal, generates a discrete synchronized sine (and cosine) IR signal, and ensures an integer number of samples per cycle of the ER signal. The sampling period is updated in every sampling instant in a closed-loop fashion. The stability of the algorithm is ensured by the discrete controller and the ideal operation of an RWF. The code is simple, short, and requires minimum computational effort to be implemented. Rigorous experimental tests probe the robustness of the proposed algorithm. The results show that the algorithm is suitable for staticpower-converter applications that need to be synchronized with polluted ac voltage supplies. R EFERENCES

Fig. 15. Three-phase boost converter operating in open loop and using the proposed phase-locked loop algorithm for synchronization purposes (CH1: 100 V/500 mV; CH2: 100 V/20 V; CH3: 100 mV/100 mV, and CH4: 5 A/1 A). (a) Step change in the ac-voltage supply frequency from 50 to 60 Hz. (b) Portion of (a) in the constant 50-Hz range. (c) Portion of (a) in the constant 60-Hz range.

of the phase-locked loop algorithm for a frequency step change from 47 to 53 Hz in the ER signal. The system shows a response time of about 125 ms to track the new frequency (similar to [23]). Although this could be excessive, the frequency changes in the ac network are not expected to change in steps. Fig. 15(a) shows the waveforms of the standard six-switch converter topology shown in Fig. 1, operating in open loop while a step change in the ac-supply-voltage frequency is produced (from 50 to 60 Hz). Like in the previous tests, the ac voltages are generated by the multifunctional programmable ac power supply, which can produce sharp step changes. The

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José R. Espinoza (S’92–M’97) was born in Concepcion, Chile, in 1965. He received the Eng. degree in electronic engineering and the M.Sc. degree in electrical engineering from the University of Concepcion, Concepcion, in 1989 and 1992, respectively, and the Ph.D. degree in electrical engineering from Concordia University, Montreal, QC, Canada, in 1997. Since January 2006, he has been a Professor with the Department of Electrical Engineering, University of Concepcion, where he is engaged in teaching and research in the areas of automatic control and power electronics. He has authored and coauthored more than 100 refereed journal and conference papers and contributed to one chapter in the Power Electronics Handbook (Academic, 2007). Dr. Espinoza is currently an Associate Editor of the IEEE TRANSACTIONS ON I NDUSTRIAL E LECTRONICS AND P OWER E LECTRONICS .

Luis A. Morán (S’79–M’81–SM’94–F’05) was born in Concepción, Chile. He received the Eng. degree in electrical engineering from the University of Concepción, Concepción, in 1982, and the Ph.D. degree from Concordia University, Montreal, PQ, Canada, in 1990. Since 1990, he has been with the Electrical Engineering Department, University of Concepción, where he is currently a Professor. He has extensive consulting experience in the mining industry, particularly in the application of medium-voltage ac drives, large-power cycloconverter drives for SAG mills, and power-quality issues. His main areas of interests include ac drives, power quality, active power filters, flexible ac transmission systems, and power-protection systems. He has written and published more than 25 papers on active power filters and static var compensators in various IEEE TRANSACTIONS . Dr. Morán was an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS from 1997 to 2001. In 1995, he was the recipient of the IEEE Outstanding Paper Award from the Industrial Electronics Society for the best paper published in the TRANSACTION ON INDUSTRIAL ELECTRONICS. In 1998, he was the recipient of the City of Concepción Medal of Honor for achievement in applied research. He was recently appointed as Distinguished Lecturer of the IEEE from January 1, 2008 to December 31, 2009.

Miguel A. Torres was born in Concepción, Chile, in 1978. He received the B.Sc. and M.Sc. degrees from the University of Concepción, Concepción, in 2002 and 2007, respectively. In 2003, he was with Laboratoire de Signaux et Systemes, Ecole Superieur d’Electricite, Paris, France, where he worked in passivity-based control applied to electrical systems. He is currently with the Department of Electrical Engineering, University of Concepción. His research interests include staticpower converters, high-voltage dc systems, and DSP applications.

Marcelo A. Pérez was born in Concepcion, Chile, in 1976. He received the Eng. degree in electronic engineering and the M.Sc. and D.Sc. degrees in electrical engineering from the University of Concepcion, Concepcion, in 2000, 2003, and 2006, respectively. He is currently a Postdoctoral Researcher in the area of efficiency improvement in multilevel converters with the Department of Electronic Engineering, Universidad Técnica Federico Santa Maria, Valparaiso, Chile.

Ernesto A. Araya received the B.Eng. degree from the Universidad de Concepción, Concepción, Chile, in 2000, where he is currently working toward the M.Sc. degree. He has published several papers related to digital control and virtual sensors in the power-electronics area.