A Segmented Thermometer Coded DAC with Deterministic Dynamic Element Matching for High Resolution ADC Test Hanjun Jiang, Beatriz Olleta, Degang Chen and Randall L. Geiger Department of Electrical and Computer Engineering Iowa State University Ames, IA 50011, USA
[email protected],
[email protected],
[email protected] and
[email protected] ABSTRACT—Dynamic element matching (DEM) is an effective way to achieve good average performance in the presence of device mismatch, yet it has not been widely adopted because of the time-local stationarity of the signal path. This paper presents a DEM approach to ADC testing in which low precision DEM DACs are used to generate stimulus signals for the ADCs under test. A deterministic DEM (DDEM) switching scheme is applied to a segmented thermometer coded DAC architecture. Detailed simulation results are presented to verify the expected performance of the proposed testing approach. The new approach is able to accurately test ADCs with linearity that exceeds that of the original DAC used as the signal generator. The new architecture is suitable for production test and built-in-self-test (BIST) environments where high linearity ADCs are difficult to test and characterize.
I. INTRODUCTION Due to increasing resolution and conversion rates, the challenge of testing analog to digital converters (ADCs) is growing [1]. Testing techniques that facilitate a reduction in the test cost would have a significant impact. Built-in-self-test (BIST) structures offer the potential to reduce cost while also adding value to the circuits under test. BIST schemes can be used for self-calibration and hence improve circuit performance. Most existing approaches have been aimed at duplicating a standard tester on chip [2], in other words, to produce a highly accurate and linear stimulus on the chip. However, the prior arts have not demonstrated linearity adequate for testing high resolution ADCs on-chip. A new approach relaxes the linearity requirements on the signal generator and uses signal processing techniques to accurately characterize the device under test (DUT). The mathematics behind linearity testing of ADCs using non-linear signals was presented in [3], where a nonlinear stationary excitation and its shifted replica are needed. In [4] a more rigorous analysis of the methods actually used and the new approach was done by the authors with simulation and experimental results included. In this paper dynamic element matching (DEM) is applied to low linearity DACs so that they can be used to test high-resolution ADCs. Due to process variation, element mismatching errors are inevitable. Although special layout techniques, special processes, and/or laser trimming can be used to reduce matching errors, these methods lead to significant cost increases. The DEM technique accepts mismatching errors as inevitable and dynamically rearranges the interconnections of the mismatched elements so that
on the average the output values are linear. The DEM method was used by various researchers [5-9] to improve the effective specifications of linearity performance of DACs. Most researchers use DEM in Delta-Sigma Converters. Our application of DEM allows the signal generator for ADC testing to be realized with a low-linearity DAC, eliminating the need of large silicon area and careful design of the test signal generator. A preliminary study investigated the use of random DEM with a highly-nonlinear DAC to test low-resolution ADCs [10]. The idea behind DEM testing is to generate more than one DAC output samples as the ADC testing stimulus with a given DAC input digital word; each sample picks different elements following the DEM philosophy. Since DEM is used in the input signal generator we do not have to worry about DEM in the signal path. Deterministic DEM was introduced and compared with the random DEM (RDEM) testing in [11] using a thermometer coded current steering DAC. It was shown that the DDEM significantly outperformed RDEM. As an added benefit, the circuit complexity is reduced because no randomizer is required. However, when high resolution DACs need to be implemented, due to the large number of current sources and high complexity of switching logic, building them using the thermometer coded architecture is impractical. The design is not trivial and a large area is required. A simpler DAC architecture that maintains the benefits of the DAC used in [11] needs to be developed. The segmented thermometer coded architecture was chosen. Each segmented array (MSB and LSB) will use DDEM, as explained later in this work. This paper is organized as follows. An explanation of how ADC INL is calculated is given in Section II. Details are presented in Section III about the DDEM segmented thermometer coded (STC) DAC architecture while in Section IV simulation results for high resolution ADC testing are shown and discussed. Section V concludes this work.
II. INL CALCULATION There are several alternative but similar definitions of the INL of an ADC. In some cases, the INL is defined as a continuous function of the ADC input voltage, whereas in other cases, the INL is only defined at the ADC’s transition points Tk, thus resulting in a discrete function INL[k], or denoted as INLk. In this paper, we follow what is most commonly used by industry test engineers and use the transition point INLk to characterize the ADC’s linearity performance. To define the INLk of the ADC, we first need the transition points of an ideal linear ADC which are usually defined as the endpoint fit line transition points Tk: T − T0 Tk = T0 + N − 2 k, k = 0 ,1... N − 2 (1) N −2
Equation 1 represents a straight line connecting the first and last transition points of the ADC, as seen in Figure 1. Actual transition points of an ADC are compared to their corresponding endpoint fit line transition points for linearity characterization. The difference between the actual transition points and the fit-line transition points is defined as INLk and is expressed in LSBs. INLk is defined mathematically by: INLk =
Tk − Tk 1 LSB
=
Tk − T0 ( N −2)−k T N −2 − T0
(2)
k = 1, 2... N − 3
Notice that by definition the INLk for the first (k=0) and last (k=N2) transition points are 0 and they do not appear in (2). 111
T5 110
T4
T6
Code output
101
T3 Fit-line
T1 010
T0
source element out of the total N elements, and p represents the number of samples to be generated for each DAC input word. p is also termed as the DDEM iteration number. All current sources are arranged conceptually along a circle to visualize the wrapping effect (physical layout of the current sources can be a rectangular array). p starting places that are q = N / P current sources apart are selected. Then, for each input code k, the DAC generates p samples of output where each sample is obtained by switching k current sources consecutively starting from one of the p starting places. The dth ( 1 ≤ d ≤ p ) sample is obtained by switching k current sources starting from i( d −1 )q +1 in the clock-wise direction. The output analog signal is obtained by forcing the summation of the selected k current sources to drive a resistor RF.
nL represents the less significant bits. If we let N M = 2nM and
011
N L = 2 n L , we have N = 2n = N M ⋅ N L . For a DAC input code k, we can break it up as following:
INL2
001
element to the DAC, so that now the DAC has totally N = 2 n current sources. We use i j ( j = 1,..., N ) to represent the jth current
For an n bit current steering DAC, we can divide the n bits to two parts: n= nM+nL, where nM represents the more significant bits and
100
T2
[11] on a thermometer coded (TC) current steering DAC. To perform the DDEM method, we add one more extra current source
000
0 ≤ k ≤ N − 1, 0
0.25
0.5
0.75 1 Input voltage
1.25
1.5
1.75
k = kM N L + k L
The most commonly used method for ADC INL testing is the standard histogram method and that is also the method that we will use in this paper to test ADC linearity. In the standard use of the histogram method, an ideal linear ramp is presented to the input of the ADC. The ADC takes samples of the input and the converted output codes are tallied into corresponding bins. Since Vin is proportional to time and the sampling intervals are constant, the total number of accumulated samples is proportional to Vin. Therefore a transition voltage is proportional to the total code hits for all output codes corresponding to lower voltages, and the accumulated histogram counts can be directly used to compute the INLk of the ADC. Naturally, in order for this method to work, it is imperative to have a highly linear ramp, with linearity a decade or more better than the resolution of the ADC under test, since any nonlinearity in the input signal will be directly translated into INLk estimation error in the histogram method. If the ramp is generated using a DAC, it is required that the DAC have resolution and linearity that are at least 3 bits more than the targeted resolution of the DUT. This is a fundamental challenge in both production test and built-in-self-test of high resolution ADCs. The DDEM approach is proposed as a solution to this problem. The DDEM approach is used to provide stimulus generator with adequate statistical linearity for ADC testing while keep the cost at a much lower level.
III. DDEM METHOD FOR SEGMENTED THERMOMETER CODED DACS In this section we will describe how we apply DDEM to a STC DAC. First we will review the DDEM switching scheme as used in
0 ≤ k M ≤ N M − 1,
(3)
0 ≤ kL ≤ N L − 1
Figure 1. A non-ideal ADC transfer curve and its endpoint fit line
To get the analog signal corresponding to k, we can obtain the analog signals corresponding to kM and kL with different weights respectively first and then combine them together. To implement this, we can use a MSB current source array to generate kM and use a LSB current source array to generate kL. Here the MSB and LSB array have NM-1 and NL-1 current source elements respectively, and the weight of each MSB array element is NL times that of a LSB array element. A 4-bit STC current steering DAC is shown in Figure 2 as an example. In this example, n=4, nM=nL=2 and NM=NL=4.
RF S1M S2M 4I
S3M 4I
MSB array
4I
S1L
S3L
S2L I
I
VOUT I
LSB array
Figure 2. A 4-bit segment coded current steering DAC structure
To implement the DDEM for a STC DAC, we only need to apply DDEM to both the MSB array and the LSB array simultaneously. We add one extra current source element for both the MSB and LSB array, then the MSB array has NM current source elements and the LSB array has NL currents source elements. We use iM , j ( j = 1,..., N M ) to represent the jth current source element out of the total NM elements of the MSB array and iL , j
( j = 1,..., N L )
to represent the jth current source element out of the total NL
q L = N L / p respectively.
Suppose now that the DAC input code is k = k M N L + k L and that each code needs to have p output samples; then, in order to generate each output sample for a code k, the DDEM method picks kM current sources from the MSB array and kL current sources from the LSB array by applying DDEM switching scheme to the MSB and LSB array respectively. Figure 3 illustrates the current source switching scheme for an 8-bit STC DAC. In this example we have nL=nM=4 and NL=NM=16, and p is selected to be 2. For each input code k, 2 samples are output. In Figure 2, k=191=11×NL+5, hence kM=11 and kL=5. For the 1st output sample, iM1~iM11 are selected from the MSB array and iL1~iL5 are selected from the LSB array; for the 2nd output sample, iM9~iM16 and iM1~iM3 are selected from the MSB array and iL9~iL13 are selected from the LSB array. I ((k )1
iM 1
iL1
iM 2
iM 16 iM 15
iL 2
iL16 iL15
iM 3 iM 4
iM 14
iL 3 iL 4
iL14
respectively and also a 1% matching error between the LSB and the MSB arrays was included. To simulate the actual test environment, noise was also added to the DAC output, and this noise could be as big as ± 3 LSBDAC. Figure 4 shows the INL distribution of the 1000 simulated ADCs. A STC DAC with an original INL equal to 38 LSB is simulated, which means that the actual DAC linearity is less than 12 bits. The DDEM approach is then applied to this DAC and the outputs are sent to the ADCs. In the simulation, p was set to be 128. We estimate the INL for each ADC based on the histogram with these inputs and calculate how much it deviates from the true ADC INL. The results are shown in Figure 5.
100 90 Frequency of Flash ADC INL
elements of the LSB array. Each DAC input code k has p output samples. As what we did to a TC DAC, we choose p index elements from each array distanced by q M = N M / p and
80 70 60 50 40 30 20 10
iM 10
iM 8
iM 9
MSB array
iMj = 16iLLd ( j = 1,...,16 d = 1,...,16)
iL10
iL 8
5
5 .7 5
15
6
.9 0 14
6 .2 0
.0 5 14
7
.3 5
8
7 13
12
.5 0
.6 5 10
11
9
8 9. 80
9
8. 95
0
9
8. 10
.0 17 0. 02 4 0. 06 4 0. 10 4 0. 14 4 0. 18 5 0. 22 5
-0
57
-0
.0
97
78
37
.0 -0
.3
.3
.1 -0
iL11
Error in the INL estimation [LSB]
i L9
LSB array
(b) 2nd output when D=191 Figure 3. DDEM switching of a 8-bit STC DAC
The described DDEM STC DAC requires DDEM cyclic switching sequence on both the MSB and LSB arrays. Since the resolution of the two arrays are both quite low, the DDEM control logic complexity can be maintained at a low level.
IV.
7. 25
0
-0
iL 7
-0
iM 7
iM 11
6. 41
10
.1
iL 6
i L12
20
79
iM 12
iL 5
iL13
30
-0
iM 6
I L (k L )2
18
iM 5
i M 13
I M ( k M )2
40
58
iM 14
iL 4
iL14
50
.2
iM 4
iL3
.2
iL15
iM 3
60
-0
iL 2
iL16
70
-0
iM 15
iL1
I ((k ) 2
iM 2
80
98
LSB array
(a)1st output when D=191 iM 1
0
Figure 4. INL distribution for 1000 flash ADCs
i L9
39
MSB array
iM 16
1
iL 8
iL10
.2
iMj = 16iLLd ( j = 1,...,16 d = 1,...,16)
iM 8 iM 9
Flash ADC INL [LSB] iL 7
iL11
Frequency of ADC INL estimation error
iM 10
iL 6
iL12
iM 7
iM 11
3. 86
3. 01 iM 6
iM 12
1
0 5. 56
iL5
iL13
4. 71
IL ( k L )1
2
I M (k M )1
-0
iM 5
iM 13
SIMULATION RESULTS
For the following simulation results, the ADCs have 16 bit resolutions while the STC DACs have 18 bits of resolution with a 9-bit MSB array and a 9-bit LSB array. The simulated ADCs have varying INL errors. The original DACs have an effective number of bit (ENOB) much less than 18 since there are large mismatching errors for the current elements inside the MSB and LSB arrays
Figure 5. INL estimation error distribution using a DDEM STC DAC
From Figure 5, it can be seen that using the DDEM STC DAC the error in the INL estimation is between -0.39 and 0.2 LSB. The degradation in performance compared to previous work [11] may be attributable to LSB and MSB matching error. The degradation in estimation is only a factor of 2 while the circuit complexity was significantly reduced. The resultant structure is suitable for BIST applications. In that case each ADC has a particular DAC to test it. To emulating the BIST environment, 1000 DAC-ADC pairs are simulated. The DACs have the same errors as before, while the ADCs used have an INL distribution as shown in Figure 6. As can be seen the ADCs to be tested are actually 16 bit linear since their INL is not bigger than ½ LSB in most of the cases. The DACs used for testing these ADCs have linearities of 12 to 13 bits without DDEM, which is actually 3 bits less than the linearity of the DUT’s.
V.
Frequency of flash ADC INL
120 100
A deterministic dynamic element matching (DDEM) approach was proposed on a segmented thermometer coded (STC) DAC structure for ADC testing purpose in this work. Simulations were used to validate this architecture. Simulation results showed that the approach is reliable to test high resolution ADCs. The architecture is suitable for BIST applications because it requires small area and uses a simple switching scheme to implement. The performance of the new DDEM STC DAC is similar to the DDEM TC DAC presented in previous work and can be successfully employed.
80 60 40 20
0. 17 8 0. 23 2 0. 28 6 0. 34 1 0. 39 5 0. 44 9 0. 50 3 0. 55 7 0. 61 1 0. 66 5 0. 72 0 0. 77 4 0. 82 8 0. 88 2 0. 93 6 0. 99 0
0
Flash ADC INL [LSB]
Finally we should point out that high resolution ADCs were successfully characterized using a DAC with original linearity 3 bit worse than that of the DUTs.
Figure 6. INL distribution for 1000 accurate ADCs Frequency of ADC INL error estimation
100 90 80 70
REFERENCES
60 50
[1]
40 30 20
[2]
10
-0 .6 03 -0 .5 67 -0 .5 30 -0 .4 94 -0 .4 57 -0 .4 21 -0 .3 84 -0 .3 48 -0 .3 11 -0 .2 75 -0 .2 38 -0 .2 02 -0 .1 65 -0 .1 29 -0 .0 92 -0 .0 56
0
[3]
INL error estimation for DAC-ADC pairs [LSB]
Figure 7. INL error estimation for DDEM STC DAC and ADCs 1000 pairs
Figure 7 shows the simulation results for the 1000 DAC-ADC pairs. We can see that the estimated INL has an error of less than ½ LSB for a majority of the cases. This test verifies that the technique is suitable for BIST applications. More simulation was done to verify the reliability of the proposed technique as a test tool. In this simulation we tried to find if the ADC INL is underestimated using the DDEM STC DAC. We simulated 1000 ADCs with INL around 0.5 LSB (Figure 6). The DAC used to estimate the ADCs’ INLs has an INL equal to 38 LSB and p= 128. Assume that the ADCs need to have less than 0.8 LSB INL in order to comply with their specifications, so the testing boundary to say that a part is a good part is below 0.8 LSB. The parts that have INL between 0.8 and 2 LSB are classified as “not so good” (NSG) parts and can be still marketed as less accurate parts. We can see in Figure 8 that although some good parts are tested as NSG ones, there are no NSG parts classified as good ones, which means that the customer will not receive a deficient part.
Estimated ADC INL [LSB]
[4]
[5] [6] [7]
[8]
[9]
[10] [11]
1.2
1
Good tested as not so good
NSG tested as NSG
0.8
0.6
[12]
[13] Not so good tested as good
0.4
0.2
Good tested as good 0 0
SUMMARY
0.2
0.4
0.6
0.8
1
1.2
Actual ADC INL [LSB]
Figure 8. DDEM STC DAC used as a production tester for 1000 accurate flash ADCs
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