A tool for Execution Time Hardware Debugging with ...

A tool for Execution Time Hardware Debugging with very low overhead: UNSHADES-l M.A:Agujrre. J,N. Tombs, A. Torralba and L.G. Franquelo Electronic Engineering Dpt. Escuela Superior de Ingenieros. University of Sevifla cI Camino de los Descubrimiento$ sin 41092 Sevilla (SPAIN) {aguirreJon,torralba,leopoldo}@gte.esi.us.es

Abstract.- Advil c:ed Field Programmable Gate Arrays (FPGA's) ell bOlt huge circuit models at bla;h speed clock rates. These devices are I te uvely used i Rapid Prototypl & sy.lerruJ. They have olber reatures tbat a re useful for obtaI I g I formado about th~ cirtuit duri g its executlo . This papen prese ts UNSElADES-I, II hardware/software tool that uploit tbe the reeo Dguratio !Cherne of Virtu fiTGA Tech ok/gy, solvt g ovscrv.lbWty II d (0 trollablUty of tbe ellisl. The syltem ca be evaluated " 0 ihe Oy", tald g I to attou t situltio 5 that sre diffICult 10 desulbe I tertWI AI ute.- Jot mmll\i a do with :I classkal liimulatAT, I 1Ilb paper du cribe tbe UNSHADES- I system a d it's [ocuKd oa tlle set of iOft:wan tools tbat provide easy IWI agenu: t . d access to tbJa executio time I lormatio . Keyword5,~

FPGA,

Hardware

Debuggi g,

Partial

Teconft&UTatlo

J. HARDWARE DEBUGGI G Software debugging norma1iy provides a set of tools that can help the p rogrammer to dive through the running code and inspect the contents of the variables during the execution (on step-by-step). All this information is linked to the high level source code (such as C, C++, BASIC, .. ,). Software debuggers provide 11 means of selecting breal.."J)Oints where tbe execution will be stopped and the code can be inspected. When a breakpoint is reached, then the software caD be run step by step, run to the next breakpoint or run uod l tilt: conclusion oftbe exc:cution.

In our hardware debugging coocept, different than (I], we try to reproduce the software debugging model, because of its close link betw~ · the designer and the running code. Other approaches Cl\a be found in the literature and tIle market are Xilinx ILA. Chipscope, lbits Hwif, ... Those tools are based' on the approach of synthesizes an in-device iOg1c analyzer and tbe conditions for triggering and the recorded signals need to be foreseen during

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coding stages. In our approach we use an interactive dialog between the FPGA and the host computer. The main objective consists in obtaining a hardware scenario that can interchange the infonnation between the emulator system and the man-machine interface in a comprehensive way. Once the hardware problem is solved, the development of a sel of tools to providing cOIltrol ,and managc hardware data will be a simple task.

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This presents the platfonn UNSHADES- I that means UNiversity of Sevi\la HArdware DEbugging System. UNSHADES consists in a bRl"dware platform based on a Xilinx Virtex device and a set of software tools running on a personal computer. Using a sufficiently . fast link configuration, run-time and control bitstrearns are down and uploaded whil st the Virtex FPGA emulates tbe digital circult runniog in the system. The emulation device has some built-in features the are suitable for our purpose. Initially tbey were provided as a system for checking the FPGA consistency in its configuration and contents in speci al conditions like space applications. We use the SelectMap [3] configuration bus, the partial reconfisumtion procedures and the system state capture features. The SelectMap interface is a Xilinx exclusive, 8 or I bit wide, high speed and bidirectional bus thal can be used for accessing to internal contents of the Virtex devices. The device confi guration, memory contents and the flip- flop (state) contents can be read or written in a chip-wide or partial way. Partial access can accelerate the downloading or uploading process as only the locations needed are inspected or modified, the Xilinx design flow provides a map with enough infonnation about the physical locarion of the signals which permits calculate and modify the device with. partial reconfiguration. T he c apture system is a sp ecific circuit included in the FPGA. The circuit can be described as follows: every flip-flop has ,Ill associated memory cell that i~ not included in the general purpose programmable resources. The contents of all the flip-flops can be transferred to their associated memory cell by mcans of a single clock cycle mechanism called capture. This .process provides a means of taking a

snapshot of the entire device state using a run-time con it ion. Finally, using SelectMap, the snapshot state can be transferred to a computer and the signal information mappe back to the original names given in the early esign stages. This mechanism is the base of the UNSHADES system. Har ware an software is built aroun the basis that during execution-time, information can be captured, accessed, uploaded an linked with its comprehensible high level esign name. The mechanism oesn't affect the normal execution of the evice and is escribed in detail in [6]. The timing and the resource count are not affecte because the capture mechanism doesn't use the common FPGA resources an the esign does not compete for the best routes an tracks with the ebugging system. Once the special properties of the selected hardware emulation system has been outline 'the har ware ebugger is simple. It consists of a software system that controls all the internal ata transfer, map an emap bits, generates the a equate slices of configuration bitstrearns and produces information in a comprehensive way for building the man machine interfaces.

II. UNSHADES.:1

HARDWARE. HIGHLIGlITS OF THE

EMULATION SYSTEM

UNSHADES har ware consists of a boar with two FPGAs:The emulation system (the VlRTEX FPGA) calle S-FPGA an a smaller FPGA with fixe configuration, calle C-FPGA that performs the transfer tasks (protocol a aptation an others) with the host PC. More etaile information woul ' be foun in http://www.gte.us.es/-aguirreihades.html. One of the tasks of the C-FPGA is relate to the control of some general purpose 10 lines that can be used for to provide extra control over the emulation system, if needed. These 10 lines are useful for some particular tasks relate to the ebugging system. Two ofthese tasks are: • Launch the capture system directly from the Pc. In this case selected variables can be inspected in an asynchronous W&y. In this case one 10 line from the C-FPGA and one 10 line from the SFPGA are hardwired. • Using an exclusive twq 10 lines metho [2], the execution can be controlle , run until a break con ition, run a single clock step an execution resume. When a break con ition (from now event, internal con ition that launches the capture system) is satisfie , the normal evolution is halte an the S-FPGA is frozen. Note that the

circuit and the surroun ing components of the system loose synchronism. Finally there's a new type of tasks that woul provi e new para igrns in testing an ebugging of large igital systems: • Exploiting the partial reconfiguration features an using the property that the bitstream file organisation is not co e but structure we've developed a method for altering the contents of individual flip-flops. This novel feature has been perused by many researchers over the last few years for large capacity FPGAs. Some non-commercial FPGAs such as the Xilinx XC6200. [4] series an FIPSOC [5] where available in the past to provi e this kin of operations, but no commercial devices provide a direct means for run-time modification of a flip-flops contents.

III. UNSHADES-l SOFIWARE. THE RUN-TIME CAPTURE AND SCHEME SYSTEM.

From software point of view UNSHADES is fully integrate into the Xilinx stan ar esign flow. Two files are nee e for full integration of UNSHADES into the system: the bitstream file an the bit allocation file. The first is necessary because the configuration process is controlled by the UNSHADES software and the secon is the map that provides the information about where every register is placed across the S-FPGA core. Hence, there's a link between the physical information and their names given 'uring the high level esign stages, in other wor s, it provi es a method for closing the loop for full backnotation. The execution time information can be isplaye using comprehensive names. The primary task of the software consists of taking the low-level bitstream information an associating it to busses an registers. The UNSHADES software provi es a graphic user interface (GUI) that presents a scheme of the registers and bits, associated with their last capture value. Figure 4 shows a snapshot of the UNSHADES GUI. Lines an arrows give information about ata flows and are added by the users as a visual aid. The example shows a small 8-bit micro controller being emulate in a Virtex XCV50. A. External nap hot The simplest ebugging tool is to take snapshots 'using an external line (figure 1, b). The PC sends a signal that requests that the Virtex launch the capture mechanism. An external 10 line is use to initiate the capture an the S-

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FPGA continues to operate at all times at the design peed. After capture, the UNSHADES oftware upload the information to the PC and presents it in the GUI.

RUN·TIME CONDITIONS

'FPGA

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f------jCE

STEP BY STEP

Note that in this mode the overhead is reduced to a snapshot line that would be linked with the external pin. And the effect on the circuit behavior is negligible. A natural extension of this tool is to launch the capture macro every certain amount that i programmed. The designer will have information about the evolution of elected ignal . Al 0 the information can be recorded into a file to provide di play in a waveform viewer. The aim of this tool is to ob erve the evolution of the y tern that ha , low variables' like state variables in power y tern controller or to capture the y tern tate once a de ign under emulation ha begun to operate incorrectly.

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'FPGA

I

f---j)(\----+I CAP CAPTURE_VIRTEX

a)

b)

Figure 1. Capture macro and external snapshot

B. Single clock cycle evolution. The system evolution can be frozen when a run-time event is atisfied. Run-time condition have to be foreseen at design time. They can refer to register contents that have enough interest for to be tudied. U ually they're comparisons with bus values or bits. More complex condition can be introduced that are combined with temporal condition. All Virtex flip-flops that belong to the design under debug can be controlled by mean of a 'clock enable' input. Using' this pin the y tern evolution can be totally or partially frozen without any risk of malfunctioning due to glitches or clock kew. If the 'clock enable' input is only asserted during a single clock cycle, the y tern will perform a 'ingle tep' evolution. In UNSHADES y tern an external 10 line, called 'debug clock' is used to allow the software to single step the S-FPGA. For this option, a small circuit that detects change on this control line must be included in the S-FPGA de ign. We u e 147 y tern gates for this circuit. Using a econd line, called the 'resume' line, normal execution can be restored until the next run-time condition.

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Figure 2. Single tep cherne

After each rising edge of the 'debug clock' line the flipflop 'clock enable' input is asserted during a single clock cycle, and a 'capture' is launched. After this, the software uploads the information to be represented in the Gill. UNSHADES can lunch a equence of a configurable number of tep and' record the information for being displayed into a waveform viewer.

In order to accelerate the recording proce partial acc~ technique are employed. The bit allocation file provide enough information to allow accessing the minimum information unit provided by the Virtex S-FPGA called a frame. A ingle frame contains the information of a column of configurable logic units. The UNSHADES software exploits this property to acce the minimum quantity frames needed to view the elected ignal set. These accesses to the S-FPGA are the bottleneck of the system and limit the effective clock peed when single stepping. In order to improve these tasks the link between the PC and the C-FPGA should be accelerated. The current version achieve 2MB/ u ing the parallel port in it EPP 1.9 mode. C. Flip-flop contents modification

One of the mo t interesting task of the UNSHADES oftware is to change the content of the S-FPGA register during run-time. This task has never been reported before in the literature for the Virtex technologies. Previou work and vendor information affirm that change cannot be performed on elected bit. To make the change correctly the proce can only be performed when the y tern i in a frozen state, this is because a equence of teps is required and no single access is sufficient.

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Figure 4 shows the current form of the UNSHADES GUT. The registers can be added or deleted when desired because the information is extracted from the FPGA when required. In order to minimize the number of bytes requested to the FPGA only the frames that contain useful information are read. Complete access to every register and the debugging tools is possible. The user can display the registers and put them into the drawing area producing an RTL schematic of the design associated to its behavior.

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V. FAULT TESTING. YET ANOTHER TOOL.

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Figure 3. Resources involved in the modification process

From the GUT we can select the candidate'registers to be changed. Then in a dialog window write the new value. When the new value is introduced, then only those bits that differ form the previous information are modified. A sequence of configuration frames is up and downloaded form the S-FPGA. The main difficulties for inducing a new value in a flipflop is determined by the Configurable Logic Block architecture. Basically the idea to force a particular value in a Flip-flop consists in changing the settings of the flipflop for a reset. Figure 3 shows the main hardware involved in the changing process, the other inputs aren't useful for the purpose. In our modification scheme we read the information check the value and read the reset and initial valu~ configuration bits, performing the adequate manipulations. After it, the modified configurations are downloaded and the desired values stored. Finally the original configuration settings are reloaded, in order to leave the system ready for being restored.

New paradigms are open when freeze design and bit change is introduced. Another tools can be developed using this technique in the field of fault tolerant testing, with the advantage of hardware acceleration, that would overcome the main difficulties from the current software testing tools in huge circuits. Single bit events can be emulated by means of register modifications and system can be resumed to check the effects of the fault insertion. Every attempt is run at hardware speed.

VI. CONCLUSIONS. A new technique for hardware debugging has been presented exploiting features of a commercial field programmable FPGA. These device can host a digital design and provide observability, controllability and insertion of desired states into internal registers. UNSHADES tools has been presented as a set of software tools in spite of there's a hardware version designed to match with the software.' Software has been hardware independent and can be adapted to other commercial platforms with few requirements.

In order to minimize the number of transactions between .

the PC and the S-FPGA a special order in the bit list has to be produced.

IV. UNSHADES-l GRAPIDCUSERINTERFACE. A good interface human machine is necessary for a comprehensive interaction between the emulation hardware and the information displayed. During synthesis stage al combinational parts are collapsed into look-up tables and cannot be rebuilt into he original schematics. Only registers can display their information.

REFERENCES [1] Hutchings B., Nelson B. and Wirthlin M.J .. "Designing and Debugging Custom Computing Applications". IEEE Design & Test of Computers. JanMarch 2000. pp 20-28. [2] M.A. Aguirre, J. Tombs, A. Torralba and L.G. Franquelo. "Improving the Design Process of VLSI Circuits by Means of a Hardware Debugging System: UNSHADES-l Framework". To be 'published in

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Proceedings of the 28 th IEEE Industrial Electronics Conference. IECON'02. Sevilla November [3] Xilinx Data book. 2002. [4] Xilinx XC6200 series datasheet. [5] J. Faura, C. Horton, Bernd Krah, J. Cabestany, M.A. Aguirre and J.M. Insenser. "A New Field Programmable System On-a-Chip for Mixed Signal Integration" · European Design & Test Conference 1997. [6] Xilinx application notes number xapp138 and xapp15 1.

Figure 4. UNSHADES-J Graphic User Interface

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