IMTC 2005 – Instrumentation and Measurement Technology Conference Ottawa, Canada, 17-19 May 2005
Affordable Multi-Coding Parallel Error Rate Measurement System Bernard Bordonado1, Alejandro Sanchez2
1
Freescale Semiconductor, BP 72329, 31023 Toulouse cedex 1, France,
[email protected] 2 Universidad Pública de Navarra, Pamplona, Spain,
[email protected]
The previously mentioned coding schemes are not supported by parallel bit error rate (BER) analyzers available on the market. Most analyzers cover specific communication standards but are not generic enough to fit these specific needs without addition of embedded or post processing software. An innovative measurement tool has then been designed to cover these needs with appropriate performances at an affordable cost (see figure 1 below for the architecture of the tool).
Abstract - In this paper we propose a solution for an affordable parallel error rate measurement system based on simple digital hardware interface, and software bringing competitive advantages towards traditional instruments solutions in terms of robustness to both glitch and duty cycle variations. Another advantage of the architecture is the flexibility to measure independent channels communicating at different data rates. Measurement speed optimization is also explained. Keywords - Measurement system, parallel bit error rate, RF receiver.
I. INTRODUCTION BER/PER Software
Radio Frequency (RF) integrated receiver circuits are now extremely common in a wide range of applications where wireless data transmission occurs within short distances (less than 100m) using low data rates (in the range of some kbits/s): - Automotive: remote keyless entry, passive entry, tire pressure and temperature monitoring. - Home automation: remote metering, remote control of alarms and small appliances. - Computing: mouse, keyboard. - Medical monitoring: insulin pumps.
Message generation (1-7 channels)
Most of these applications are using miniature cost effective RF modules based on integrated circuit (IC) technology and target a long battery lifetime (6 months to 6 years depending on the application) difficult to reach when complex integrated circuits based on communication standards are used. For example Bluetooth is oversized in terms of speed and system features (such as channeling, modulation scheme or embedded protocol) for the targeted performances, and demonstrates too high of a current consumption. Simple proprietary communication links are used instead, with elementary OOK (On Off Keying) or FSK (Frequency Shift Keying) modulation schemes, coding formats such as Manchester or Miller and packet profiles including delimiters, checksum and/or redundancy. Performances of these proprietary links can be measured using the device packet format but a faster measurement of error rate is possible if the capability to receive a continuous stream of data is added as test functionality to the RF IC design.
Modulated RF generators or transmitters (1-7)
Combined RF channels Digital I/O board Device Under Test (DUT)
Acquisition of received data after demodulation and eventually decoding (1-7 channels) Figure 1: High level schematic of the BER measurement system
This tool is built around a commercial digital I/O (DIO) board and proprietary application software developed using LabVIEW™ allowing simultaneous BER measurements over up to 7 reception channels. The performances, targeted to cover the characterization of the applications listed, are in the range of BER = 10-5.
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Thanks to its flexible software architecture, this measurement tool can also measure packet error rate (PER) and accept non continuous streams, which is extremely useful to characterize time sliced communication links, common in handheld and mobile applications.
Software control is then available to accept variable device under test (DUT) analog and RF delay. This delay has no maximum value, and it can be set with a resolution lower than one tenth of a bit (see section 2 for explanation of this value). This is usually more than enough for multi channel receiver devices requiring preambles longer than several bits.
The measurement system functions needed to deliver error rate figures are: - Generation of messages organized as packets, each channel being freely configured to run at a different data rate according to user specified parameters: - packet size (memory limited only) - coding type (Manchester and Miller are today supported by the software, and others could be implemented) - random or fixed data or user specified patterns allowing error insertion - RF signal duty cycle bias and random jitter superimposition, simulated by oversampling - Acquisition of the received data, each channel being oversampled to allow further post processing. - Comparison of the sent and received messages using time and content synchronization recovery methods, to allow the pattern recognition to be glitch and jitter / duty cycle tolerant, without need of a device generated synchronous clock. Robustness of the comparison is ensured by a voting algorithm.
STEP 2 Trigger Acquisition
STEP 1 Auto Trigger Generation DIO board Port 1 (Output)
DIO board Port 0 (Output)
Hardware control DUT programming
Pattern Generation
STEP 3 Pattern Acquisition DIO board Port 2 (Input)
DUT(s) 1-7 Channels
This tool used interactively is ideal for IC lab evaluation, application performances tuning and IC rejects analysis. If embedded in a fully automated measurement sequencer, it can also address performances characterization over an exhaustive set of application conditions.
Pattern for channel 1 RF generator channel 1
Pattern for channel 7
II. PROPOSED APPROACH
RF generator channel 7
Figure 2a: Generation and acquisition sequence
Technical contribution is significant along three aspects: - Tolerance of synchronization method to any device internal delay between RF and digital signal. - Use of oversampling to allow measurements on parallel channels running at different data rates. - Compact size of the BER measurement system allowing its integration into a more complex bench.
Pulse to trigger generation (Port 1) Software initialization
Time
1
A. Synchronization
2
The tool development has required an optimized use of digital resources (clocks, memory, and digital lines) of the DIO board to allow oversampling, operation at different data rates on each channel, clock recovery and proper control of generated duty cycle and jitter variations to simulate a non perfect transmitter. To guarantee the capability to resynchronize the packets sent and acquired, and to count errors properly, the DIO board is used to self trigger its acquisition sequence (see figures 2a and 2b below).
Non critical delay Fixed by software, can be adapted to different DUTs
3
Time
Pulse to trigger acquisition (Port 0/2)
Figure 2b: Generation and acquisition sequence steps
Another critical choice has been made for the acquisition method between “edge detection” and clock based “sampling”.
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Using edge detection is interesting in terms of reduced software complexity but needs additional hardware resources such as a timer board to allow timestamping and therefore more accurate control of the duty cycle and jitter. This extra cost has been avoided using a custom method based on oversampling and software synchronization techniques. The drawback of this method for high data rate devices is the significant size of data arrays to manipulate in the computer memory, but data array size is acceptable for the targeted low data rate devices (below 100kbits/s). As timestamping is not available, duty cycle variation and jitter superimposition is still made possible through direct manipulation of the data arrays before digital generation. Oversampling (detailed below) allows one to select discrete values for duty cycle offset or to superimpose random variations of the duty cycle over time, i.e. jitter.
From the DUT point of view, the system is real time as it is able to generate and send a message at the data rate speed, but the analysis is not real time as the algorithm is based on post processing of the sampled arrays. Figure 3 below shows the full sequence of measurement in terms of data conversion, generation and acquisition. More details on the BER analysis are provided in the next section. The triggering of the generation and acquisition has been described in the figure 2b, but the system also must decide when to stop acquiring samples. This is done by counting samples until reaching a limit, built from the length of the data generated, increased by an estimated value of the internal delay of the DUT and some tolerance margin for safety. Thanks to the embedded protocol (see item 3 on figure 3), there is no problem accepting some dummy samples at the end of the acquisition. B. Oversampling
Direct manipulation of the generated arrays has also the advantage of allowing the system to guarantee the noncoherence of all channels streams. This is important as receiver devices in the true field application are not receiving coherent signals.
NRZ random data
Data Generation
The measurement software algorithm has been written to allow synchronization and error detection on parallel independent channels. This has been made possible by setting the DIO board master clock frequency to the least common multiple of device desired data rates (for example 2400bps, 6000bps, 9600bps) multiplied by a number equal to or greater than 10.
Encoded data
Start
Packet 1
Encoded data
Packet 2
Stop
Data embedded into a packet Protocol using NRZ Start/Stop tags
Create message in computer memory by concatenation of N packets
Packet N
Send Message
Send Message
Send messages to DUT at desired data rate (one message per RF input level) Time
DUT delay
Acquire Message
BER Analysis
Decimation of oversampled data (voting algorithm)
Acquire Message
BER Analysis
Time
Synchronization (protocol patterns) Comparison
Figure 3: Measurement sequence on one channel
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Measurement
Array index
In the end, to generate (items 1 to 4 on figure 3), send to DUT (item 5 on figure 3), oversample and properly acquire patterns (items 6 and 7 on figure 3) for a device working in the range of 10kbps, the DIO board master clock must run at over 200kHz. The acquisition sampling speed is constant so due to the different IC data rates possible, the oversampling ratio can be different on each channel. This is not a problem for the system capability as will be presented in the results section. To compare sent and received packets, the software is operating in two steps. The raw acquired samples are “decimated” (see figure 3 item 7) according to the oversampling ratio (for example 10) and a 0/1 decision is made through a majority vote. Positions of any possible glitches are voluntarily ignored to be at the same time jitter and glitch tolerant. Data is then available to be compared with the sent pattern, but the synchronization is not guaranteed as the delay in the DUT is unknown. To avoid impacting the measurements with decoding uncertainties, the system is comparing sent and received messages at encoded level.
position in the stream of the found “start pattern” and the values of the parameters (average packet size) the packet id can be found. To work correctly, the device delay has to be under a packet size. It still allows the system to measure long internal delay devices, as the packet size is not limited and can be freely increased. The function includes a moving average tracking algorithm of the packet size to avoid synchronization loss (see figure 5 below). The found packets are classified by their positions in the stream, decoded and compared with the corresponding position of sent packets. Bit Error Counter = 0 Packet Error Counter=0
Search for “START” pattern in one block of one packet size + tolerance
Found ?
Yes
No Jump to next block
To achieve synchronization, the recovery routine must meet a certain number of requirements: - It must be able to analyze a stream of data which is organized in packets, then distinguish in the bit streams those packets and identify them by “packet id” in order to compare the proper packets in sent and received streams. - It must manage packets of variable size. The system is intended to deal with coding schemes in which the stop patterns are not fixed and with devices whose internal delay might change the packet size. - Due to variable internal delay of the receiver IC, the position of the beginning of the captured stream will be variable.
+1 Packet in Bit Error Counter +1 in Packet Error Counter
Search for “STOP” pattern around expected packet size + tolerance
No
Found ? Yes
The start pattern or start tag constitutes the reference for recovery. Synchronization is therefore obtained by a sequential search of predetermined start and stop tags embedded in the generated patterns. The delay inside the DUT has to be smaller than the size of one packet, but this is usually easy to achieve at these data rates with a minimum packet size of 10 bits. Also the errors occurring in start pattern result in loss of an entire packet. The recovery routine will go on looking for the reference tag continuously. When the tag or start pattern is located, then the next one is searched for at a distance defined by the packets size, the “stop pattern” average size and a margin including the size variation of stop pattern and data (see figure 4). When a packet is found by this method, its position in the stream is calculated: the acquired or received stream has more or less the same length of the sent one. Knowing the
Compute packet number based on position in acquired data Yes
No
Bit error(s) ?
Compare found packet with same packet generated data
Figure 4: Synchronization and error analysis code flow chart
The best compromise between measurement speed and software (mostly memory) overhead is then found by selecting the oversampling ratio to be one order of magnitude higher than the highest data rate intended to be measured. This rule ensures an acceptable tolerance to glitch during voting phase (see figure 3 item 7) and a minimum resolution of 10% on the duty cycle.
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Generated message Preamble
Preamble
1
2
1
3
2
4
3
.................
4
The capability of the measurement system has been verified in loopback mode first, then using multiple single channel DUT receivers as reference, correlating results with a commercial communication analyzer. The system has then been used for the characterization of a dual channel receiver and results correlated with a proprietary application code running on a dedicated microcontroller.
N
.................
N
Acquired message DUT delay < one packet
Synchonization window size is equal to packet size plus a user selected tolerance
Another important aspect of the measurement system performance is the impact of software post processing in terms of speed. Using a standard lab computer (PC Pentium III, 1GHz, 256Mo of RAM, Windows 2000, LabVIEW 7, PCI-6533 DIO board), the overhead is below 50% of the messages real length. This is acceptable for BER=10-5 targets.
Figure 5: Sliding synchronization window
C. Integration of BER measurement system with other functions The presented solution is conservatively using DIO board resources (see figure 2a) allowing integration in a more complex automated measurement system as remaining digital lines can be used to control DUT through SPI, I2C or any proprietary interface. This compact solution helps to simplify the measurement hardware and software. Another advantage of the architecture is that it’s easy to resize based on the hardware available and the number of DUT channels. As an example, a system with four RF generators can measure in parallel four single channel devices, two dual channel devices or one quadruple channel device. All channels can be measured at any data rate in the range defined by the main sampling clock. III.
A measurement system analysis (see reference 3 for method) based on 200 measurement cycles for one sample (20000 bits per point) and the same measurement over a batch of 80 samples has given a %R&R (repeatability and reproducibility) for bit error rate below 10%, which is an acceptable value for most of the usual applications of such a tool. The figure 7 below shows the typical results of measurements in the following configuration: 2 channels, 2000 packets of 50 bits Miller encoded 8 bits for start/stop protocol, data randomly generated at 6000bps.
RESULTS
The main criterion for measurement system validation is high resistance against jitter and glitch. This resistance is mostly defined by the rate of oversampling and the voting algorithm programmed majority. Some values are summarized in the figure 6 below, using Miller coding: Sampling frequency (Hz) 192000 192000 192000
Duration Data Duration of Miller Samples Duty cycle rate of one bit period Samples per Miller resolution (bps) (µs) (µs) per bit period per bit 2400 417 208 80 40 2.5% 6000 167 83 32 16 6.3% 9600 104 52 20 10 10.0%
Figure 6: Summary of system capability in terms of duty cycle
From this table, we can see that in the worst case at the highest data rate: - During data generation, the system can simulate jitter variations with a resolution of +/-10%. - During data acquisition, the most tolerant vote is 6 over 10 majority, which means each bit will be correctly recognized even with a 40% duty cycle/jitter peak variation.
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Figure 7: Software graphical interface showing typical BER/PER measurement
CONCLUSION The bit/packet error rate measurement architecture presented here is affordable, robust against glitch and jitter, flexible in terms of characterization of multi channel devices using independent channel data rates. It also allows complete automation of measurements. Potential next developments are the addition of coding schemes other than Manchester and Miller and overhead reduction. APPENDIX The system described in this article has been validated and used as reference measurement tool for the characterization of two different receiver integrated circuits already used as production devices. Correlation between the results obtained from that tool and application level software were excellent. REFERENCES [1]
[2]
[3]
Bordonado, Bernard, “LabVIEW and RF measurements automation for automotive ASIC”, FuturVIEW 2003 Conference, ENSMA Poitiers, France Berber, S.M, “An automated method for BER characteristics measurement”, Instrumentation and Measurement, IEEE Transactions on , Volume: 53 , Issue: 2 , April 2004 AIAG Measurement System Analysis Manual, 3rd Edition, March 2002
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