and Automated Clock Gating. Nainesh Agarwal and Nikitas Dimopoulos. Dept. of Elec. and Comp. Engineering. University of Victoria. Victoria, BC, Canada.
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Algorithmic Level Hardware Design using CoDeL and Automated Clock Gating Nainesh Agarwal and Nikitas Dimopoulos Dept. of Elec. and Comp. Engineering University of Victoria Victoria, BC, Canada {nagarwal,nikitas}@ece.uvic.ca
TABLE I ESTIMATED VS . MEASURED USING
Analysis Filter Bank Module
S YNOPSYS Start
Module Analysis Synthesis DWT
Estimated (%) 20 20 13
Ready
Measured using Synopsys Statistical (%) Simulation (%) 17 80 17 80 18 60
Start Ready
fStart fReady StartPt
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Step
Step
iStart iReady
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M (Rows) N (Cols) Size (M*N)
I. A BSTRACT
Register File
P OWER SAVINGS :
StartPt Forward/Inverse
For rapidly prototyping hardware architectures, we have developed a system level design language, called CoDeL (Controller Description Language) [1]–[4]. CoDeL targets the specification and design at the behavioral level. Details of the platform and the language syntax can be found in [1], [2]. We have now developed extensions to the CoDeL compiler which implement clock gating to dramatically lower dynamic power dissipation in CMOS VLSI circuits. This mechanism disables the clock to the registers during periods when we are ensured that the registers are inactive. To estimate these power savings from automated clock gating, we have developed an analysis framework, which allows quick and accurate power savings estimation based on the description at the behavioral level. This estimation framework is built into the CoDeL compiler and the estimates are output upon compilation of an design. To evaluate CoDeL’s power efficient compilation we use an implementation of a 5/3 Discrete Wavelet Transform using the lifting technique. A detailed description can be found in [4]. We have implemented the forward and inverse DWT using three separate modules (see figure 1): the 5/3 analysis filter bank module, the 5/3 synthesis filter bank module, and the DWT module. All the modules are implemented using CoDeL. For synthesis we have used Synopsys tools with the TSMC 0.18-micron CMOS technology. Table I shows a comparison of the power savings that are predicted by the estimation framework and what we obtain from power analysis using Synopsys. The power results from Synopsys come from two methods. One uses statistical switching activity for the various elements of the circuit, while the other uses switching activity annotated through simulation. The statistical power analysis provides a better comparison for our estimation framework, since they are both based on a static
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DWT Module
Synthesis Filter Bank Module
Fig. 1.
DWT System Architecture
analysis of the system. The simulation based power analysis, however, is a more accurate estimate of the expected power savings in the final design. We find that the power savings estimated using the analysis framework compares quite well to the power savings using statistical power analysis. From the simulation based power analysis, we find that in the final design we can expect as much as 80% power savings by using the clock-gated design. The results show that the extension to CoDeL, which implements clock gating, is an effective tool for lowering dynamic power consumption, while still permitting hardware design and specification at the algorithmic level. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. R EFERENCES [1] R. Sivakumar, V. Dimakopoulos, and N. Dimopoulos, “CoDeL: A rapid prototyping environment for the specification and automatic synthesis of controllers for multiprocessor interconnection networks,” in Proc. SAMOS III, July 2003, pp. 58–63. [2] N. Agarwal and N. Dimopoulos, “Using CoDeL to rapidly prototype network processsor extensions,” in Lecture Notes in Computer Science, vol. 3133. Springer-Verlag GmbH, Nov 2004, pp. 333–342. [3] ——, “Rapidly prototyping DSP extensions using CoDeL: the DWT using lifting,” in CCECE 2005, May 2005. [4] ——, “Power-efficient rapid system prototyping using CoDeL: The 2D DWT using lifting,” in Proc. IEEE PacRim 2005, Aug 2005.
