An Efficient CMOS Rectifier with Low-Voltage Operation ... - IEEE Xplore

An Efficient CMOS Rectifier with Low-Voltage Operation for RFID Tags Pouya Kamalinejad, Shahriar Mirabbasi and Victor C.M. Leung University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, BC, Canada, V6T 1Z4 [email protected], [email protected], [email protected] Abstract—A high-efficiency CMOS rectifier for radiofrequency identification (RFID) applications is presented. Using an on-chip generated clock signal, a new switching scheme is proposed to enhance the power efficiency of the conventional 4 transistor (4T)-cell rectifier. By switching the gate of chargetransfer transistors to the intermediate nodes of preceding and succeeding stages, low on-resistance and small leakage current are obtained simultaneously. To further improve the low-voltage operation capability, an external gate-boosting technique is also applied to the proposed design which enables an efficient operation for input voltage levels well below the nominal standard threshold voltage of MOS transistors. The two proposed rectifier architectures are designed and laid out in a standard 0.13𝜇m CMOS technology. For a 950 MHz RF input and 10 kΩ output load, post-layout simulation results confirm a power conversion efficiency (PCE) of 74% at −10 dBm and 57%at −26 dBm for switched 4T-cell and gate-boosted switched 4T-cell, respectively. While the PCE of the proposed switched 4T-cell rectifier compares favorably with that of the state-of-the-art rectifier designs, the gate-boosted version achieves a relatively high PCE while operating with a very low input power.

I. I NTRODUCTION Radio-frequency identification (RFID) technology has been gaining extensive attention in the past few years. RFIDs are now the predominant choice in numerous industrial applications such as automated data management, object identification, contact-less smart cards, medical implants and many more [1], [2]. From the power supply perspective, RFID tags are categorized into three major classes of active, semi-passive, and passive tags. Active tags rely on an on-board battery as their main energy source for autonomous operation. Semipassive tags are also dependant on a battery for the start-up, however, the required energy for communication is provided by the reader. In contrast, passive tags extract the entire required energy from the radio-frequency (RF) signal transmitted by the reader which in turn alleviates the need for an on-board power supply. This autonomous capability of passive tags allows for a lower production cost and a longer, maintenancefree lifetime. However, since the radiated RF energy received by the tag decreases rapidly as a function of distance from the reader, the absence of sufficient energy puts stringent demands on the power supply generating circuit when it comes to semipassive and more severely, passive tag applications. Therefore, This research is funded in part by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the Institute for Computing, Information and Cognitive Systems (ICICS) at UBC. CAD support and access to technology is facilitated by CMC Microsystems. c 2011 IEEE 978-1-4577-1221-0/11/$26.00 ⃝

to guarantee the desired communication range, an efficient RFto-DC converter (also called rectifier) is necessary to provide a stable power supply with the required voltage level [2]. The performance of a rectifier is evaluated in terms of power conversion efficiency (PCE) as: PCE =

Pout Pin

(1)

where Pout is the output DC power of the rectifier and Pin is the received RF input power. This performance metric plays a critical role in the operation of the entire RFID tag as suggested by Friis transmission equation (in the presence of impedance matching): )2 ( 𝜆 (2) Ptag = EIRPreader ⋅ Gtag ⋅ PCErectifier ⋅ 4𝜋𝑑 where Ptag is the practicable operating power of an RFID tag, EIRPreader is the effective isotropic radiated power of the reader, Gtag is the tag antenna gain, PCErectifier is the power conversion efficiency as shown in Eq.1, 𝜆 is the wavelength of the transmitted RF signal, and 𝑑 is the distance between the tag and the reader [3]. In North America, the maximum transmitted power, EIRPreader is set to 4 W by the electronic product code (EPC) protocol. Gtag is a function of antenna area and Ptag is dependent on the required sensitivity of the receiver and the tag’s application. Thus, a viable and promising option to increase the communication range 𝑑, is by manipulating PCErectifier . In a typical RF-to-DC rectifier, PCE is mainly degraded as a result of two mechanisms: forward voltage drop in chargetransfer switches (related to the on-resistance of the switches), and their leakage current. Note that parasitics also contribute to efficiency degradation, but they have a second-order effect. In conventional Dickson rectifiers, Schottky diodes were considered as an attractive candidate to perform the chargetransfer task due to their low forward voltage drop and fast switching speed [4]. However, Schottky diodes are not properly modeled in all CMOS technologies which restricts their usefulness in low-cost applications where high integration levels are desired. Therefore, recently most researchers have been working towards finding solutions to the aforementioned problems (forward voltage drop and leakage current) in CMOS technology. [5-10] provide comprehensive analysis and design strategies to enhance the performance of Dickson-based UHF CMOS rectifiers.

(a)

(b)

Fig. 1. Conventional rectifier architectures. Conventional CMOS rectifier (a), Self-Vth -cancellation CMOS rectifier (b).

However, Dickson-based rectifiers are generally incapable of providing high PCE due to their inefficient architecture (especially, when Schottky diodes are not available), thus recently most of investigations have been focused on a more effective architecture, the so-called differential drive or 4Tcell rectifiers [11]. 4T-cell rectifier has a cross-coupled bridge configuration and simultaneously provides a low on-resistance and small leakage current. [12] uses low-Vth transistors in a 4T-cell architecture and achieves a power efficiency of 23.5% (for the complete power extraction system consisting of antenna, impedance matching network and rectifier) at 950 MHz RF input frequency for a load current of 4𝜇A. [3] presents a 4T-cell rectifier for which 66% of PCE is achieved for 953 MHz input frequency at −12 dBm RF input power and 10 kΩ output load. In [13], a self-biasing scheme is applied to the differential rectifier to dynamically bias the gate of transistors (by means of an auxiliary driver stage) in such a way that maximum power efficiency is achieved at a given input power. The proposed technique in [13] achieves a PCE of 60% for 0.36V input voltage amplitude. This paper proposes a switching scheme for the 4T-cell architecture. At each stage, by timely connecting the gate of NMOS and PMOS switches to intermediate voltages in the succeeding and preceding stages, the on-resistance and reverse leakage current of transistors are improved simultaneously as compared to the conventional 4T-cell rectifiers. To further enhance the PCE for small input power and voltage levels, a gate-boosting technique is added to the switched rectifier which allows for a high PCE at input voltages well below the standard threshold voltage of MOS transistors. The proposed architectures are designed and implemented in a standard 0.13𝜇m CMOS technology and their performance are verified by post-layout simulations. The rest of the paper is organized as follows: Section II provides a brief overview of conventional 4T-cell rectifier and then presents the proposed switching scheme. Section III describes the proposed gate-boosting technique applied to switched 4T-cell rectifier while Section IV provides the post layout simulation results and Section V concludes the paper. II. R ECTIFIER A RCHITECTURE WITH THE P ROPOSED S WITCHING S CHEME Fig.1(a) shows a conventional CMOS rectifier for which the turn-on voltage of the transistors is roughly equal to their threshold voltage and thus fails to provide a reasonable PCE for small input voltages. In Fig.1(b), a static gatebiasing scheme is applied to the CMOS rectifier of Fig.1(a)

Fig. 2.

Differential CMOS rectifier architecture.

by connecting the gate terminals of n-MOS and p-MOS transistors to the output and input of the corresponding stage, respectively [9]. This scheme is called ”static biasing” as the gate terminals of transistors at each stage are always boosted by a voltage which is independent of the input RF voltage. The shortcoming of this scheme manifests itself when the threshold voltage of transistors is not negligible as compared to the voltage levels in the circuit which consequently results in a high on-resistance and significant leakage currents, and thus, a dramatic reduction in PCE. To overcome this drawback, [11] proposes a differential architecture to dynamically bias the gate of transistors by a differential-mode signal. As shown in Fig. 2, differential-mode RF inputs are applied to the rectifier through the coupling capacitors CC . For the intervals where VRF- is negative and accordingly VY is below VCM level, MP1 transfers charge from input VRF+ to CS and MN1 is off. At the same time, VX is larger than VCM and thus MN2 transfers charge from DC OUTn-1 to CC- while MP2 is off. MN1 -MP1 and MN2 -MP2 exchange their tasks in the subsequent interval when VRF+ is negative. Note that at each branch, when one transistor is conducting, the other is off, therefore, a simultaneous reduction in the turn-on voltage and leakage current is achieved which in turn leads to a high PCE for small input powers. [3] uses the same architecture to achieve a PCE of 66% at −12 dBm RF input. However, it should be noted that the input RF power is not necessarily a good metric to evaluate the performance of a rectifier unless it is accompanied with the information about the input voltage level. The peak voltage available at the input, under perfect power matching condition, is given by [11]: √ PAV 1 (3) VINp ≈ RANT 𝜔𝐶 where PAV is the available power at the antenna terminals, RANT is the antenna equivalent resistance, 𝜔 is the resonance frequency of the antenna impedance and C is the chip equivalent input capacitance. To enhance the input voltage seen by the chip, 𝑅ANT has to be minimized, however, the minimum antenna impedance is dictated by geometrical constraints and maximum efficiency. Thus, as suggested by Eq.3, small input RF powers lead to small input voltage levels at the input of

Fig. 3.

Switched Differential CMOS rectifier.

the rectifier. For small input voltages (Vin < Vth ) the differential architecture fails to build up a large enough VCM which therefore compromises the advantage of differential-drive technique. To address this problem, we propose a switching scheme as shown in Fig. 3. To further enhance the gate drive voltage, each stage (excluding the first and the last stage) exploits the intermediate voltages (VXi − VYi ) already generated in the preceding and succeeding stages instead of it’s own intermediate voltages. Therefore, when VRF+ is positive, CLK1 connects the gate terminals of MP1 and MN1 (VGn+ ) to the preceding stage intermediate voltage VYn-1 (instead of VYn ). Consequently, MP1 , which is supposed to conduct, experiences a larger source-gate drive voltage and MN1 , which is supposed to be off, is driven by a larger reversed bias voltage across its gatesource terminals. In the next cycle, when VRF+ is negative, CLK connects VGn+ to VYn+1 , therefore, reinforcing MP1 to be off and MN1 to conduct. The same scenario happens for MN2 and MP2 in every other cycle. Thus, assuming equal voltage increment for all stages, i.e., if VX,Yi ’s are equally separated, the proposed scheme provides a gate-drive voltage enhancement as large as ΔV = V(X,Y)i − V(X,Y)i-1 . In the proposed scheme, the first stage uses its own intermediate voltages (VX1 and VY1 ) for VXn-1 and VYn-1 as there is no preceding stage available. Similarly, as there is no succeeding stage after the last stage, the last stage uses its own intermediate voltages (VXk and VYk ) for VXn+1 and VYn+1 (k is the number of stages). To improve the performance of the proposed switching scheme, it is essential to adjust CLK1 and CLK2 for each stage, such that to maximize the amount of charge that is transferred in the forward direction while minimizing the reverse leakage current. For this purpose, as shown in Fig.4, CLK1 turns on while VXN > DC-outn (shaded area). Note that in this architecture, the most leakage for MP1 occurs when DC-out > VXn and VGS-MP1 is still negative, i.e., at the beginning of [t2 , t3 ] interval. Thus, CLK1 turns off at t2 to avoid the leakage current. Although this timing scheme provides sufficient forward charge transfer and reduces the reverse leakage, it is not an optimum choice. Simulation results

Fig. 4.

Switched Differential CMOS rectifier timing diagram.

Fig. 5.

Clock generation circuit.

show that reverse leakage current is very sensitive to voltage levels and it starts to flow prior to t2 where VXN > DC-outn . For clock generation from the sinusoidal (intermediate) voltages in each stage, a simple regenerative amplifier is used as shown in Fig. 5. VXn (sinusoidal input) and DC outn (DC output of the corresponding stage to adjust the trigger point of the clock) are applied to the input terminals of the amplifier and CLK1 -CLK1 are obtained at the output of the two inverter buffers. Note that the timing precision requirements of the generated clock signals are not stringent and the simple amplifier shown can perform the task of clock generation with a reasonable power consumption. CLK2 -CLK2 are generated in the same manner with another similar amplifier. In the simulated circuit with 950 MHz input, the generated clock edges are not aligned with the crossing point of the inputs due to the delay of the amplifier and inverter buffers, i.e., t1 and t2 will be slightly shifted to the right in Fig.5. However, the system is tolerant to this delay and has a feedback-based selfcorrection property: the delay in t1 and t2 , (see Fig. 5) results in a reduction in DC outn , which consequently increases the duty cycle of the clock and thus DC outn will increase, and therefore the adverse effect of the delay is partially compensated. For the amplifiers used for clock generation, VDD and Vb can be obtained from a pre-charged battery in semi-passive or active RFID tags or from an auxiliary conventional 4T-cell rectifier in passive RFID tags. The auxiliary rectifier can then be switched off when the output of the main rectifier reaches the desired value after which the main rectifier can continue its operation in a self-sufficient manner.

Fig. 6.

Gate-boosted CMOS Differential rectifier. Fig. 8.

Fig. 7.

Gate-boosted CMOS Differential rectifier timing diagram.

III. P ROPOSED G ATE -B OOSTED R ECTIFIER A RCHITECTURES To further improve the low-voltage capability of the proposed switched rectifier circuit, a gate-boosting technique is applied to the switched rectifier as shown in Fig. 6. A floating voltage source is attached between the output of switches and the gate terminals of the transistors such that when CLK1 is high (time interval [t1 , t2 ]), −Vboost is added to VYn-1 , and therefore, MP1 source-gate drive voltage and MN1 reverse bias are increased by ∣𝑉boost ∣. In the next cycle when CLK1 is low, (time interval [t2 , t′1 ]), the floating voltage source swaps the direction of its terminals. Therefore, +𝑉boost is added to VYn+1 and thus it enhances MN1 gate-source drive voltage (and MP1 reverse bias voltage) by the same amount, ∣𝑉boost ∣. Consequently, as shown in Fig.7 by applying the gate-boosting technique to the differential rectifier scheme presented in Section II, the gate voltage of transistors are boosted by as much as ΔV + Vboost where ΔV = V(X-Y)i − V(X-Y)i-1 . To implement the floating voltage source capable of swapping its terminals in appropriate time cycles, the switchedcapacitor architecture of Fig.8 is proposed. After a few clock periods when the switched-capacitor circuit reaches its steadystate, Cboost is charged to Vboost and acts as a floating voltage source. When CLK1 is high, Cboost provides −Vboost between nodes X and Y through MF1-2 . In the next clock cycle, where CLK1 goes low, MF1-2 turn off and Cboost is reversely placed providing +Vboost between nodes X and Y through MR1-2 . In semi-passive or active tags, Vboost can be supplied from

Floating voltage source implementation.

a pre-charged battery. In passive tags, Vboost can be chosen from the output of one of the intermediate stages that has a reasonable output value. This is because a too small voltage (with respect to the voltage being generated at each stage) does not allow for taking full advantage of benefits of the gainboosting technique and a too high voltage leads to a relatively long transition time at the edge of the clock which results in increased leakage current. The power consumption of the voltage booster is a function of the frequency of operation, the leakage current of the two capacitors (Crefresh , Cboost ) and the driver transistors, and consequently is on the order of few hundred nano-watts. Note that although the proposed voltage booster is very low power, its loading effect on the intermediate node to which it is connected has to be taken into account in passive tag applications. To drive M1 -M4 to recharge Cboost , a low-frequency clock is more attractive as it leads to smaller power consumption, however, if a low-frequency clock signal does not exist on the chip, pregenerated CLK1 can be employed in order to minimize circuit complexity and layout area. The block diagram of the proposed gate-boosted scheme is shown in Fig. 9 for a K-stage rectifier. Note that Fig. 9 can also represent the switched differential rectifier (Section II), if Vboost generator network is removed. IV. P OST-L AYOUT S IMULATION R ESULTS The proposed switched differential and gate-boosted rectifiers are designed and laid out on a prototype three-stage rectifier in a 0.13 𝜇m CMOS technology. The transistor sizes are designed to optimize the performance and capacitors are implemented with a metal-insulator-metal (MIM) structure. External VDD = 0.6 V, Vb = 0.3 V and Vboost = 0.2 V are applied to the rectifiers. At 950 MHz input frequency, the output voltage versus RF input voltage amplitudes of switched rectifier and gateboosted rectifier for different load resistance values are shown in Fig.10, respectively. As can be seen from Fig.10, gateboosted rectifier provides a lower turn-on voltage with respect to switched rectifier which confirms the low-voltage capability of the proposed design.

(a)

(b) Fig. 11. Rectifier PCE as a function of input power. Switched rectifier (a), Gate-boosted rectifier (b). Fig. 9.

Block diagram of the proposed gate-boosted rectifier.

(a)

(b) Fig. 10. Rectifier output voltage as a function of input voltage. Switched rectifier (a), Gate-boosted rectifier (b).

The six clock generators (two for each stage) dissipate a total power of 7.2 𝜇W and the six Vboost distributers consume 6.5 𝜇W. Considering the clock generators power overhead in switched rectifier and Vboost distribution network as well as the clock generator power consumption for the gateboosted rectifier, the PCE of the two proposed architectures at 950 MHz input frequency for a 10 kΩ load resistance are shown in Fig.11. As can be seen form Fig.11, even

accounting for clock generators and Vboost distributers power overhead, the obtained PCE curves show an improvement over the conventional differential rectifiers both in terms of power efficiency and input RF power level. Note that although the output voltage curves in Fig.10 show a monotonically increasing behavior (over the entire voltage range shown), PCE drops for both designs as shown in Fig.11, when the input power exceeds the maximum efficiency point, which suggests the self-output-power regulation capability of the proposed rectifiers [3]. The self-output-power regulation behavior is desirable for rectifier operation in the sense that in practice, it relaxes the requirements for the regulator block succeeding the rectifier. This characteristic stems from the fact that high input power levels generate large intermediate voltages at each stage, resulting in excessive gate-drive voltages (i.e., overcompensated threshold voltage) that in turn leads to higher leakage current and degrades the power conversion efficiency. As stated in Section II, at a large distance from the reader where the incident RF power to the tag is small, a small input voltage is received at the input of the rectifier which undermines the proper operation of the differential rectifier. Therefore, to secure a long range of operation, a small turn-on voltage is as important as a small power-up threshold. Fig. 12 shows the input voltage range improvement achieved through gate-boosting technique. As can be seen from Fig. 12, the maximum efficiency for the gate-boosted rectifier occurs at 350 mV input amplitude which proves a significant enhancement over the corresponding maximum efficiency input voltage of 800 mV for its switched rectifier counterpart. Moreover, as inferred from Fig.12, the gate-boosted rectifier is capable of providing acceptable PCE for input voltage amplitudes well below the threshold voltage of CMOS transistors in 0.13 𝜇m CMOS, where Vthn ≃ 0.355 V and Vthp ≃ −0.325 V. However, the input voltage range enhancement is achieved at

Fig. 12.

Switched rectifier vs. Gate-boosted rectifier input voltage range.

the cost of more power consumption (consumed by the booster network) and consequently smaller overall PCE. As shown in Fig. 11 and Fig. 12, as compared to switched rectifier, PCE of gate-boosted rectifier starts to drop at a lower value of input power (and input voltage), which is due to the fact that beyond a certain point corresponding to maximum efficiency, extra boosting poses additional leakage currents and leads to the observed PCE degradation. Table I provides a performance summary of the proposed differential-drive rectifiers along with a comparison with recently reported results in the same category of rectifiers. TABLE I P ERFORMANCE S UMMARY AND C OMPARISON OF THE P ROPOSED D IFFERENTIAL -D RIVE R ECTIFIERS WITH CMOS S TATE - OF - THE -A RT R ECTIFIERS

Technology Number of stages Input Frequency Load Resistance Output Voltage Maximum Efficiency

[12]★

[3]★

[13]★★

0.18𝜇m 2

0.18𝜇m N/A

0.13𝜇m 4

950 MHz N/A (2𝜇W) 0.5V @ 0.36V 23% @ −21 dBmc

953 MHz 10 kΩ

950 MHz N/A (4𝜇A) 0.6V @ 0.9V @ -12 dBm 0.36V 66% @ 60% @ −12 dBm 0.36V

This★★ work-1a 0.13𝜇m 3

This★★ work-2b 0.13𝜇m 3

950 MHz 10 kΩ

950 MHz 10 kΩ

1.4V @ 0.8V 74% @ −10 dBm

0.6V @ 0.34V 57% @ −26 dBm

★ Measurement

results. ★★ Post-layout simulation results. rectifier. b Gate-boosted rectifier. c The complete power extraction system. a Switched

V. C ONCLUSION Two prototype three-stage CMOS RF-to-DC converters for UHF RFID tags are designed and laid out in 0.13 𝜇m CMOS. Compared to conventional rectifiers, both structures provide high power conversion efficiency and low voltage operation capability. To enhance the differential rectifier PCE, a new switching scheme is proposed that simultaneously reduces the effective turn-on voltage and leakage current of switch transistors. A simple clock generator is used to provide the appropriate clock signals required for the switching. The proposed scheme is then improved in terms of operation voltage range by applying an external voltage booster. Through the use of a floating voltage source capable of swapping its terminals, the gate of charge transfer switches are dynamically biased to alleviate the drawbacks associated with static biasing

scheme. Note that in start-up phase, both structures rely on a power source for the purpose of clock and Vboost generation which can be supplied through an on-board battery in semipassive tags. In passive RFID application, an auxiliary 4T-cell rectifier has to be incorporated in order to supply the required energy in start-up phase. The auxiliary rectifier can then be switched off when the output of the main rectifier reaches the desired value after which the main rectifier can continue its operation in a self-sufficient manner. The switched rectifier achieves a PCE of 74% at −10 dBm input power (800 mV input amplitude) while the gate-boosted rectifier provides a reasonable PCE of 57% at −25 dBm input power (350 mV input amplitude). The two proposed techniques can be combined to form a rectifier capable of providing high PCE over a wide input power range. R EFERENCES [1] V. Pillai, H. Heinrich, D. Dieska, P. Nikitin, R. Martinez, and K. Rao, “An ultra-low-power long range battery/passive RFID tag for UHF and microwave bands with a current consumption of 700 nA at 1.5V,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 7, pp. 1500 –1512, Jul. 2007. [2] Y. Yao, J. Wu, Y. Shi, and F. Dai, “A fully integrated 900-MHz passive RFID transponder front end with novel zero-threshold RF-DC rectifier,” IEEE Transactions on Industrial Electronics, vol. 56, no. 7, pp. 2317 –2325, Jul. 2009. [3] A. Sasaki, K. Kotani, and T. Ito, “Differential-drive CMOS rectifier for UHF RFIDs with 66% PCE at -12 dBm input,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 105 –108, Nov. 2008. [4] U. Karthaus and M. Fischer, “Fully integrated passive UHF RFID transponder IC with 16.7-𝜇W minimum RF input power,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1602 – 1608, Oct. 2003. [5] J. Yi, W.-H. Ki, and C.-Y. Tsui., “Analysis and design strategy of UHF micro-power CMOS rectifiers for micro-sensor and RFID applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 38, no. 10, pp. 1602 – 1608, Oct. 2003. [6] A. Ashry, K. Sharaf, and M. Ibrahim, “A simple and accurate model for RFID rectifier,” IEEE Systems Journal, vol. 2, no. 4, pp. 520 –524, Dec. 2008. [7] F. Mazzilli, P. Thoppay, N. Johl, and C. Dehollain, “Design methodology and comparison of rectifiers for UHF-band RFIDs,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2010, pp. 505 –508, May 2010. [8] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, T. Suzuki, and S. Otaka, “A 950-MHz rectifier circuit for sensor network tags with 10-m distance,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 35 – 41, Jan. 2006. [9] K. Kotani and T. Ito, “High efficiency CMOS rectifier circuit with selfVth-cancellation and power regulation functions for UHF RFIDs,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 119 –122, Nov. 2007. [10] X. Wang, B. Jiang, W. Che, N. Yan, and H. Min, “A high efficiency AC-DC charge pump using feedback compensation technique,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 252 –255, Nov. 2007. [11] A. Facen and A. Boni, “Power supply generation in CMOS passive UHF RFID tags,” Research in Microelectronics and Electronics, pp. 33 –36, 2006. [12] S. Mandal and R. Sarpeshkar, “Low-power CMOS rectifier design for RFID applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 6, pp. 1177 –1188, Jun. 2007. [13] A. SharifBakhtiar, M. Jalali, and S. Mirabbasi, “A high-efficiency CMOS rectifier for low-power RFID tags,” IEEE International Conference on RFID, pp. 83 –88, Apr. 2010.